1224          HReg argL = iselIntExpr_R(env, e->Iex.Binop.arg1);  in iselIntExpr_R_wrk()  local
1228          addInstr(env, mk_iMOVsd_RR(argL, hregAMD64_RDI()) );  in iselIntExpr_R_wrk()
1423          IRExpr* argL = e->Iex.Unop.arg->Iex.Binop.arg1;  in iselIntExpr_R_wrk()  local
1438             HReg reg      = iselIntExpr_R(env, argL);  in iselIntExpr_R_wrk()
2828          HReg argL = iselDblExpr(env, triop->arg2);  in iselDblExpr_wrk()  local
2830          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselDblExpr_wrk()
3365          HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);  in iselVecExpr_wrk()  local
3368          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselVecExpr_wrk()
3381          HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);  in iselVecExpr_wrk()  local
3384          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselVecExpr_wrk()
3400          HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);  in iselVecExpr_wrk()  local
3403          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselVecExpr_wrk()
3419          HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);  in iselVecExpr_wrk()  local
3422          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselVecExpr_wrk()
3561          HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);  in iselVecExpr_wrk()  local
3588          addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,  in iselVecExpr_wrk()
3613          HReg argL = iselVecExpr(env, e->Iex.Binop.arg1);  in iselVecExpr_wrk()  local
3636          addInstr(env, AMD64Instr_SseLdSt(False/*!isLoad*/, 16, argL,  in iselVecExpr_wrk()
3668          HReg argL = iselVecExpr(env, triop->arg2);  in iselVecExpr_wrk()  local
3671          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselVecExpr_wrk()
3684          HReg argL = iselVecExpr(env, triop->arg2);  in iselVecExpr_wrk()  local
3687          addInstr(env, mk_vMOVsd_RR(argL, dst));  in iselVecExpr_wrk()