Lines Matching refs:VBinS
1124 i->ARM64in.VBinS.op = op; in ARM64Instr_VBinS()
1125 i->ARM64in.VBinS.dst = dst; in ARM64Instr_VBinS()
1126 i->ARM64in.VBinS.argL = argL; in ARM64Instr_VBinS()
1127 i->ARM64in.VBinS.argR = argR; in ARM64Instr_VBinS()
1709 vex_printf("f%s ", showARM64FpBinOp(i->ARM64in.VBinS.op)); in ppARM64Instr()
1710 ppHRegARM64asSreg(i->ARM64in.VBinS.dst); in ppARM64Instr()
1712 ppHRegARM64asSreg(i->ARM64in.VBinS.argL); in ppARM64Instr()
1714 ppHRegARM64asSreg(i->ARM64in.VBinS.argR); in ppARM64Instr()
2126 addHRegUse(u, HRmWrite, i->ARM64in.VBinS.dst); in getRegUsage_ARM64Instr()
2127 addHRegUse(u, HRmRead, i->ARM64in.VBinS.argL); in getRegUsage_ARM64Instr()
2128 addHRegUse(u, HRmRead, i->ARM64in.VBinS.argR); in getRegUsage_ARM64Instr()
2371 i->ARM64in.VBinS.dst = lookupHRegRemap(m, i->ARM64in.VBinS.dst); in mapRegs_ARM64Instr()
2372 i->ARM64in.VBinS.argL = lookupHRegRemap(m, i->ARM64in.VBinS.argL); in mapRegs_ARM64Instr()
2373 i->ARM64in.VBinS.argR = lookupHRegRemap(m, i->ARM64in.VBinS.argR); in mapRegs_ARM64Instr()
4123 UInt sD = dregEnc(i->ARM64in.VBinS.dst); in emit_ARM64Instr()
4124 UInt sN = dregEnc(i->ARM64in.VBinS.argL); in emit_ARM64Instr()
4125 UInt sM = dregEnc(i->ARM64in.VBinS.argR); in emit_ARM64Instr()
4127 switch (i->ARM64in.VBinS.op) { in emit_ARM64Instr()