Lines Matching refs:X00
2624 #define X00 BITS4(0,0, 0,0) macro
2956 *p++ = X_3_6_2_16_5(X110, X100101, X00, 0/*imm16*/, xD); in imm64_to_ireg()
3058 UInt instr = X_2_6_3_9_2_5_5(X00, X111000, isLoad ? X010 : X000, in do_load_or_store8()
3059 simm9 & 0x1FF, X00, in do_load_or_store8()
3073 UInt instr = X_2_6_2_12_5_5(X00, X111001, isLoad ? X01 : X00, in do_load_or_store8()
3108 simm9 & 0x1FF, X00, in do_load_or_store16()
3122 UInt instr = X_2_6_2_12_5_5(X01, X111001, isLoad ? X01 : X00, in do_load_or_store16()
3157 simm9 & 0x1FF, X00, in do_load_or_store32()
3171 UInt instr = X_2_6_2_12_5_5(X10, X111001, isLoad ? X01 : X00, in do_load_or_store32()
3209 simm9 & 0x1FF, X00, xN, xD); in do_load_or_store64()
3222 UInt instr = X_2_6_2_12_5_5(X11, X111001, isLoad ? X01 : X00, in do_load_or_store64()
3273 argR->ARM64riA.I12.shift == 12 ? X01 : X00, in emit_ARM64Instr()
3301 argR->ARM64riA.I12.shift == 12 ? X01 : X00, in emit_ARM64Instr()
3725 *p++ = X_2_6_2_12_5_5(X10, X010001, X00, simm12, X11111, X11111); in emit_ARM64Instr()
3727 *p++ = X_2_6_2_12_5_5(X11, X010001, X00, -simm12, X11111, X11111); in emit_ARM64Instr()
3736 *p++ = X_2_6_2_12_5_5(X10, X010001, X00, 0, X11111, dd); in emit_ARM64Instr()
3819 *p++ = X_2_6_2_12_5_5(X01, X111101, isLD ? X01 : X00, in emit_ARM64Instr()
3836 *p++ = X_2_6_2_12_5_5(X10, X111101, isLD ? X01 : X00, in emit_ARM64Instr()
3853 *p++ = X_2_6_2_12_5_5(X11, X111101, isLD ? X01 : X00, in emit_ARM64Instr()