Lines Matching refs:X0100
2717 #define X0100 BITS4(0,1,0,0) macro
2977 case ARMalu_ADD: subopc = X0100; break; in emit_ARMInstr()
3544 case ARMvfp_MUL: pqrs = X0100; break; in emit_ARMInstr()
3569 case ARMvfp_MUL: pqrs = X0100; break; in emit_ARMInstr()
3590 insn = XXXXXXXX(0xE, X1110,X1011,X0000,dD,X1011,X0100,dM); in emit_ARMInstr()
3596 insn = XXXXXXXX(0xE, X1110,X1011,X0001,dD,X1011,X0100,dM); in emit_ARMInstr()
3641 UInt insn = XXXXXXXX(0xE, X1110, X1011, X0100, dD, X1011, X0100, dM); in emit_ARMInstr()
3651 UInt insn = XXXXXXXX(cc, X1110,X1011,X0000,dD,X1011,X0100,dM); in emit_ARMInstr()
3745 X1011, X0100, regD); in emit_ARMInstr()
3755 X1011, X0100, regD); in emit_ARMInstr()
3804 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), in emit_ARMInstr()
3824 insn = XXXXXXXX(0xF, X0100, BITS4(0, D, bL, 0), in emit_ARMInstr()
4062 regD, X0100, BITS4(1,Q,M,0), regM); in emit_ARMInstr()
4066 regD, X0100, BITS4(0,Q,M,0), regM); in emit_ARMInstr()
4174 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, in emit_ARMInstr()
4190 insn = XXXXXXXX(0xF, X0011, BITS4(1,D,1,1), X1011, regD, X0100, in emit_ARMInstr()
4487 X0100, BITS4(N,Q,M,0), regM); in emit_ARMInstr()
4491 X0100, BITS4(N,Q,M,0), regM); in emit_ARMInstr()
4495 X0100, BITS4(N,Q,M,1), regM); in emit_ARMInstr()
4499 X0100, BITS4(N,Q,M,1), regM); in emit_ARMInstr()
4861 #undef X0100