Lines Matching refs:vassert
94 #define X86ST(f) vassert(0)
102 #define AMD64ST(f) vassert(0)
110 #define PPC32ST(f) vassert(0)
118 #define PPC64ST(f) vassert(0)
126 #define S390ST(f) vassert(0)
134 #define ARMST(f) vassert(0)
142 #define ARM64ST(f) vassert(0)
150 #define MIPS32ST(f) vassert(0)
158 #define MIPS64ST(f) vassert(0)
166 #define TILEGXST(f) vassert(0)
223 vassert(!vex_initdone); in LibVEX_Init()
224 vassert(failure_exit); in LibVEX_Init()
225 vassert(log_bytes); in LibVEX_Init()
226 vassert(debuglevel >= 0); in LibVEX_Init()
228 vassert(vcon->iropt_verbosity >= 0); in LibVEX_Init()
229 vassert(vcon->iropt_level >= 0); in LibVEX_Init()
230 vassert(vcon->iropt_level <= 2); in LibVEX_Init()
231 vassert(vcon->iropt_unroll_thresh >= 0); in LibVEX_Init()
232 vassert(vcon->iropt_unroll_thresh <= 400); in LibVEX_Init()
233 vassert(vcon->guest_max_insns >= 1); in LibVEX_Init()
234 vassert(vcon->guest_max_insns <= 100); in LibVEX_Init()
235 vassert(vcon->guest_chase_thresh >= 0); in LibVEX_Init()
236 vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); in LibVEX_Init()
237 vassert(vcon->guest_chase_cond == True in LibVEX_Init()
246 vassert(1 == sizeof(UChar)); in LibVEX_Init()
247 vassert(1 == sizeof(Char)); in LibVEX_Init()
248 vassert(2 == sizeof(UShort)); in LibVEX_Init()
249 vassert(2 == sizeof(Short)); in LibVEX_Init()
250 vassert(4 == sizeof(UInt)); in LibVEX_Init()
251 vassert(4 == sizeof(Int)); in LibVEX_Init()
252 vassert(8 == sizeof(ULong)); in LibVEX_Init()
253 vassert(8 == sizeof(Long)); in LibVEX_Init()
254 vassert(4 == sizeof(Float)); in LibVEX_Init()
255 vassert(8 == sizeof(Double)); in LibVEX_Init()
256 vassert(1 == sizeof(Bool)); in LibVEX_Init()
257 vassert(4 == sizeof(Addr32)); in LibVEX_Init()
258 vassert(8 == sizeof(Addr64)); in LibVEX_Init()
259 vassert(16 == sizeof(U128)); in LibVEX_Init()
260 vassert(16 == sizeof(V128)); in LibVEX_Init()
261 vassert(32 == sizeof(U256)); in LibVEX_Init()
263 vassert(sizeof(void*) == 4 || sizeof(void*) == 8); in LibVEX_Init()
264 vassert(sizeof(void*) == sizeof(int*)); in LibVEX_Init()
265 vassert(sizeof(void*) == sizeof(HWord)); in LibVEX_Init()
266 vassert(sizeof(void*) == sizeof(Addr)); in LibVEX_Init()
267 vassert(sizeof(unsigned long) == sizeof(SizeT)); in LibVEX_Init()
269 vassert(VEX_HOST_WORDSIZE == sizeof(void*)); in LibVEX_Init()
270 vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); in LibVEX_Init()
275 vassert(sizeof(IRExpr) == 16); in LibVEX_Init()
276 vassert(sizeof(IRStmt) == 20 /* x86 */ in LibVEX_Init()
279 vassert(sizeof(IRExpr) == 32); in LibVEX_Init()
280 vassert(sizeof(IRStmt) == 32); in LibVEX_Init()
284 vassert(sizeof(HReg) == 4); in LibVEX_Init()
288 vassert(N_RREGUNIVERSE_REGS == 64); in LibVEX_Init()
294 vassert(udiv32(100, 7) == 14); in LibVEX_Init()
295 vassert(sdiv32(100, 7) == 14); in LibVEX_Init()
296 vassert(sdiv32(-100, 7) == -14); /* and not -15 */ in LibVEX_Init()
297 vassert(sdiv32(100, -7) == -14); /* ditto */ in LibVEX_Init()
298 vassert(sdiv32(-100, -7) == 14); /* not sure what this proves */ in LibVEX_Init()
388 vassert(vex_initdone); in LibVEX_Translate()
389 vassert(vta->needs_self_check != NULL); in LibVEX_Translate()
390 vassert(vta->disp_cp_xassisted != NULL); in LibVEX_Translate()
393 vassert(vta->disp_cp_chain_me_to_fastEP != NULL); in LibVEX_Translate()
394 vassert(vta->disp_cp_xindir != NULL); in LibVEX_Translate()
397 vassert(vta->disp_cp_chain_me_to_fastEP == NULL); in LibVEX_Translate()
398 vassert(vta->disp_cp_xindir == NULL); in LibVEX_Translate()
424 vassert(vta->archinfo_host.endness == VexEndnessLE); in LibVEX_Translate()
441 vassert(vta->archinfo_host.endness == VexEndnessLE); in LibVEX_Translate()
458 vassert(vta->archinfo_host.endness == VexEndnessBE); in LibVEX_Translate()
475 vassert(vta->archinfo_host.endness == VexEndnessBE || in LibVEX_Translate()
496 vassert(vta->archinfo_host.endness == VexEndnessBE); in LibVEX_Translate()
513 vassert(vta->archinfo_host.endness == VexEndnessLE); in LibVEX_Translate()
530 vassert(vta->archinfo_host.endness == VexEndnessLE); in LibVEX_Translate()
547 vassert(vta->archinfo_host.endness == VexEndnessLE in LibVEX_Translate()
565 vassert(vta->archinfo_host.endness == VexEndnessLE in LibVEX_Translate()
583 vassert(vta->archinfo_host.endness == VexEndnessLE); in LibVEX_Translate()
610 vassert(vta->archinfo_guest.endness == VexEndnessLE); in LibVEX_Translate()
611 vassert(0 == sizeof(VexGuestX86State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
612 vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4); in LibVEX_Translate()
613 vassert(sizeof( ((VexGuestX86State*)0)->guest_CMLEN ) == 4); in LibVEX_Translate()
614 vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); in LibVEX_Translate()
631 vassert(vta->archinfo_guest.endness == VexEndnessLE); in LibVEX_Translate()
632 vassert(0 == sizeof(VexGuestAMD64State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
633 vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8); in LibVEX_Translate()
634 vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMLEN ) == 8); in LibVEX_Translate()
635 vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); in LibVEX_Translate()
652 vassert(vta->archinfo_guest.endness == VexEndnessBE); in LibVEX_Translate()
653 vassert(0 == sizeof(VexGuestPPC32State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
654 vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4); in LibVEX_Translate()
655 vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMLEN ) == 4); in LibVEX_Translate()
656 vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); in LibVEX_Translate()
673 vassert(vta->archinfo_guest.endness == VexEndnessBE || in LibVEX_Translate()
675 vassert(0 == sizeof(VexGuestPPC64State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
676 vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMSTART ) == 8); in LibVEX_Translate()
677 vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMLEN ) == 8); in LibVEX_Translate()
678 vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); in LibVEX_Translate()
679 vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); in LibVEX_Translate()
696 vassert(vta->archinfo_guest.endness == VexEndnessBE); in LibVEX_Translate()
697 vassert(0 == sizeof(VexGuestS390XState) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
698 vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8); in LibVEX_Translate()
699 vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8); in LibVEX_Translate()
700 vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); in LibVEX_Translate()
717 vassert(vta->archinfo_guest.endness == VexEndnessLE); in LibVEX_Translate()
718 vassert(0 == sizeof(VexGuestARMState) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
719 vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4); in LibVEX_Translate()
720 vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4); in LibVEX_Translate()
721 vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); in LibVEX_Translate()
738 vassert(vta->archinfo_guest.endness == VexEndnessLE); in LibVEX_Translate()
739 vassert(0 == sizeof(VexGuestARM64State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
740 vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8); in LibVEX_Translate()
741 vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMLEN ) == 8); in LibVEX_Translate()
742 vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8); in LibVEX_Translate()
759 vassert(vta->archinfo_guest.endness == VexEndnessLE in LibVEX_Translate()
761 vassert(0 == sizeof(VexGuestMIPS32State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
762 vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMSTART) == 4); in LibVEX_Translate()
763 vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMLEN ) == 4); in LibVEX_Translate()
764 vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); in LibVEX_Translate()
781 vassert(vta->archinfo_guest.endness == VexEndnessLE in LibVEX_Translate()
783 vassert(0 == sizeof(VexGuestMIPS64State) % LibVEX_GUEST_STATE_ALIGN); in LibVEX_Translate()
784 vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMSTART) == 8); in LibVEX_Translate()
785 vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMLEN ) == 8); in LibVEX_Translate()
786 vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8); in LibVEX_Translate()
803 vassert(vta->archinfo_guest.endness == VexEndnessLE); in LibVEX_Translate()
804 vassert(0 == in LibVEX_Translate()
806 vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_CMSTART ) == 8); in LibVEX_Translate()
807 vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_CMLEN ) == 8); in LibVEX_Translate()
808 vassert(sizeof( ((VexGuestTILEGXState*)0)->guest_NRADDR ) == 8); in LibVEX_Translate()
832 vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); in LibVEX_Translate()
834 vassert(vta->archinfo_guest.endness == vta->archinfo_host.endness); in LibVEX_Translate()
845 vassert(pxControl >= VexRegUpdSpAtMemAccess in LibVEX_Translate()
879 vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); in LibVEX_Translate()
880 vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); in LibVEX_Translate()
882 vassert(vta->guest_extents->len[i] < 10000); /* sanity */ in LibVEX_Translate()
886 vassert(pxControl >= VexRegUpdSpAtMemAccess in LibVEX_Translate()
1012 vassert(irsb->offsIP >= 16); in LibVEX_Translate()
1099 vassert(vta->addProfInc); /* else where did it come from? */ in LibVEX_Translate()
1100 vassert(res.offs_profInc == -1); /* there can be only one (tm) */ in LibVEX_Translate()
1101 vassert(out_used >= 0); in LibVEX_Translate()
1194 vassert(0); in LibVEX_Chain()
1258 vassert(0); in LibVEX_UnChain()
1288 vassert(0); in LibVEX_evCheckSzB()
1332 vassert(0); in LibVEX_PatchProfInc()