140     WriteBackMemAccess } CacheModelResult;  typedef
142 typedef CacheModelResult (*simcall_type)(Addr, UChar);
316 CacheModelResult cachesim_I1_ref(Addr a, UChar size)  in cachesim_I1_ref()
324 CacheModelResult cachesim_D1_ref(Addr a, UChar size)  in cachesim_D1_ref()
424 CacheModelResult cachesim_I1_Read(Addr a, UChar size)  in cachesim_I1_Read()
436 CacheModelResult cachesim_D1_Read(Addr a, UChar size)  in cachesim_D1_Read()
448 CacheModelResult cachesim_D1_Write(Addr a, UChar size)  in cachesim_D1_Write()
531 CacheModelResult prefetch_I1_ref(Addr a, UChar size)  in prefetch_I1_ref()
540 CacheModelResult prefetch_D1_ref(Addr a, UChar size)  in prefetch_D1_ref()
552 CacheModelResult prefetch_I1_Read(Addr a, UChar size)  in prefetch_I1_Read()
565 CacheModelResult prefetch_D1_Read(Addr a, UChar size)  in prefetch_D1_Read()
578 CacheModelResult prefetch_D1_Write(Addr a, UChar size)  in prefetch_D1_Write()
687 static CacheModelResult cacheuse##_##L##_doRead(Addr a, UChar size)         \
883 CacheModelResult cacheuse_LL_access(Addr memline, line_loaded* l1_loaded)  in cacheuse_LL_access()
939 static CacheModelResult update##_##L##_use(cache_t2* cache, int idx, \
1022 void inc_costs(CacheModelResult r, ULong* c1, ULong* c2)  in inc_costs()
1049 const HChar* cacheRes(CacheModelResult r)  in cacheRes()
1065     CacheModelResult IrRes;  in log_1I0D()
1089     CacheModelResult Ir1Res, Ir2Res;  in log_2I0D()
1122     CacheModelResult Ir1Res, Ir2Res, Ir3Res;  in log_3I0D()
1162     CacheModelResult IrRes, DrRes;  in log_1I1Dr()
1198     CacheModelResult DrRes;  in log_0I1Dr()
1225     CacheModelResult IrRes, DwRes;  in log_1I1Dw()
1258     CacheModelResult DwRes;  in log_0I1Dw()