62   Addr memline, iaddr;  member
162       c->loaded[i].memline  = 0;  in cachesim_clearcache()
715 		 idx, L.loaded[idx].memline,  L.loaded[idx].iaddr,          \
732 		 i, idx, L.loaded[idx].memline,  L.loaded[idx].iaddr,       \
759 		 idx, L.loaded[idx].memline,  L.loaded[idx].iaddr,          \
774 		 i, idx, L.loaded[idx].memline,  L.loaded[idx].iaddr,       \
796 		 idx, L.loaded[idx].memline,  L.loaded[idx].iaddr,          \
811 		 i, idx, L.loaded[idx].memline,  L.loaded[idx].iaddr,       \
852 static void update_LL_use(int idx, Addr memline)  in update_LL_use()  argument
859            idx, CLG_(bb_base) + current_ii->instr_offset, memline);  in update_LL_use()
862 	     use->count, i, use->mask, loaded->memline, loaded->iaddr);  in update_LL_use()
875   loaded->memline = memline;  in update_LL_use()
883 CacheModelResult cacheuse_LL_access(Addr memline, line_loaded* l1_loaded)  in cacheuse_LL_access()  argument
885    UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1);  in cacheuse_LL_access()
887    UWord tag  = memline & LL.tag_mask;  in cacheuse_LL_access()
892    CLG_DEBUG(6,"LL.Acc(Memline %#lx): Set %u\n", memline, setNo);  in cacheuse_LL_access()
899 		 idx, LL.loaded[idx].memline,  LL.loaded[idx].iaddr,  in cacheuse_LL_access()
914 		 i, idx, LL.loaded[idx].memline,  LL.loaded[idx].iaddr,  in cacheuse_LL_access()
929    update_LL_use(idx, memline);  in cacheuse_LL_access()
940 			       UInt mask, Addr memline)		     \
947            cache->name, idx, CLG_(bb_base) + current_ii->instr_offset, memline, mask); \
950 	     use->count, c, use->mask, loaded->memline, loaded->iaddr);	\
966   loaded->memline = memline;                                         \
972   if (memline == 0) return LL_Hit;                                   \
973   return cacheuse_LL_access(memline, loaded);                        \