Lines Matching refs:sets_min_1
75 int sets_min_1; member
184 c->sets_min_1 = c->sets - 1; in cachesim_initcache()
288 UInt set1 = block1 & c->sets_min_1; in cachesim_ref()
299 UInt set2 = block2 & c->sets_min_1; in cachesim_ref()
395 UInt set1 = ( a >> c->line_size_bits) & (c->sets_min_1); in cachesim_ref_wb()
396 UInt set2 = ((a+size-1) >> c->line_size_bits) & (c->sets_min_1); in cachesim_ref_wb()
405 else if (((set1 + 1) & (c->sets_min_1)) == set2) { in cachesim_ref_wb()
689 UInt set1 = ( a >> L.line_size_bits) & (L.sets_min_1); \
690 UInt set2 = ((a+size-1) >> L.line_size_bits) & (L.sets_min_1); \
750 } else if (((set1 + 1) & (L.sets_min_1)) == set2) { \
885 UInt setNo = (memline >> LL.line_size_bits) & (LL.sets_min_1); in cacheuse_LL_access()