60    if (ci->num_levels < cache.level) ci->num_levels = cache.level;  in add_cache()
65 #define add_icache(level, size, assoc, linesize) \  argument
68                 VEX_CACHE_INIT(INSN_CACHE, level, size, linesize, assoc)); \
71 #define add_dcache(level, size, assoc, linesize) \  argument
74                 VEX_CACHE_INIT(DATA_CACHE, level, size, linesize, assoc)); \
77 #define add_ucache(level, size, assoc, linesize) \  argument
80                 VEX_CACHE_INIT(UNIFIED_CACHE, level, size, linesize, assoc)); \
83 #define add_itcache(level, size, assoc) \  argument
86           VEX_CACHE_INIT(INSN_CACHE, level, size, 0, assoc); \
113 Intel_cache_info(Int level, VexCacheInfo *ci)  in Intel_cache_info()  argument
122    if (level < 2) {  in Intel_cache_info()
124                     "processor (%d)\n", level);  in Intel_cache_info()
487    UInt level;  in get_caches_from_CPUID()  local
492    VG_(cpuid)(0, 0, &level, (UInt*)&vendor_id[0],  in get_caches_from_CPUID()
496    if (0 == level) {    // CPUID level is 0, early Pentium?  in get_caches_from_CPUID()
502       ret = Intel_cache_info(level, ci);  in get_caches_from_CPUID()
569 get_cache_info_for_level(ULong topology, UInt level)  in get_cache_info_for_level()  argument
571    return (topology >> (56 - level * 8)) & 0xff;  in get_cache_info_for_level()
575 get_line_size(UInt level, Bool is_insn_cache)  in get_line_size()  argument
577    return ecag(1, level, is_insn_cache);  in get_line_size()
581 get_total_size(UInt level, Bool is_insn_cache)  in get_total_size()  argument
583    return ecag(2, level, is_insn_cache);  in get_total_size()
587 get_associativity(UInt level, Bool is_insn_cache)  in get_associativity()  argument
589    return ecag(3, level, is_insn_cache);  in get_associativity()
593 get_cache(UInt level, VexCacheKind kind)  in get_cache()  argument
596    UInt size = get_total_size(level, is_insn_cache);  in get_cache()
597    UInt line_size = get_line_size(level, is_insn_cache);  in get_cache()
598    UInt assoc = get_associativity(level, is_insn_cache);  in get_cache()
600    return VEX_CACHE_INIT(kind, level + 1, size, line_size, assoc);  in get_cache()
615    UInt level, cache_kind, info, i;  in get_cache_info()  local
622    for (level = 0; level < 8; level++) {  in get_cache_info()
623       info = get_cache_info_for_level(topology, level);  in get_cache_info()
640    for (level = 0; level < ci->num_levels; level++) {  in get_cache_info()
641       info = get_cache_info_for_level(topology, level);  in get_cache_info()
645          ci->caches[i++] = get_cache(level, INSN_CACHE);  in get_cache_info()
646          ci->caches[i++] = get_cache(level, DATA_CACHE);  in get_cache_info()
650          ci->caches[i++] = get_cache(level, INSN_CACHE);  in get_cache_info()
654          ci->caches[i++] = get_cache(level, DATA_CACHE);  in get_cache_info()
658          ci->caches[i++] = get_cache(level, UNIFIED_CACHE);  in get_cache_info()
691       VG_(debugLog)(1, "cache", "        level = %u\n", c->level);  in write_cache_info()
701    UInt level, i;  in cache_info_is_sensible()  local
707    for (level = 1; level <= ci->num_levels; ++level) {  in cache_info_is_sensible()
712          if (ci->caches[i].level == level) {  in cache_info_is_sensible()
721          VG_(debugLog)(1, "cache", "warning: No caches at level %u\n", level);  in cache_info_is_sensible()
726                        "kind at level %u\n", level);  in cache_info_is_sensible()
731                        "at level %u\n", level);  in cache_info_is_sensible()
737    for (level = 2; level <= ci->num_levels; ++level) {  in cache_info_is_sensible()
740          if (ci->caches[i].level == level - 1) {  in cache_info_is_sensible()
747                        "at level %u\n", level, level - 1);  in cache_info_is_sensible()