Lines Matching refs:i32
1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
10 declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
11 declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
12 declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
13 declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
19 declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
20 declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
21 declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
22 declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
27 declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
28 declare <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
31 declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
32 declare <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
35 declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
36 declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
55 %1 = insertelement <4 x float> undef, float %in, i32 0
56 %2 = insertelement <4 x float> %1, float %in, i32 1
57 %3 = insertelement <4 x float> %2, float %in, i32 2
58 %4 = insertelement <4 x float> %3, float %in, i32 3
62 define internal <4 x i32> @smear_4i(i32 %in) nounwind readnone alwaysinline {
63 %1 = insertelement <4 x i32> undef, i32 %in, i32 0
64 %2 = insertelement <4 x i32> %1, i32 %in, i32 1
65 %3 = insertelement <4 x i32> %2, i32 %in, i32 2
66 %4 = insertelement <4 x i32> %3, i32 %in, i32 3
67 ret <4 x i32> %4
71 %1 = insertelement <4 x i16> undef, i16 %in, i32 0
72 %2 = insertelement <4 x i16> %1, i16 %in, i32 1
73 %3 = insertelement <4 x i16> %2, i16 %in, i32 2
74 %4 = insertelement <4 x i16> %3, i16 %in, i32 3
81 %1 = insertelement <2 x float> undef, float %in, i32 0
82 %2 = insertelement <2 x float> %1, float %in, i32 1
86 define internal <2 x i32> @smear_2i(i32 %in) nounwind readnone alwaysinline {
87 %1 = insertelement <2 x i32> undef, i32 %in, i32 0
88 %2 = insertelement <2 x i32> %1, i32 %in, i32 1
89 ret <2 x i32> %2
93 %1 = insertelement <2 x i16> undef, i16 %in, i32 0
94 %2 = insertelement <2 x i16> %1, i16 %in, i32 1
99 define internal <4 x i32> @smear_4i32(i32 %in) nounwind readnone alwaysinline {
100 %1 = insertelement <4 x i32> undef, i32 %in, i32 0
101 %2 = insertelement <4 x i32> %1, i32 %in, i32 1
102 %3 = insertelement <4 x i32> %2, i32 %in, i32 2
103 %4 = insertelement <4 x i32> %3, i32 %in, i32 3
104 ret <4 x i32> %4
126 …value = shufflevector <3 x float> %value, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
127 %_low = shufflevector <3 x float> %low, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
128 …%_high = shufflevector <3 x float> %high, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
131 %c = shufflevector <4 x float> %b, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
136 …value = shufflevector <3 x float> %value, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
141 %c = shufflevector <4 x float> %b, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
169 define <4 x i32> @_Z5clampDv4_iS_S_(<4 x i32> %value, <4 x i32> %low, <4 x i32> %high) nounwind rea…
170 …%1 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %value, <4 x i32> %high) nounwind re…
171 …%2 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %1, <4 x i32> %low) nounwind readnone
172 ret <4 x i32> %2
175 define <4 x i32> @_Z5clampDv4_iii(<4 x i32> %value, i32 %low, i32 %high) nounwind readonly {
176 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
177 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
178 …%1 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %value, <4 x i32> %_high) nounwind r…
179 …%2 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %1, <4 x i32> %_low) nounwind readno…
180 ret <4 x i32> %2
183 define <3 x i32> @_Z5clampDv3_iS_S_(<3 x i32> %value, <3 x i32> %low, <3 x i32> %high) nounwind rea…
184 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
185 %_low = shufflevector <3 x i32> %low, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
186 %_high = shufflevector <3 x i32> %high, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
187 …%a = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwind …
188 …%b = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind readno…
189 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
190 ret <3 x i32> %c
193 define <3 x i32> @_Z5clampDv3_iii(<3 x i32> %value, i32 %low, i32 %high) nounwind readonly {
194 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
195 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
196 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
197 …%a = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwind …
198 …%b = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind readno…
199 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
200 ret <3 x i32> %c
203 define <2 x i32> @_Z5clampDv2_iS_S_(<2 x i32> %value, <2 x i32> %low, <2 x i32> %high) nounwind rea…
204 …%1 = tail call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %value, <2 x i32> %high) nounwind re…
205 …%2 = tail call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %1, <2 x i32> %low) nounwind readnone
206 ret <2 x i32> %2
209 define <2 x i32> @_Z5clampDv2_iii(<2 x i32> %value, i32 %low, i32 %high) nounwind readonly {
210 %_high = tail call <2 x i32> @smear_2i(i32 %high) nounwind readnone
211 %_low = tail call <2 x i32> @smear_2i(i32 %low) nounwind readnone
212 …%a = tail call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %value, <2 x i32> %_high) nounwind r…
213 …%b = tail call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %a, <2 x i32> %_low) nounwind readno…
214 ret <2 x i32> %b
219 define <4 x i32> @_Z5clampDv4_jS_S_(<4 x i32> %value, <4 x i32> %low, <4 x i32> %high) nounwind rea…
220 …%1 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %value, <4 x i32> %high) nounwind re…
221 …%2 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %1, <4 x i32> %low) nounwind readnone
222 ret <4 x i32> %2
225 define <4 x i32> @_Z5clampDv4_jjj(<4 x i32> %value, i32 %low, i32 %high) nounwind readonly {
226 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
227 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
228 …%1 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %value, <4 x i32> %_high) nounwind r…
229 …%2 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %1, <4 x i32> %_low) nounwind readno…
230 ret <4 x i32> %2
233 define <3 x i32> @_Z5clampDv3_jS_S_(<3 x i32> %value, <3 x i32> %low, <3 x i32> %high) nounwind rea…
234 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
235 %_low = shufflevector <3 x i32> %low, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
236 %_high = shufflevector <3 x i32> %high, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
237 …%a = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwind …
238 …%b = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind readno…
239 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
240 ret <3 x i32> %c
243 define <3 x i32> @_Z5clampDv3_jjj(<3 x i32> %value, i32 %low, i32 %high) nounwind readonly {
244 %_value = shufflevector <3 x i32> %value, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
245 %_high = tail call <4 x i32> @smear_4i(i32 %high) nounwind readnone
246 %_low = tail call <4 x i32> @smear_4i(i32 %low) nounwind readnone
247 …%a = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %_value, <4 x i32> %_high) nounwind …
248 …%b = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %a, <4 x i32> %_low) nounwind readno…
249 %c = shufflevector <4 x i32> %b, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
250 ret <3 x i32> %c
253 define <2 x i32> @_Z5clampDv2_jS_S_(<2 x i32> %value, <2 x i32> %low, <2 x i32> %high) nounwind rea…
254 …%1 = tail call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %value, <2 x i32> %high) nounwind re…
255 …%2 = tail call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %1, <2 x i32> %low) nounwind readnone
256 ret <2 x i32> %2
259 define <2 x i32> @_Z5clampDv2_jjj(<2 x i32> %value, i32 %low, i32 %high) nounwind readonly {
260 %_high = tail call <2 x i32> @smear_2i(i32 %high) nounwind readnone
261 %_low = tail call <2 x i32> @smear_2i(i32 %low) nounwind readnone
262 …%a = tail call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %value, <2 x i32> %_high) nounwind r…
263 …%b = tail call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %a, <2 x i32> %_low) nounwind readno…
264 ret <2 x i32> %b
284 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
285 %2 = shufflevector <3 x float> %v2, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
287 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
292 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
295 %c = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
333 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
334 %2 = shufflevector <3 x float> %v2, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
336 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
341 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
344 %c = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
377 %1 = sext <2 x i8> %v1 to <2 x i32>
378 %2 = sext <2 x i8> %v2 to <2 x i32>
379 %3 = tail call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
380 %4 = trunc <2 x i32> %3 to <2 x i8>
385 %1 = sext <3 x i8> %v1 to <3 x i32>
386 %2 = sext <3 x i8> %v2 to <3 x i32>
387 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
388 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
389 %5 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
390 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
391 %7 = trunc <3 x i32> %6 to <3 x i8>
396 %1 = sext <4 x i8> %v1 to <4 x i32>
397 %2 = sext <4 x i8> %v2 to <4 x i32>
398 %3 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
399 %4 = trunc <4 x i32> %3 to <4 x i8>
410 %1 = sext <2 x i16> %v1 to <2 x i32>
411 %2 = sext <2 x i16> %v2 to <2 x i32>
412 %3 = tail call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
413 %4 = trunc <2 x i32> %3 to <2 x i16>
418 %1 = sext <3 x i16> %v1 to <3 x i32>
419 %2 = sext <3 x i16> %v2 to <3 x i32>
420 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
421 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
422 %5 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
423 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
424 %7 = trunc <3 x i32> %6 to <3 x i16>
429 %1 = sext <4 x i16> %v1 to <4 x i32>
430 %2 = sext <4 x i16> %v2 to <4 x i32>
431 %3 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
432 %4 = trunc <4 x i32> %3 to <4 x i16>
436 define i32 @_Z3maxii(i32 %v1, i32 %v2) nounwind readnone {
437 %1 = icmp sgt i32 %v1, %v2
438 %2 = select i1 %1, i32 %v1, i32 %v2
439 ret i32 %2
442 define <2 x i32> @_Z3maxDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
443 …%1 = tail call <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
444 ret <2 x i32> %1
447 define <3 x i32> @_Z3maxDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
448 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
449 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
450 …%3 = tail call <4 x i32 > @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
451 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
452 ret <3 x i32> %4
455 define <4 x i32> @_Z3maxDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
456 …%1 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
457 ret <4 x i32> %1
475 %1 = zext <2 x i8> %v1 to <2 x i32>
476 %2 = zext <2 x i8> %v2 to <2 x i32>
477 %3 = tail call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
478 %4 = trunc <2 x i32> %3 to <2 x i8>
483 %1 = zext <3 x i8> %v1 to <3 x i32>
484 %2 = zext <3 x i8> %v2 to <3 x i32>
485 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
486 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
487 %5 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
488 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
489 %7 = trunc <3 x i32> %6 to <3 x i8>
494 %1 = zext <4 x i8> %v1 to <4 x i32>
495 %2 = zext <4 x i8> %v2 to <4 x i32>
496 %3 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
497 %4 = trunc <4 x i32> %3 to <4 x i8>
508 %1 = zext <2 x i16> %v1 to <2 x i32>
509 %2 = zext <2 x i16> %v2 to <2 x i32>
510 %3 = tail call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
511 %4 = trunc <2 x i32> %3 to <2 x i16>
516 %1 = zext <3 x i16> %v1 to <3 x i32>
517 %2 = zext <3 x i16> %v2 to <3 x i32>
518 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
519 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
520 %5 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
521 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
522 %7 = trunc <3 x i32> %6 to <3 x i16>
527 %1 = zext <4 x i16> %v1 to <4 x i32>
528 %2 = zext <4 x i16> %v2 to <4 x i32>
529 %3 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
530 %4 = trunc <4 x i32> %3 to <4 x i16>
534 define i32 @_Z3maxjj(i32 %v1, i32 %v2) nounwind readnone {
535 %1 = icmp ugt i32 %v1, %v2
536 %2 = select i1 %1, i32 %v1, i32 %v2
537 ret i32 %2
540 define <2 x i32> @_Z3maxDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
541 …%1 = tail call <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
542 ret <2 x i32> %1
545 define <3 x i32> @_Z3maxDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
546 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
547 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
548 …%3 = tail call <4 x i32 > @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
549 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
550 ret <3 x i32> %4
553 define <4 x i32> @_Z3maxDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
554 …%1 = tail call <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
555 ret <4 x i32> %1
608 %1 = sext <2 x i8> %v1 to <2 x i32>
609 %2 = sext <2 x i8> %v2 to <2 x i32>
610 %3 = tail call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
611 %4 = trunc <2 x i32> %3 to <2 x i8>
616 %1 = sext <3 x i8> %v1 to <3 x i32>
617 %2 = sext <3 x i8> %v2 to <3 x i32>
618 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
619 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
620 %5 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
621 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
622 %7 = trunc <3 x i32> %6 to <3 x i8>
627 %1 = sext <4 x i8> %v1 to <4 x i32>
628 %2 = sext <4 x i8> %v2 to <4 x i32>
629 %3 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
630 %4 = trunc <4 x i32> %3 to <4 x i8>
641 %1 = sext <2 x i16> %v1 to <2 x i32>
642 %2 = sext <2 x i16> %v2 to <2 x i32>
643 %3 = tail call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
644 %4 = trunc <2 x i32> %3 to <2 x i16>
649 %1 = sext <3 x i16> %v1 to <3 x i32>
650 %2 = sext <3 x i16> %v2 to <3 x i32>
651 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
652 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
653 %5 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
654 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
655 %7 = trunc <3 x i32> %6 to <3 x i16>
660 %1 = sext <4 x i16> %v1 to <4 x i32>
661 %2 = sext <4 x i16> %v2 to <4 x i32>
662 %3 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
663 %4 = trunc <4 x i32> %3 to <4 x i16>
667 define i32 @_Z3minii(i32 %v1, i32 %v2) nounwind readnone {
668 %1 = icmp slt i32 %v1, %v2
669 %2 = select i1 %1, i32 %v1, i32 %v2
670 ret i32 %2
673 define <2 x i32> @_Z3minDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
674 …%1 = tail call <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
675 ret <2 x i32> %1
678 define <3 x i32> @_Z3minDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
679 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
680 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
681 …%3 = tail call <4 x i32 > @llvm.arm.neon.vmins.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
682 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
683 ret <3 x i32> %4
686 define <4 x i32> @_Z3minDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
687 …%1 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
688 ret <4 x i32> %1
706 %1 = zext <2 x i8> %v1 to <2 x i32>
707 %2 = zext <2 x i8> %v2 to <2 x i32>
708 %3 = tail call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
709 %4 = trunc <2 x i32> %3 to <2 x i8>
714 %1 = zext <3 x i8> %v1 to <3 x i32>
715 %2 = zext <3 x i8> %v2 to <3 x i32>
716 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
717 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
718 %5 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
719 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
720 %7 = trunc <3 x i32> %6 to <3 x i8>
725 %1 = zext <4 x i8> %v1 to <4 x i32>
726 %2 = zext <4 x i8> %v2 to <4 x i32>
727 %3 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
728 %4 = trunc <4 x i32> %3 to <4 x i8>
739 %1 = zext <2 x i16> %v1 to <2 x i32>
740 %2 = zext <2 x i16> %v2 to <2 x i32>
741 %3 = tail call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %1, <2 x i32> %2) nounwind readnone
742 %4 = trunc <2 x i32> %3 to <2 x i16>
747 %1 = zext <3 x i16> %v1 to <3 x i32>
748 %2 = zext <3 x i16> %v2 to <3 x i32>
749 %3 = shufflevector <3 x i32> %1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
750 %4 = shufflevector <3 x i32> %2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
751 %5 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %3, <4 x i32> %4) nounwind readnone
752 %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
753 %7 = trunc <3 x i32> %6 to <3 x i16>
758 %1 = zext <4 x i16> %v1 to <4 x i32>
759 %2 = zext <4 x i16> %v2 to <4 x i32>
760 %3 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readnone
761 %4 = trunc <4 x i32> %3 to <4 x i16>
765 define i32 @_Z3minjj(i32 %v1, i32 %v2) nounwind readnone {
766 %1 = icmp ult i32 %v1, %v2
767 %2 = select i1 %1, i32 %v1, i32 %v2
768 ret i32 %2
771 define <2 x i32> @_Z3minDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
772 …%1 = tail call <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone
773 ret <2 x i32> %1
776 define <3 x i32> @_Z3minDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
777 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
778 %2 = shufflevector <3 x i32> %v2, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
779 …%3 = tail call <4 x i32 > @llvm.arm.neon.vminu.v4i32(<4 x i32> %1, <4 x i32> %2) nounwind readno…
780 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
781 ret <3 x i32> %4
784 define <4 x i32> @_Z3minDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
785 …%1 = tail call <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone
786 ret <4 x i32> %1
832 @yuv_U = internal constant <4 x i32> <i32 0, i32 -100, i32 516, i32 0>, align 16
833 @yuv_V = internal constant <4 x i32> <i32 409, i32 -208, i32 0, i32 0>, align 16
834 @yuv_0 = internal constant <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
835 @yuv_255 = internal constant <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>, align 16
839 %_sy = zext i8 %pY to i32
840 %_su = zext i8 %pU to i32
841 %_sv = zext i8 %pV to i32
843 %_sy2 = add i32 -16, %_sy
844 %_sy3 = mul i32 298, %_sy2
845 %_su2 = add i32 -128, %_su
846 %_sv2 = add i32 -128, %_sv
847 %_y = tail call <4 x i32> @smear_4i32(i32 %_sy3) nounwind readnone
848 %_u = tail call <4 x i32> @smear_4i32(i32 %_su2) nounwind readnone
849 %_v = tail call <4 x i32> @smear_4i32(i32 %_sv2) nounwind readnone
851 %mu = load <4 x i32>, <4 x i32>* @yuv_U, align 8
852 %mv = load <4 x i32>, <4 x i32>* @yuv_V, align 8
853 %_u2 = mul <4 x i32> %_u, %mu
854 %_v2 = mul <4 x i32> %_v, %mv
855 %_y2 = add <4 x i32> %_y, %_u2
856 %_y3 = add <4 x i32> %_y2, %_v2
858 … call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %_y3, <4 x i32> <i32 8, i32 8, i32 8, i3…
862 %c0 = load <4 x i32>, <4 x i32>* @yuv_0, align 8
863 %c255 = load <4 x i32>, <4 x i32>* @yuv_255, align 8
864 …%r1 = tail call <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32> %_y3, <4 x i32> %c0) nounwind readn…
865 …%r2 = tail call <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32> %r1, <4 x i32> %c255) nounwind read…
866 %r3 = lshr <4 x i32> %r2, <i32 8, i32 8, i32 8, i32 8>
867 %r4 = trunc <4 x i32> %r3 to <4 x i8>
894 %1 = shufflevector <3 x float> %v, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
896 %3 = shufflevector <4 x float> %2, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
906 %1 = insertelement <2 x float> undef, float %v, i32 0
908 %3 = extractelement <2 x float> %2, i32 0
918 %1 = shufflevector <3 x float> %v, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
920 %3 = shufflevector <4 x float> %2, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
933 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
940 %1 = insertelement <4 x float> undef, float %in, i32 0
941 %2 = insertelement <4 x float> %1, float %in, i32 1
942 %3 = insertelement <4 x float> %2, float %in, i32 2
943 %4 = insertelement <4 x float> %3, float %in, i32 3
949 %x0 = extractelement <3 x float> %in, i32 0
951 %y0 = extractelement <3 x float> %in, i32 1
953 %z0 = extractelement <3 x float> %in, i32 2
956 %px = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 0
958 %xm = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %px2, i32 4) nounwind
960 %py = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 3
962 %ym = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %py2, i32 4) nounwind
964 %pz = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 5
966 %zm2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %pz2, i32 4) nounwind
967 %zm = shufflevector <4 x float> %zm2, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
974 %a6 = shufflevector <4 x float> %a5, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
979 %x0 = extractelement <2 x float> %in, i32 0
981 %y0 = extractelement <2 x float> %in, i32 1
984 %px = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 0
987 %py = getelementptr inbounds %struct.rs_matrix3x3, %struct.rs_matrix3x3* %m, i32 0, i32 0, i32 3
994 %a4 = shufflevector <4 x float> %a3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
999 %x0 = extractelement <4 x float> %in, i32 0
1001 %y0 = extractelement <4 x float> %in, i32 1
1003 %z0 = extractelement <4 x float> %in, i32 2
1005 %w0 = extractelement <4 x float> %in, i32 3
1008 %px = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 0
1011 %py = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 4
1014 %pz = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 8
1017 %pw = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 12
1032 %x0 = extractelement <3 x float> %in, i32 0
1034 %y0 = extractelement <3 x float> %in, i32 1
1036 %z0 = extractelement <3 x float> %in, i32 2
1039 %px = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 0
1042 %py = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 4
1045 %pz = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 8
1048 %pw = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 12
1062 %x0 = extractelement <2 x float> %in, i32 0
1064 %y0 = extractelement <2 x float> %in, i32 1
1067 %px = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 0
1070 %py = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 4
1073 %pw = getelementptr inbounds %struct.rs_matrix4x4, %struct.rs_matrix4x4* %m, i32 0, i32 0, i32 12
1112 %1 = shufflevector <3 x float> %color, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1113 %2 = insertelement <4 x float> %1, float 1.0, i32 3
1120 %1 = insertelement <4 x float> undef, float %r, i32 0
1121 %2 = insertelement <4 x float> %1, float %g, i32 1
1122 %3 = insertelement <4 x float> %2, float %b, i32 2
1123 %4 = insertelement <4 x float> %3, float 1.0, i32 3
1130 %1 = insertelement <4 x float> undef, float %r, i32 0
1131 %2 = insertelement <4 x float> %1, float %g, i32 1
1132 %3 = insertelement <4 x float> %2, float %b, i32 2
1133 %4 = insertelement <4 x float> %3, float %a, i32 3