Lines Matching refs:float
5 declare <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float>, <4 x float>) nounwind readnone
6 declare float @llvm.sqrt.f32(float) nounwind readnone
8 define float @_Z3dotDv4_fS_(<4 x float> %lhs, <4 x float> %rhs) nounwind readnone {
9 %1 = fmul <4 x float> %lhs, %rhs
10 …%2 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %1, <4 x float> %1) nounwind readnone
11 …%3 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x float> %2) nounwind readnone
12 %4 = extractelement <4 x float> %3, i32 0
13 ret float %4
16 define float @_Z3dotDv3_fS_(<3 x float> %lhs, <3 x float> %rhs) nounwind readnone {
17 %1 = fmul <3 x float> %lhs, %rhs
18 %2 = shufflevector <3 x float> %1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
19 %3 = bitcast <4 x float> %2 to <2 x i64>
21 %5 = bitcast <2 x i64> %4 to <4 x float>
22 …%6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %5, <4 x float> %5) nounwind readnone
23 …%7 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %6, <4 x float> %6) nounwind readnone
24 %8 = extractelement <4 x float> %7, i32 0
25 ret float %8
28 define float @_Z3dotDv2_fS_(<2 x float> %lhs, <2 x float> %rhs) nounwind readnone {
29 %1 = fmul <2 x float> %lhs, %rhs
30 %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
31 …%3 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x float> %2) nounwind readnone
32 %4 = extractelement <4 x float> %3, i32 0
33 ret float %4
36 define float @_Z3dotff(float %lhs, float %rhs) nounwind readnone {
37 %1 = fmul float %lhs, %rhs
38 ret float %1
41 define float @_Z6lengthDv4_f(<4 x float> %in) nounwind readnone alwaysinline {
42 %1 = fmul <4 x float> %in, %in
43 …%2 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %1, <4 x float> %1) nounwind readnone
44 …%3 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x float> %2) nounwind readnone
45 %4 = extractelement <4 x float> %3, i32 0
46 %5 = tail call float @llvm.sqrt.f32(float %4) nounwind readnone
47 ret float %5
50 define float @_Z6lengthDv3_f(<3 x float> %in) nounwind readnone alwaysinline {
51 %1 = fmul <3 x float> %in, %in
52 %2 = shufflevector <3 x float> %1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
53 %3 = bitcast <4 x float> %2 to <2 x i64>
55 %5 = bitcast <2 x i64> %4 to <4 x float>
56 …%6 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %5, <4 x float> %5) nounwind readnone
57 …%7 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %6, <4 x float> %6) nounwind readnone
58 %8 = extractelement <4 x float> %7, i32 0
59 %9 = tail call float @llvm.sqrt.f32(float %8) nounwind readnone
60 ret float %9
63 define float @_Z6lengthDv2_f(<2 x float> %in) nounwind readnone alwaysinline {
64 %1 = fmul <2 x float> %in, %in
65 %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
66 …%3 = tail call <4 x float> @llvm.x86.sse3.hadd.ps(<4 x float> %2, <4 x float> %2) nounwind readnone
67 %4 = extractelement <4 x float> %3, i32 0
68 %5 = tail call float @llvm.sqrt.f32(float %4) nounwind readnone
69 ret float %5
72 define float @_Z6lengthf(float %in) nounwind readnone alwaysinline {
73 %1 = bitcast float %in to i32
75 %3 = bitcast i32 %2 to float
76 ret float %3