41     snprintf(bu, MAX_SIZE, "/sys/class/pwm/pwmchip%d/pwm%d/duty_cycle", dev->chipid, dev->pin);  in mraa_pwm_setup_duty_fp()
61     snprintf(bu, MAX_SIZE, "/sys/class/pwm/pwmchip%d/pwm%d/period", dev->chipid, dev->pin);  in mraa_pwm_write_period()
100     snprintf(bu, MAX_SIZE, "/sys/class/pwm/pwmchip%d/pwm%d/period", dev->chipid, dev->pin);  in mraa_pwm_read_period()
163 mraa_pwm_init_internal(mraa_adv_func_t* func_table, int chipin, int pin)  in mraa_pwm_init_internal()  argument
171     dev->pin = pin;  in mraa_pwm_init_internal()
179 mraa_pwm_init(int pin)  in mraa_pwm_init()  argument
185     if (mraa_is_sub_platform_id(pin)) {  in mraa_pwm_init()
189     if (plat->pins[pin].capabilites.pwm != 1) {  in mraa_pwm_init()
195         return plat->adv_func->pwm_init_replace(pin);  in mraa_pwm_init()
198         if (plat->adv_func->pwm_init_pre(pin) != MRAA_SUCCESS)  in mraa_pwm_init()
202     if (plat->pins[pin].capabilites.gpio == 1) {  in mraa_pwm_init()
205         mux_i = mraa_gpio_init_raw(plat->pins[pin].gpio.pinmap);  in mraa_pwm_init()
224     if (plat->pins[pin].pwm.mux_total > 0) {  in mraa_pwm_init()
225         if (mraa_setup_mux_mapped(plat->pins[pin].pwm) != MRAA_SUCCESS) {  in mraa_pwm_init()
231     int chip = plat->pins[pin].pwm.parent_id;  in mraa_pwm_init()
232     int pinn = plat->pins[pin].pwm.pinmap;  in mraa_pwm_init()
247 mraa_pwm_init_raw(int chipin, int pin)  in mraa_pwm_init_raw()  argument
249 … mraa_pwm_context dev = mraa_pwm_init_internal(plat == NULL ? NULL : plat->adv_func , chipin, pin);  in mraa_pwm_init_raw()
254     snprintf(directory, MAX_SIZE, SYSFS_PWM "/pwmchip%d/pwm%d", dev->chipid, dev->pin);  in mraa_pwm_init_raw()
270         int size = snprintf(out, MAX_SIZE, "%d", dev->pin);  in mraa_pwm_init_raw()
360     snprintf(bu, MAX_SIZE, "/sys/class/pwm/pwmchip%d/pwm%d/enable", dev->chipid, dev->pin);  in mraa_pwm_enable()
392     int size = snprintf(out, MAX_SIZE, "%d", dev->pin);  in mraa_pwm_unexport_force()