Lines Matching refs:u32
80 u32 timestamp;
85 u32 first_mpdu : 1; //[0]
86 u32 last_mpdu : 1; //[1]
87 u32 reserved1 : 6; //[7:2]
88 u32 mgmt_type : 1; //[8]
89 u32 ctrl_type : 1; //[9]
90 u32 reserved2 : 6; //[15:10]
91 u32 overflow_err : 1; //[16]
92 u32 msdu_length_err : 1; //[17]
93 u32 tcp_udp_chksum_fail : 1; //[18]
94 u32 ip_chksum_fail : 1; //[19]
95 u32 reserved3 : 7; //[26:20]
96 u32 mpdu_length_err : 1; //[27]
97 u32 tkip_mic_err : 1; //[28]
98 u32 decrypt_err : 1; //[29]
99 u32 fcs_err : 1; //[30]
100 u32 msdu_done : 1; //[31]
104 u32 reserved1 : 13; //[12:0]
105 u32 encrypted : 1; //[13]
106 u32 retry : 1; //[14]
107 u32 reserved2 : 1; //[15]
108 u32 seq_num : 12; //[27:16]
109 u32 reserved3 : 4; //[31:28]
110 u32 reserved4;
111 u32 reserved5 : 28; //[27:0]
112 u32 tid : 4; //[31:28]
124 u32 reserved1[2];
125 u32 reserved2 : 8; //[7:0]
126 u32 decap_format : 2; //[9:8]
127 u32 reserved3 : 22; //[31:10]
131 u32 reserved1[4];
132 u32 reserved2 : 15;
133 u32 last_msdu : 1; //[15]
134 u32 reserved3 : 16; //[31:16]
138 u32 reserved1 : 13; //[12:0]
139 u32 overflow_err : 1; //[13]
140 u32 last_mpdu : 1; //[14]
141 u32 post_delim_err : 1; //[15]
142 u32 reserved2 : 12; //[27:16]
143 u32 mpdu_length_err : 1; //[28]
144 u32 tkip_mic_err : 1; //[29]
145 u32 decrypt_err : 1; //[30]
146 u32 fcs_err : 1; //[31]
166 u32 reserved1[4];
167 u32 rssi_comb : 8; //[7:0]
168 u32 reserved2 : 24; //[31:8]
169 u32 l_sig_rate : 4; //[3:0]
170 u32 l_sig_rate_select : 1; //[4]
171 u32 reserved3 : 19; //[23:5]
172 u32 preamble_type : 8; //[31:24]
173 u32 ht_sig_vht_sig_a_1 : 24; //[23:0]
174 u32 reserved4 : 8; //[31:24]
175 u32 ht_sig_vht_sig_a_2 : 24; //[23:0]
176 u32 reserved5 : 8; //[31:25]
177 u32 reserved6[2];
181 u32 reserved1[16];
182 u32 tsf_timestamp;
183 u32 reserved2[5];
191 u32 reserved1;
203 u32 ba_start_seq_num : 12; //[11:0]
204 u32 reserved1 : 3; //[14:12]
205 u32 ba_status : 1; //[15]
206 u32 reserved2 : 15; //[30:16]
207 u32 tx_ok : 1; //[31]
208 u32 ba_bitmap_31_0 : 32; //[31:0]
209 u32 ba_bitmap_63_32 : 32; //[31:0]
210 u32 reserved3[8];
211 u32 ack_rssi_ave : 8; //[7:0]
212 u32 reserved4 : 16; //[23:8]
213 u32 total_tries : 5; //[28:24]
214 u32 reserved5 : 3; //[31:29]
215 u32 reserved6[4];
220 u32 timestamp : 23; //[22:0]
221 u32 reserved1 : 1; //[23]
222 u32 series : 1; //[24]
223 u32 reserved2 : 3; //[27:25]
224 u32 packet_bw : 2; //[29:28]
225 u32 reserved3 : 1; //[30]
226 u32 tx_packet : 1; //[31]
241 u32 reserved1 : 28; //[27:0]
242 u32 short_gi : 1; //[28]
243 u32 reserved2 : 3; //[31:29]
244 u32 reserved3 : 24; //[23:21]
245 u32 rate : 4; //[27:24]
246 u32 nss : 2; //[29:28]
247 u32 preamble_type : 2; //[31:30]
248 u32 reserved4[2];
260 u32 reserved1[2];
261 u32 start_seq_num : 12; //[11:0]
262 u32 reserved2 : 20; //[31:12]
263 u32 seqnum_bitmap_31_0 : 32; //[31:0]
264 u32 seqnum_bitmap_63_32 : 32; //[31:0]
265 u32 reserved3[8];
266 u32 reserved4 : 15; //[14:0]
267 u32 ampdu : 1; //[15]
268 u32 no_ack : 1; //[16]
269 u32 reserved5 : 15; //[31:17]
270 u32 reserved6 : 16; //[15:0]
271 u32 frame_control : 16; //[31:16]
272 u32 reserved7 : 16; //[23:21]
273 u32 qos_ctl : 16; //[31:16]
274 u32 reserved8[4];
275 u32 reserved9 : 24; //[23:21]
276 u32 valid_s0_bw20 : 1; //[24]
277 u32 valid_s0_bw40 : 1; //[25]
278 u32 valid_s0_bw80 : 1; //[26]
279 u32 valid_s0_bw160 : 1; //[27]
280 u32 valid_s1_bw20 : 1; //[28]
281 u32 valid_s1_bw40 : 1; //[29]
282 u32 valid_s1_bw80 : 1; //[30]
283 u32 valid_s1_bw160 : 1; //[31]
292 u32 reserved10[3];
297 u32 reserved1[3];
299 u32 txdesc_ctl[PKTLOG_MAX_TXCTL_WORDS];
326 u32 ba_bitmap_31_0;
327 u32 ba_bitmap_63_32;
328 u32 tx_seqnum_bitmap_31_0;
329 u32 tx_seqnum_bitmap_63_32;
330 u32 shifted_bitmap_31_0;
331 u32 shifted_bitmap_63_32;
353 u32 timestamp;
362 u32 timestamp_low;
363 u32 timestamp_high;
366 u32 version;
367 u32 msg_seq_no;
368 u32 payload_len;
386 u32 driver_ts;
392 u32 driver_timestamp_usec;
393 u32 firmware_timestamp_usec;