Lines Matching refs:xtensa_arg_internal

5569 static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
5575 static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
5581 static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
5586 static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
5590 static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
5595 static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
5599 static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
5604 static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
5608 static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
5613 static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
5617 static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
5622 static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
5626 static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
5631 static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
5635 static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
5641 static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
5649 static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
5654 static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
5659 static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
5663 static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
5669 static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
5673 static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
5680 static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
5689 static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
5695 static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
5700 static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
5706 static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
5711 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
5715 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
5721 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
5725 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
5731 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
5735 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
5741 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
5745 static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
5751 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
5755 static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
5761 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
5765 static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
5771 static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
5777 static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
5783 static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
5788 static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
5794 static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
5799 static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
5804 static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
5808 static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
5814 static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
5818 static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
5822 static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
5826 static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
5830 static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
5836 static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
5842 static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
5848 static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
5854 static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
5860 static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
5866 static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
5872 static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
5878 static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
5883 static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
5888 static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
5893 static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
5900 static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
5904 static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
5908 static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
5914 static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
5920 static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
5926 static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
5931 static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
5936 static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
5942 static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
5947 static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
5953 static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
5958 static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
5964 static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
5969 static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
5975 static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
5980 static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
5984 static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
5990 static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
5996 static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
6002 static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
6006 static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
6010 static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
6014 static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
6018 static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
6023 static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
6027 static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
6033 static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
6037 static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
6042 static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
6046 static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
6052 static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
6058 static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
6064 static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
6068 static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
6073 static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
6083 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
6087 static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
6091 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
6095 static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
6099 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
6103 static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
6107 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
6111 static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
6115 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
6119 static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
6124 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
6128 static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
6133 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
6137 static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
6141 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
6145 static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
6149 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
6153 static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
6157 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
6161 static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
6165 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
6169 static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
6174 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
6178 static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
6182 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
6186 static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
6191 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
6195 static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
6200 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
6204 static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
6209 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
6213 static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
6218 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
6222 static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
6227 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
6231 static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
6241 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
6245 static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
6255 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
6259 static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
6269 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
6273 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
6279 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
6283 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
6289 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
6293 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
6299 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
6303 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
6309 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
6313 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
6319 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
6323 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
6329 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
6333 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
6339 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
6343 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
6349 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
6353 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
6359 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
6363 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
6369 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
6373 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
6379 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
6383 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
6389 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
6393 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
6399 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
6403 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
6409 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
6413 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
6419 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
6423 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
6429 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
6433 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
6439 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
6443 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
6449 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
6453 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
6459 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
6463 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
6469 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
6473 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
6479 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
6483 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
6489 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
6493 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
6499 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
6503 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
6509 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
6513 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
6519 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
6523 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
6529 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
6533 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
6539 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
6543 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
6549 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
6553 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
6559 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
6563 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
6569 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
6573 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
6579 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
6583 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
6589 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
6593 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
6599 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
6603 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
6609 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
6613 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
6619 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
6623 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
6629 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
6633 static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
6639 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
6643 static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
6649 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
6653 static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
6659 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
6663 static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
6669 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
6673 static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
6679 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
6683 static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
6689 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
6693 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
6699 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
6703 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
6709 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
6713 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
6719 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
6723 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
6729 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
6733 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
6739 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
6743 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
6749 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
6753 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
6759 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
6763 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
6769 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
6773 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
6779 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
6783 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
6789 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
6793 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
6799 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
6803 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
6809 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
6813 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
6819 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
6823 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
6829 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
6833 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
6839 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
6843 static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
6849 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
6853 static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
6859 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
6863 static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
6869 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
6873 static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
6879 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
6883 static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
6889 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
6893 static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
6899 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
6903 static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
6909 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
6913 static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
6919 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
6923 static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
6929 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
6933 static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
6940 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
6944 static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
6950 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
6954 static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
6960 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
6964 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
6970 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
6974 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
6980 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
6984 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
6990 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
6994 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
7000 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
7004 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
7010 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
7014 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
7020 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
7024 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
7030 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
7034 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
7040 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
7044 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
7050 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
7054 static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
7060 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
7064 static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
7070 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
7074 static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
7080 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
7084 static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
7089 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
7093 static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
7099 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
7103 static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
7109 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
7113 static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
7119 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
7124 static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
7128 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
7133 static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
7137 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
7142 static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
7146 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
7151 static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
7155 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
7160 static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
7164 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
7169 static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
7173 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
7178 static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
7182 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
7187 static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
7191 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
7198 static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
7202 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
7209 static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
7213 static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
7218 static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
7224 static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
7229 static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
7234 static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
7239 static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
7244 static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
7249 static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
7254 static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
7259 static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
7264 static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
7269 static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
7274 static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
7279 static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
7284 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
7288 static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
7292 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
7296 static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
7300 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
7304 static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
7308 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
7312 static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
7316 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
7320 static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
7324 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
7328 static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
7332 static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
7336 static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
7360 static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
7364 static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
7370 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
7374 static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
7380 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
7384 static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
7391 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
7395 static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
7402 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
7406 static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
7412 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
7416 static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
7422 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
7426 static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
7432 static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
7437 static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
7442 static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
7446 static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
7451 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
7455 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
7461 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
7465 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
7472 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
7476 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
7483 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
7487 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
7493 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
7497 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
7504 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
7508 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
7515 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
7519 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
7525 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
7529 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
7536 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
7540 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
7547 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
7551 static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
7557 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
7561 static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
7568 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
7572 static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
7579 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
7583 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
7589 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
7593 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
7599 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
7603 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
7609 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
7613 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
7619 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
7623 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
7629 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
7633 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
7639 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
7643 static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
7649 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
7653 static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
7659 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
7663 static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
7669 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
7673 static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
7680 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
7684 static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
7691 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
7695 static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
7702 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
7706 static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
7712 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
7716 static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
7723 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
7727 static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
7734 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
7738 static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
7744 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
7748 static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
7754 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
7758 static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
7764 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
7768 static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
7774 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
7778 static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
7785 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
7789 static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
7796 static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
7800 static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
7813 static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
7817 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
7821 static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
7827 static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
7833 static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
7838 static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
7843 static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
7848 static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
7854 static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
7859 static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
7864 static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
7869 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
7873 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
7879 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
7883 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
7890 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
7894 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
7901 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
7905 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
7911 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
7915 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
7922 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
7926 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
7933 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
7937 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
7943 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
7947 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
7954 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
7958 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
7965 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
7969 static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
7975 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
7979 static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
7986 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
7990 static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
7997 static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
8002 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
8007 static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
8012 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
8017 static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
8022 static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
8027 static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
8032 static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
8037 static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
8042 static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
8047 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
8052 static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
8057 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
8062 static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
8067 static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
8072 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
8077 static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
8082 static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
8087 static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
8092 static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
8097 static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
8102 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
8106 static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
8113 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
8117 static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
8124 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
8128 static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
8136 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
8140 static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
8148 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
8152 static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
8161 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
8165 static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
8174 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
8178 static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
8184 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
8188 static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
8195 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
8199 static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
8206 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
8210 static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
8216 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
8220 static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
8227 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
8231 static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
8238 static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
8242 static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
8248 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
8253 static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
8258 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
8263 static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
8269 static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
8273 static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
8278 static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
8283 static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
8288 static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
8293 static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
8298 static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
8303 static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
8307 static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
8311 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
8315 static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
8321 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
8325 static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
8331 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
8335 static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
8341 static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
8347 static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
8353 static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
8358 static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
8364 static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
8370 static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
8376 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
8382 static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
8387 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
8391 static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
8395 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
8399 static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
8403 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
8407 static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
8411 static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
8417 static xtensa_arg_internal Iclass_xt_mul32_args[] = {
8423 static xtensa_arg_internal Iclass_rur_fcr_args[] = {
8427 static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
8439 static xtensa_arg_internal Iclass_wur_fcr_args[] = {
8443 static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
8455 static xtensa_arg_internal Iclass_rur_fsr_args[] = {
8459 static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
8470 static xtensa_arg_internal Iclass_wur_fsr_args[] = {
8474 static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
8485 static xtensa_arg_internal Iclass_fp_args[] = {
8491 static xtensa_arg_internal Iclass_fp_stateArgs[] = {
8496 static xtensa_arg_internal Iclass_fp_mac_args[] = {
8502 static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
8507 static xtensa_arg_internal Iclass_fp_cmov_args[] = {
8513 static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
8517 static xtensa_arg_internal Iclass_fp_mov_args[] = {
8523 static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
8527 static xtensa_arg_internal Iclass_fp_mov2_args[] = {
8532 static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
8536 static xtensa_arg_internal Iclass_fp_cmp_args[] = {
8542 static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
8546 static xtensa_arg_internal Iclass_fp_float_args[] = {
8552 static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
8557 static xtensa_arg_internal Iclass_fp_int_args[] = {
8563 static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
8567 static xtensa_arg_internal Iclass_fp_rfr_args[] = {
8572 static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
8576 static xtensa_arg_internal Iclass_fp_wfr_args[] = {
8581 static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
8585 static xtensa_arg_internal Iclass_fp_lsi_args[] = {
8591 static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
8595 static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
8601 static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
8605 static xtensa_arg_internal Iclass_fp_lsx_args[] = {
8611 static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
8615 static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
8621 static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
8625 static xtensa_arg_internal Iclass_fp_ssi_args[] = {
8631 static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
8635 static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
8641 static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
8645 static xtensa_arg_internal Iclass_fp_ssx_args[] = {
8651 static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
8655 static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
8661 static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
8665 static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
8670 static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
8676 static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
8682 static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
8688 static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {