Lines Matching refs:rd
171 (dnf f-rd "short rd" () 15 3) ;; RD
175 (dnf f-rd-x "extension rd" () 31 3) ;; RD
268 (x-reg-field rd) ; f-rd6
960 (short-regs rd d h-registers "destination register")
1397 (.str name " $rd,[$rn,$rm]")
1398 (+ OP4_LDSTR16X sel OP_LOAD rd rn rm)
1400 (sem-op rd (add rn rm) mode sel))
1408 (.str name " $rd,[$rn],$rm")
1409 (+ OP4_LDSTR16P sel OP_LOAD rd rn rm)
1412 (sem-op rd rn mode sel)
1467 (.str name " $rd,[$rn,$disp3]")
1468 (+ OP4_LDSTR16D sel OP_LOAD rd rn disp3) ;; convert size to 'B'
1473 (sem-op rd effa mode sel)
1532 (.str name " $rd,[$rn]")
1533 (emit (.sym name "d16.s") rd rn (disp3 0))
1583 ;;always update rd
1621 (.str name " $rd,[$rn,$rm]")
1622 (+ OP4_LDSTR16X sel OP_STORE rd rn rm)
1624 (sem-op (add rn rm) rd mode sel)
1656 (.str name " $rd,[$rn],$rm")
1657 (+ OP4_LDSTR16P sel OP_STORE rd rn rm)
1659 (sem-op rn rd mode sel)
1688 (.str name " $rd,[$rn,$disp3]")
1689 (+ OP4_LDSTR16D sel OP_STORE rd rn disp3) ;; convert size to 'B'
1694 (sem-op effa rd mode sel)
1749 (.str name " $rd,[$rn]")
1750 (emit (.sym name "d16") rd rn (disp3 0))
1784 (.str "mov" name " $rd,$rn")
1785 (+ OP4_FLOW16 (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) rd rn)
1787 (set rd rn))
1843 "movts $sn,$rd"
1844 (+ OP4_FLOW16 (f-opc-8-5 #x10) (f-dc-9-1 #x0) rd sn) ;; rd is source for movts
1845 (set sn rd)
1856 …f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) sdreg rd6);; rd is source for movts
1885 "movfs $rd,$sn"
1886 (+ OP4_FLOW16 (f-opc-8-5 #x11) (f-dc-9-1 #x0) rd sn)
1887 (set rd sn)
2126 …(+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x1) trapnum6) ;; (+ OP4_IMM16 OPI_TRAP (f-rd 0) …
2142 (.str name " $rd,$rn,$rm")
2143 (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
2146 (set rd (sem-op SI rn rm))
2147 (set zbit (zflag rd))
2148 (set nbit (nflag rd))
2212 (.str name ".s $rd,$rn,$simm3")
2213 (+ OP4_IMM16 code rd rn simm3)
2216 (set rd (name SI rn simm3))
2217 (set zbit (zflag rd))
2218 (set nbit (nflag rd))
2248 "add $rd,$rn,$simm3"
2249 (emit addi16 rd rn simm3))
2262 "sub $rd,$rn,$simm3"
2263 (emit subi16 rd rn simm3))
2284 (.str name " $rd,$rn,$rm")
2285 (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
2288 (set rd (sem-op SI rn (and rm (const 31))))
2289 (set zbit (zflag rd))
2290 (set nbit (nflag rd))
2327 (.str name " $rd,$rn,$shift")
2328 (+ shortcode (f-opc-4-1 f5) rd rn shift)
2331 (set rd (sem-op SI rn shift))
2332 (set zbit (zflag rd))
2333 (set nbit (nflag rd))
2389 ("bitr $rd,$rn")
2390 (+ OP4_ASHIFT16 (f-opc-4-1 1) rd rn (f-shift 0))
2392 (bit-reversal rd rn)
2393 (set zbit (zflag rd))
2394 (set nbit (nflag rd))
2463 "mov.b $rd,$imm8"
2464 (+ OP4_IMM16 (f-opc-4-1 #x0) rd imm8)
2465 (set rd (zext SI imm8))
2471 "mov $rd,$imm8"
2472 (emit mov8 rd imm8))
2494 (set rd6 (or (and SI rd6 (const #xffff)) ; keep low bits of rd
2515 (.str "f" name " $rd,$rn,$rm")
2516 (+ OP4_DSP16 code rd rn rm)
2521 (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rm))
2532 (set rd sdtmp)
2542 (set sdtmp (c-call SI (.str "epiphany_i" name) rd rn rm))
2546 (set rd sdtmp)))
2554 (.str "i" name " $rd,$rn,$rm")
2555 (emit (.sym "f_" name "f16") rd rn rm)
2641 (.str "f" name " rd,rn")
2642 (+ OP4_DSP16 code rd rn rn)
2646 (set sdtmp (c-call SI (.str "epiphany_fabs") rd rn rn))
2657 (set rd sdtmp)
2707 (.str "f" name " $rd,$rn")
2711 (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn))
2720 (set rd sdtmp)
2764 (.str "f" name " $rd,$rn")
2765 (+ OP4_DSP16 code rd rn rn)
2768 (set sdtmp (c-call SI (.str "epiphany_f" name) rd rn rn))
2790 (set rd sdtmp)
2865 ;; ; (set rd (subword SI frd 0))