Lines Matching refs:srl
216 (set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255)))
227 (set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3)))
240 (set (ifield f-imm-27-8) (srl (ifield f-imm16) 8)))
257 (set (ifield (.sym "f-" reg "-x")) (srl (ifield (.sym "f-" reg "6"))
775 (set trmbit (and (const 1) (srl val (const 0))))
776 (set invExcEnbit (and (const 1) (srl val (const 1))))
777 (set ovfExcEnbit (and (const 1) (srl val (const 2))))
778 (set unExcEnbit (and (const 1) (srl val (const 3))))
779 (set timer0bit0 (and (const 1) (srl val (const 4))))
780 (set timer0bit1 (and (const 1) (srl val (const 5))))
781 (set timer0bit2 (and (const 1) (srl val (const 6))))
782 (set timer0bit3 (and (const 1) (srl val (const 7))))
783 (set timer1bit0 (and (const 1) (srl val (const 8))))
784 (set timer1bit1 (and (const 1) (srl val (const 9))))
785 (set timer1bit2 (and (const 1) (srl val (const 10))))
786 (set timer1bit3 (and (const 1) (srl val (const 11))))
788 (set coreCfgResBit12 (and (const 1) (srl val (const 12))))
789 (set coreCfgResBit13 (and (const 1) (srl val (const 13))))
790 (set coreCfgResBit14 (and (const 1) (srl val (const 14))))
791 (set coreCfgResBit15 (and (const 1) (srl val (const 15))))
792 (set coreCfgResBit16 (and (const 1) (srl val (const 16))))
794 (set arithmetic-modebit0 (and (const 1) (srl val (const 17))))
795 (set arithmetic-modebit1 (and (const 1) (srl val (const 18))))
796 (set arithmetic-modebit2 (and (const 1) (srl val (const 19))))
798 (set coreCfgResBit20 (and (const 1) (srl val (const 20))))
799 (set coreCfgResBit21 (and (const 1) (srl val (const 21))))
801 (set clockGateEnbit (and (const 1) (srl val (const 22))))
802 (set mbkptEnbit (and (const 1) (srl val (const 23))))
804 (set coreCfgResBit24 (and (const 1) (srl val (const 24))))
805 (set coreCfgResBit25 (and (const 1) (srl val (const 25))))
806 (set coreCfgResBit26 (and (const 1) (srl val (const 26))))
807 (set coreCfgResBit27 (and (const 1) (srl val (const 27))))
808 (set coreCfgResBit28 (and (const 1) (srl val (const 28))))
809 (set coreCfgResBit29 (and (const 1) (srl val (const 29))))
810 (set coreCfgResBit30 (and (const 1) (srl val (const 30))))
811 (set coreCfgResBit31 (and (const 1) (srl val (const 31))))
821 (set extFstallbit (and (const 1) (srl newval (const 19))))
822 (set expcause2bit (and (const 1) (srl newval (const 18))))
823 (set expcause1bit (and (const 1) (srl newval (const 17))))
824 (set expcause0bit (and (const 1) (srl newval (const 16))))
825 (set busbit (and (const 1) (srl newval (const 15))))
826 (set bisbit (and (const 1) (srl newval (const 13))))
827 (set bvsbit (and (const 1) (srl newval (const 14))))
828 (set vsbit (and (const 1) (srl newval (const 12))))
829 (set bvbit (and (const 1) (srl newval (const 10))))
830 (set bcbit (and (const 1) (srl newval (const 11))))
831 (set bnbit (and (const 1) (srl newval (const 9))))
832 (set bzbit (and (const 1) (srl newval (const 8))))
833 (set vbit (and (const 1) (srl newval (const 7))))
834 (set cbit (and (const 1) (srl newval (const 6))))
835 (set nbit (and (const 1) (srl newval (const 5))))
836 (set zbit (and (const 1) (srl newval (const 4))))
837 (set sflagbit (and (const 1) (srl newval (const 3))))
838 (set kmbit (and (const 1) (srl newval (const 2))))
839 ;;(set gie (and (const 1) (srl newval (const 1))))
2319 (shift-rrr lsr srl)
2362 (op-shift-rri lsr OP4_LSHIFT16 0 #x6 srl)
2379 (set v (or (and (srl v 1) #x55555555) (sll (and v #x55555555) 1)))
2380 (set v (or (and (srl v 2) #x33333333) (sll (and v #x33333333) 2)))
2381 (set v (or (and (srl v 4) #x0f0f0f0f) (sll (and v #x0f0f0f0f) 4)))
2382 (set v (or (and (srl v 8) #x00ff00ff) (sll (and v #x00ff00ff) 8)))
2383 (set v (or (srl v 16) (sll v 16)))