585 #define REG_SP	13  macro
3765   unwind.fp_reg = REG_SP;  in s_arm_unwind_fnstart()
4440   if (reg == REG_SP || reg == REG_PC)  in s_arm_unwind_movsp()
4446   if (unwind.fp_reg != REG_SP)  in s_arm_unwind_movsp()
4522   if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)  in s_arm_unwind_setfp()
4532   if (sp_reg == REG_SP)  in s_arm_unwind_setfp()
7135 	      else if (inst.operands[i].reg == REG_SP)  in parse_operands()
7237    if (reg == REG_SP || reg == REG_PC)			\
7239        inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC;	\
7248     if (warn_on_deprecated && reg == REG_SP)	\
8362 	constraint (Rd == REG_SP, BAD_SP);  in do_co_reg()
8810   if (thumb_mode && Rt == REG_SP)  in do_vmrs()
9035   inst.operands[0].reg = REG_SP;  in do_push_pop()
9210       constraint (reg != REG_SP, _("SRS base register must be r13"));  in do_srs()
9213     reg = REG_SP;  in do_srs()
10160   if (Rn == REG_SP)  in do_t_add_sub_w()
10201 	  constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);  in do_t_add_sub()
10210 	      if (Rd == REG_SP && Rs == REG_SP && !flags)  in do_t_add_sub()
10212 	      else if (Rd <= 7 && Rs == REG_SP && add && !flags)  in do_t_add_sub()
10317 	  constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);  in do_t_add_sub()
10327 	  constraint (Rd == REG_SP && Rs == REG_SP && value > 3,  in do_t_add_sub()
10329 	  constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,  in do_t_add_sub()
10342 	  constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))  in do_t_add_sub()
10343 		      || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),  in do_t_add_sub()
11125 	  else if (inst.operands[0] .reg == REG_SP)  in do_t_ldmstm()
11262 		   || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)  in do_t_ldst()
11263 		   || (Rn == REG_SP && opcode == T_MNEM_str))  in do_t_ldst()
11301 	  && inst.operands[0].reg == REG_SP  in do_t_ldst()
11352   if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)  in do_t_ldst()
11548 		  if ((Rn == REG_SP || Rn == REG_PC)  in do_t_mov_cmp()
11549 		      && (Rm == REG_SP || Rm == REG_PC))  in do_t_mov_cmp()
11561 		  constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);  in do_t_mov_cmp()
12779   constraint (Rn == REG_SP, BAD_SP);  in do_t_tb()
13953   inst.operands[0].reg = REG_SP;  in nsyn_insert_sp()
16733   if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))  in do_crc32_1()
21397   cfi_add_CFA_def_cfa (REG_SP, 0);  in tc_arm_frame_initial_instructions()
22814 	if ((rd > 7 && (rd != REG_SP || rs != REG_SP))  in md_apply_fix()
22815 	    || (rs > 7 && rs != REG_SP && rs != REG_PC))  in md_apply_fix()
22829 	if (rd == REG_SP)  in md_apply_fix()
22837 	else if (rs == REG_PC || rs == REG_SP)  in md_apply_fix()