Lines Matching refs:Rn
7995 unsigned Rn = inst.operands[2].reg; in do_rd_rm_rn() local
7999 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg, in do_rd_rm_rn()
8013 inst.instruction |= Rn << 16; in do_rd_rm_rn()
8413 unsigned Rd, Rn; in do_co_reg2c() local
8416 Rn = inst.operands[3].reg; in do_co_reg2c()
8421 reject_bad_reg (Rn); in do_co_reg2c()
8426 constraint (Rn == REG_PC, BAD_PC); in do_co_reg2c()
8432 inst.instruction |= Rn << 16; in do_co_reg2c()
8456 unsigned Rd, Rn, Rm; in do_div() local
8459 Rn = (inst.operands[1].present in do_div()
8464 constraint ((Rn == REG_PC), BAD_PC); in do_div()
8468 inst.instruction |= Rn << 0; in do_div()
10153 int Rd, Rn; in do_t_add_sub_w() local
10156 Rn = inst.operands[1].reg; in do_t_add_sub_w()
10160 if (Rn == REG_SP) in do_t_add_sub_w()
10165 inst.instruction |= (Rn << 16) | (Rd << 8); in do_t_add_sub_w()
10175 int Rd, Rs, Rn; in do_t_add_sub() local
10277 Rn = inst.operands[2].reg; in do_t_add_sub()
10281 if (Rd > 7 || Rs > 7 || Rn > 7) in do_t_add_sub()
10290 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); in do_t_add_sub()
10294 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn)) in do_t_add_sub()
10298 if (Rd > 7 || Rn > 7 in do_t_add_sub()
10302 if (Rd == Rn) in do_t_add_sub()
10304 Rn = Rs; in do_t_add_sub()
10310 inst.instruction |= Rn << 3; in do_t_add_sub()
10319 reject_bad_reg (Rn); in do_t_add_sub()
10353 Rn = inst.operands[2].reg; in do_t_add_sub()
10357 if (Rd > 7 || Rs > 7 || Rn > 7) in do_t_add_sub()
10365 inst.instruction |= Rn << 3; in do_t_add_sub()
10366 else if (Rn == Rd) in do_t_add_sub()
10375 inst.instruction |= Rd | (Rs << 3) | (Rn << 6); in do_t_add_sub()
10424 int Rd, Rs, Rn; in do_t_arit3() local
10430 Rn = inst.operands[2].reg; in do_t_arit3()
10435 reject_bad_reg (Rn); in do_t_arit3()
10459 if (Rd > 7 || Rn > 7 || Rs > 7) in do_t_arit3()
10471 inst.instruction |= Rn << 3; in do_t_arit3()
10494 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); in do_t_arit3()
10500 inst.instruction |= Rn << 3; in do_t_arit3()
10512 int Rd, Rs, Rn; in do_t_arit3c() local
10518 Rn = inst.operands[2].reg; in do_t_arit3c()
10523 reject_bad_reg (Rn); in do_t_arit3c()
10547 if (Rd > 7 || Rn > 7 || Rs > 7) in do_t_arit3c()
10560 inst.instruction |= Rn << 3; in do_t_arit3c()
10563 if (Rd == Rn) in do_t_arit3c()
10591 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG); in do_t_arit3c()
10597 inst.instruction |= Rn << 3; in do_t_arit3c()
10598 else if (Rd == Rn) in do_t_arit3c()
10624 int Rd, Rn; in do_t_bfi() local
10633 Rn = REG_PC; in do_t_bfi()
10636 Rn = inst.operands[1].reg; in do_t_bfi()
10637 reject_bad_reg (Rn); in do_t_bfi()
10645 inst.instruction |= Rn << 16; in do_t_bfi()
10654 unsigned Rd, Rn; in do_t_bfx() local
10657 Rn = inst.operands[1].reg; in do_t_bfx()
10660 reject_bad_reg (Rn); in do_t_bfx()
10665 inst.instruction |= Rn << 16; in do_t_bfx()
10927 unsigned Rd, Rn, Rm; in do_t_div() local
10930 Rn = (inst.operands[1].present in do_t_div()
10935 reject_bad_reg (Rn); in do_t_div()
10939 inst.instruction |= Rn << 16; in do_t_div()
11225 int Rn; in do_t_ldst() local
11250 Rn = inst.operands[1].reg; in do_t_ldst()
11255 if (Rn <= 7 && inst.operands[1].imm <= 7) in do_t_ldst()
11260 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh in do_t_ldst()
11262 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr) in do_t_ldst()
11263 || (Rn == REG_SP && opcode == T_MNEM_str)) in do_t_ldst()
11266 if (Rn > 7) in do_t_ldst()
11268 if (Rn == REG_PC) in do_t_ldst()
11441 unsigned Rd, Rn, Rm, Ra; in do_t_mla() local
11444 Rn = inst.operands[1].reg; in do_t_mla()
11449 reject_bad_reg (Rn); in do_t_mla()
11454 inst.instruction |= Rn << 16; in do_t_mla()
11462 unsigned RdLo, RdHi, Rn, Rm; in do_t_mlal() local
11466 Rn = inst.operands[2].reg; in do_t_mlal()
11471 reject_bad_reg (Rn); in do_t_mlal()
11476 inst.instruction |= Rn << 16; in do_t_mlal()
11483 unsigned Rn, Rm; in do_t_mov_cmp() local
11485 Rn = inst.operands[0].reg; in do_t_mov_cmp()
11488 if (Rn == REG_PC) in do_t_mov_cmp()
11499 low_regs = (Rn <= 7 && Rm <= 7); in do_t_mov_cmp()
11512 && Rn == REG_PC in do_t_mov_cmp()
11521 constraint (Rn == REG_PC, BAD_PC); in do_t_mov_cmp()
11542 reject_bad_reg (Rn); in do_t_mov_cmp()
11548 if ((Rn == REG_SP || Rn == REG_PC) in do_t_mov_cmp()
11553 "register."), Rm, Rn); in do_t_mov_cmp()
11559 constraint (Rn == REG_PC, BAD_PC); in do_t_mov_cmp()
11561 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP); in do_t_mov_cmp()
11565 reject_bad_reg (Rn); in do_t_mov_cmp()
11576 inst.instruction |= Rn << 8; in do_t_mov_cmp()
11586 inst.instruction |= Rn << r0off; in do_t_mov_cmp()
11608 if (Rn != Rm) in do_t_mov_cmp()
11632 inst.instruction |= Rn; in do_t_mov_cmp()
11640 inst.instruction |= Rn << 8; in do_t_mov_cmp()
11672 inst.instruction |= Rn; in do_t_mov_cmp()
11679 inst.instruction |= Rn << r0off; in do_t_mov_cmp()
11706 inst.instruction |= (Rn & 0x8) << 4; in do_t_mov_cmp()
11707 inst.instruction |= (Rn & 0x7); in do_t_mov_cmp()
11715 inst.instruction |= Rn; in do_t_mov_cmp()
11723 inst.instruction |= Rn; in do_t_mov_cmp()
11729 inst.instruction |= (Rn & 0x8) << 4; in do_t_mov_cmp()
11730 inst.instruction |= (Rn & 0x7); in do_t_mov_cmp()
11746 if (Rn < 8 && Rm < 8) in do_t_mov_cmp()
11755 inst.instruction |= Rn; in do_t_mov_cmp()
11769 constraint (Rn > 7, in do_t_mov_cmp()
11771 inst.instruction |= Rn << 8; in do_t_mov_cmp()
11812 unsigned Rn, Rm; in do_t_mvn_tst() local
11814 Rn = inst.operands[0].reg; in do_t_mvn_tst()
11819 constraint (Rn == REG_PC, BAD_PC); in do_t_mvn_tst()
11821 reject_bad_reg (Rn); in do_t_mvn_tst()
11833 || Rn > 7 || Rm > 7) in do_t_mvn_tst()
11850 inst.instruction |= Rn << r0off; in do_t_mvn_tst()
11859 inst.instruction |= Rn; in do_t_mvn_tst()
11869 inst.instruction |= Rn << r0off; in do_t_mvn_tst()
11880 constraint (Rn > 7 || Rm > 7, in do_t_mvn_tst()
11884 inst.instruction |= Rn; in do_t_mvn_tst()
11940 unsigned Rn; in do_t_msr() local
11972 Rn = inst.operands[1].reg; in do_t_msr()
11973 reject_bad_reg (Rn); in do_t_msr()
11979 inst.instruction |= Rn << 16; in do_t_msr()
11986 unsigned Rd, Rn, Rm; in do_t_mul() local
11992 Rn = inst.operands[1].reg; in do_t_mul()
11998 || (Rd != Rn in do_t_mul()
12000 || Rn > 7 in do_t_mul()
12011 constraint (Rn > 7 || Rm > 7, in do_t_mul()
12022 if (Rd == Rn) in do_t_mul()
12025 inst.instruction |= Rn << 3; in do_t_mul()
12036 inst.instruction |= Rn << 16; in do_t_mul()
12040 reject_bad_reg (Rn); in do_t_mul()
12048 unsigned RdLo, RdHi, Rn, Rm; in do_t_mull() local
12052 Rn = inst.operands[2].reg; in do_t_mull()
12057 reject_bad_reg (Rn); in do_t_mull()
12062 inst.instruction |= Rn << 16; in do_t_mull()
12146 unsigned Rd, Rn; in do_t_orn() local
12149 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd; in do_t_orn()
12153 reject_bad_reg (Rn); in do_t_orn()
12156 inst.instruction |= Rn << 16; in do_t_orn()
12180 unsigned Rd, Rn, Rm; in do_t_pkhbt() local
12183 Rn = inst.operands[1].reg; in do_t_pkhbt()
12187 reject_bad_reg (Rn); in do_t_pkhbt()
12191 inst.instruction |= Rn << 16; in do_t_pkhbt()
12540 unsigned Rd, Rn, Rm; in do_t_simd() local
12543 Rn = inst.operands[1].reg; in do_t_simd()
12547 reject_bad_reg (Rn); in do_t_simd()
12551 inst.instruction |= Rn << 16; in do_t_simd()
12558 unsigned Rd, Rn, Rm; in do_t_simd2() local
12562 Rn = inst.operands[2].reg; in do_t_simd2()
12565 reject_bad_reg (Rn); in do_t_simd2()
12569 inst.instruction |= Rn << 16; in do_t_simd2()
12602 unsigned Rd, Rn; in do_t_ssat_usat() local
12605 Rn = inst.operands[2].reg; in do_t_ssat_usat()
12608 reject_bad_reg (Rn); in do_t_ssat_usat()
12612 inst.instruction |= Rn << 16; in do_t_ssat_usat()
12646 unsigned Rd, Rn; in do_t_ssat16() local
12649 Rn = inst.operands[2].reg; in do_t_ssat16()
12652 reject_bad_reg (Rn); in do_t_ssat16()
12656 inst.instruction |= Rn << 16; in do_t_ssat16()
12696 unsigned Rd, Rn, Rm; in do_t_sxtah() local
12699 Rn = inst.operands[1].reg; in do_t_sxtah()
12703 reject_bad_reg (Rn); in do_t_sxtah()
12707 inst.instruction |= Rn << 16; in do_t_sxtah()
12768 unsigned Rn, Rm; in do_t_tb() local
12776 Rn = inst.operands[0].reg; in do_t_tb()
12779 constraint (Rn == REG_SP, BAD_SP); in do_t_tb()
12784 inst.instruction |= (Rn << 16) | Rm; in do_t_tb()
12820 unsigned Rd, Rn; in do_t_usat16() local
12823 Rn = inst.operands[2].reg; in do_t_usat16()
12826 reject_bad_reg (Rn); in do_t_usat16()
12830 inst.instruction |= Rn << 16; in do_t_usat16()
16721 unsigned int Rn = inst.operands[1].reg; in do_crc32_1() local
16726 inst.instruction |= LOW4 (Rn) << 16; in do_crc32_1()
16731 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC) in do_crc32_1()
16733 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP)) in do_crc32_1()