425   } operands[ARM_IT_MAX_OPERANDS];  member
599   unsigned int operands[8];  member
3200       imm1 = inst.operands[1].imm;  in add_to_lit_pool()
3201       imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg  in add_to_lit_pool()
3203 	       : ((bfd_int64_t) inst.operands[1].imm) >> 32);  in add_to_lit_pool()
3207 	  imm2 = inst.operands[1].imm;  in add_to_lit_pool()
4791       inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;  in parse_big_immediate()
4798 	  inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)  in parse_big_immediate()
4800 	  inst.operands[i].regisimm = 1;  in parse_big_immediate()
4830       inst.operands[i].imm = 0;  in parse_big_immediate()
4832 	inst.operands[i].imm |= generic_bignum[idx]  in parse_big_immediate()
4834       inst.operands[i].reg = 0;  in parse_big_immediate()
4836 	inst.operands[i].reg |= generic_bignum[idx]  in parse_big_immediate()
4838       inst.operands[i].regisimm = 1;  in parse_big_immediate()
5139 	  inst.operands[i].imm = reg;  in parse_shift()
5140 	  inst.operands[i].immisreg = 1;  in parse_shift()
5145   inst.operands[i].shift_kind = shift;  in parse_shift()
5146   inst.operands[i].shifted = 1;  in parse_shift()
5170       inst.operands[i].reg = value;  in parse_shifter_operand()
5171       inst.operands[i].isreg = 1;  in parse_shifter_operand()
5212       inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;  in parse_shifter_operand()
5401   inst.operands[i].imm = exp.X_add_number << 8;  in parse_neon_alignment()
5402   inst.operands[i].immisalign = 1;  in parse_neon_alignment()
5404   inst.operands[i].preind = 0;  in parse_neon_alignment()
5455 	  inst.operands[i].reg = REG_PC;  in parse_address_main()
5456 	  inst.operands[i].isreg = 1;  in parse_address_main()
5457 	  inst.operands[i].preind = 1;  in parse_address_main()
5478   inst.operands[i].reg = reg;  in parse_address_main()
5479   inst.operands[i].isreg = 1;  in parse_address_main()
5483       inst.operands[i].preind = 1;  in parse_address_main()
5486       else if (*p == '-') p++, inst.operands[i].negative = 1;  in parse_address_main()
5490 	  inst.operands[i].imm = reg;  in parse_address_main()
5491 	  inst.operands[i].immisreg = 1;  in parse_address_main()
5509 	  if (inst.operands[i].negative)  in parse_address_main()
5511 	      inst.operands[i].negative = 0;  in parse_address_main()
5581 		    inst.operands[i].negative = 1;  in parse_address_main()
5603     inst.operands[i].writeback = 1;  in parse_address_main()
5610 	  if (parse_immediate (&p, &inst.operands[i].imm,  in parse_address_main()
5619 	  if (inst.operands[i].preind)  in parse_address_main()
5629 	  inst.operands[i].postind = 1;  in parse_address_main()
5630 	  inst.operands[i].writeback = 1;  in parse_address_main()
5632 	  if (inst.operands[i].preind)  in parse_address_main()
5639 	  else if (*p == '-') p++, inst.operands[i].negative = 1;  in parse_address_main()
5645 	      if (inst.operands[i].immisalign)  in parse_address_main()
5646 		inst.operands[i].imm |= reg;  in parse_address_main()
5648 		inst.operands[i].imm = reg;  in parse_address_main()
5649 	      inst.operands[i].immisreg = 1;  in parse_address_main()
5658 	      if (inst.operands[i].negative)  in parse_address_main()
5660 		  inst.operands[i].negative = 0;  in parse_address_main()
5676 		    inst.operands[i].negative = 1;  in parse_address_main()
5684   if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)  in parse_address_main()
5686       inst.operands[i].preind = 1;  in parse_address_main()
6139   inst.operands[0].reg = reg;  in parse_tb()
6152   inst.operands[0].imm = reg;  in parse_tb()
6163       inst.operands[0].shifted = 1;  in parse_tb()
6193       inst.operands[i].reg = val;  in parse_neon_mov()
6194       inst.operands[i].isscalar = 1;  in parse_neon_mov()
6195       inst.operands[i].vectype = optype;  in parse_neon_mov()
6196       inst.operands[i++].present = 1;  in parse_neon_mov()
6204       inst.operands[i].reg = val;  in parse_neon_mov()
6205       inst.operands[i].isreg = 1;  in parse_neon_mov()
6206       inst.operands[i].present = 1;  in parse_neon_mov()
6215       inst.operands[i].reg = val;  in parse_neon_mov()
6216       inst.operands[i].isreg = 1;  in parse_neon_mov()
6217       inst.operands[i].isquad = (rtype == REG_TYPE_NQ);  in parse_neon_mov()
6218       inst.operands[i].issingle = (rtype == REG_TYPE_VFS);  in parse_neon_mov()
6219       inst.operands[i].isvec = 1;  in parse_neon_mov()
6220       inst.operands[i].vectype = optype;  in parse_neon_mov()
6221       inst.operands[i++].present = 1;  in parse_neon_mov()
6227 	  inst.operands[i].reg = val;  in parse_neon_mov()
6228 	  inst.operands[i].isreg = 1;  in parse_neon_mov()
6229 	  inst.operands[i].present = 1;  in parse_neon_mov()
6243 	      inst.operands[i].reg = val;  in parse_neon_mov()
6244 	      inst.operands[i].isreg = 1;  in parse_neon_mov()
6245 	      inst.operands[i].present = 1;  in parse_neon_mov()
6256 	  inst.operands[i].reg = val;  in parse_neon_mov()
6257 	  inst.operands[i].isreg = 1;  in parse_neon_mov()
6258 	  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);  in parse_neon_mov()
6259 	  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);  in parse_neon_mov()
6260 	  inst.operands[i].isvec = 1;  in parse_neon_mov()
6261 	  inst.operands[i].vectype = optype;  in parse_neon_mov()
6262 	  inst.operands[i].present = 1;  in parse_neon_mov()
6272 	      inst.operands[i].reg = val;  in parse_neon_mov()
6273 	      inst.operands[i].isreg = 1;  in parse_neon_mov()
6274 	      inst.operands[i++].present = 1;  in parse_neon_mov()
6282 	      inst.operands[i].reg = val;  in parse_neon_mov()
6283 	      inst.operands[i].isreg = 1;  in parse_neon_mov()
6284 	      inst.operands[i].present = 1;  in parse_neon_mov()
6287       else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)  in parse_neon_mov()
6292 	inst.operands[i].immisfloat = 1;  in parse_neon_mov()
6307       inst.operands[i].reg = val;  in parse_neon_mov()
6308       inst.operands[i].isreg = 1;  in parse_neon_mov()
6309       inst.operands[i++].present = 1;  in parse_neon_mov()
6317 	  inst.operands[i].reg = val;  in parse_neon_mov()
6318 	  inst.operands[i].isscalar = 1;  in parse_neon_mov()
6319 	  inst.operands[i].present = 1;  in parse_neon_mov()
6320 	  inst.operands[i].vectype = optype;  in parse_neon_mov()
6325 	  inst.operands[i].reg = val;  in parse_neon_mov()
6326 	  inst.operands[i].isreg = 1;  in parse_neon_mov()
6327 	  inst.operands[i++].present = 1;  in parse_neon_mov()
6339 	  inst.operands[i].reg = val;  in parse_neon_mov()
6340 	  inst.operands[i].isreg = 1;  in parse_neon_mov()
6341 	  inst.operands[i].isvec = 1;  in parse_neon_mov()
6342 	  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);  in parse_neon_mov()
6343 	  inst.operands[i].vectype = optype;  in parse_neon_mov()
6344 	  inst.operands[i].present = 1;  in parse_neon_mov()
6358 	      inst.operands[i].reg = val;  in parse_neon_mov()
6359 	      inst.operands[i].isreg = 1;  in parse_neon_mov()
6360 	      inst.operands[i].isvec = 1;  in parse_neon_mov()
6361 	      inst.operands[i].issingle = 1;  in parse_neon_mov()
6362 	      inst.operands[i].vectype = optype;  in parse_neon_mov()
6363 	      inst.operands[i].present = 1;  in parse_neon_mov()
6370 	  inst.operands[i].reg = val;  in parse_neon_mov()
6371 	  inst.operands[i].isreg = 1;  in parse_neon_mov()
6372 	  inst.operands[i].isvec = 1;  in parse_neon_mov()
6373 	  inst.operands[i].issingle = 1;  in parse_neon_mov()
6374 	  inst.operands[i].vectype = optype;  in parse_neon_mov()
6375 	  inst.operands[i].present = 1;  in parse_neon_mov()
6561 				 & inst.operands[i].vectype);	\  in parse_operands()
6567       inst.operands[i].reg = val;				\  in parse_operands()
6568       inst.operands[i].isreg = 1;				\  in parse_operands()
6569       inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\  in parse_operands()
6570       inst.operands[i].issingle = (rtype == REG_TYPE_VFS);	\  in parse_operands()
6571       inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\  in parse_operands()
6581 				 & inst.operands[i].vectype);	\  in parse_operands()
6585       inst.operands[i].reg = val;				\  in parse_operands()
6586       inst.operands[i].isreg = 1;				\  in parse_operands()
6587       inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\  in parse_operands()
6588       inst.operands[i].issingle = (rtype == REG_TYPE_VFS);	\  in parse_operands()
6589       inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\  in parse_operands()
6600       inst.operands[i].imm = val;				\  in parse_operands()
6607       val = parse_scalar (& str, elsz, & inst.operands[i].vectype);	\  in parse_operands()
6610       inst.operands[i].reg = val;					\  in parse_operands()
6611       inst.operands[i].isscalar = 1;					\  in parse_operands()
6670       if (i > 0 && (i > 1 || inst.operands[0].present))  in parse_operands()
6737 	      inst.operands[i].imm = 0;  in parse_operands()
6825 	    inst.operands[i].writeback = 1;  in parse_operands()
6869 		inst.operands[i].writeback = 1;  in parse_operands()
6901 		  inst.operands[i].imm = val;  in parse_operands()
6902 		  inst.operands[i].hasreloc = 1;  in parse_operands()
6930 	  inst.operands[i].reg = val;  in parse_operands()
6931 	  inst.operands[i].isreg = 1;  in parse_operands()
6949 	    inst.operands[i].reg = rege->number;  in parse_operands()
6950 	    inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);  in parse_operands()
6964 	    inst.operands[i].reg = rege->number;  in parse_operands()
6965 	    inst.operands[i].isreg = 1;  in parse_operands()
7016 	      inst.operands[i].isvec = 1;  in parse_operands()
7018 	      inst.operands[i].reg = REG_PC;  in parse_operands()
7033 	      inst.operands[1].writeback = 1;  in parse_operands()
7039 	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);  in parse_operands()
7043 	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);  in parse_operands()
7048 	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg,  in parse_operands()
7053 	      val = parse_vfp_reg_list (&str, &inst.operands[i].reg,  in parse_operands()
7055 	      inst.operands[i].issingle = 1;  in parse_operands()
7060 	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg,  in parse_operands()
7065 	  val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,  in parse_operands()
7066 					   &inst.operands[i].vectype);  in parse_operands()
7125 	  if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)  in parse_operands()
7131 	  if (inst.operands[i].isreg)  in parse_operands()
7133 	      if (inst.operands[i].reg == REG_PC)  in parse_operands()
7135 	      else if (inst.operands[i].reg == REG_SP)  in parse_operands()
7141 	  if (inst.operands[i].isreg  in parse_operands()
7142 	      && inst.operands[i].reg == REG_PC  in parse_operands()
7143 	      && (inst.operands[i].writeback || thumb))  in parse_operands()
7162 	  inst.operands[i].imm = val;  in parse_operands()
7170       inst.operands[i].present = 1;  in parse_operands()
7201       inst.operands[backtrack_index].present = 0;  in parse_operands()
7360   if (inst.operands[i].shift_kind == SHIFT_RRX)  in encode_arm_shift()
7364       inst.instruction |= inst.operands[i].shift_kind << 5;  in encode_arm_shift()
7365       if (inst.operands[i].immisreg)  in encode_arm_shift()
7368 	  inst.instruction |= inst.operands[i].imm << 8;  in encode_arm_shift()
7378   if (inst.operands[i].isreg)  in encode_arm_shifter_operand()
7380       inst.instruction |= inst.operands[i].reg;  in encode_arm_shifter_operand()
7387 	inst.instruction |= inst.operands[i].imm;  in encode_arm_shifter_operand()
7397   constraint (!inst.operands[i].isreg,  in encode_arm_addr_mode_common()
7400   inst.instruction |= inst.operands[i].reg << 16;  in encode_arm_addr_mode_common()
7402   if (inst.operands[i].preind)  in encode_arm_addr_mode_common()
7410       if (inst.operands[i].writeback)  in encode_arm_addr_mode_common()
7414   else if (inst.operands[i].postind)  in encode_arm_addr_mode_common()
7416       gas_assert (inst.operands[i].writeback);  in encode_arm_addr_mode_common()
7441   const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);  in encode_arm_addr_mode_2()
7445   if (inst.operands[i].immisreg)  in encode_arm_addr_mode_2()
7447       constraint ((inst.operands[i].imm == REG_PC  in encode_arm_addr_mode_2()
7448 		   || (is_pc && inst.operands[i].writeback)),  in encode_arm_addr_mode_2()
7451       inst.instruction |= inst.operands[i].imm;  in encode_arm_addr_mode_2()
7452       if (!inst.operands[i].negative)  in encode_arm_addr_mode_2()
7454       if (inst.operands[i].shifted)  in encode_arm_addr_mode_2()
7456 	  if (inst.operands[i].shift_kind == SHIFT_RRX)  in encode_arm_addr_mode_2()
7460 	      inst.instruction |= inst.operands[i].shift_kind << 5;  in encode_arm_addr_mode_2()
7474 	  constraint ((is_t || inst.operands[i].writeback),  in encode_arm_addr_mode_2()
7487 	  if (!inst.operands[i].negative)  in encode_arm_addr_mode_2()
7502   if (inst.operands[i].immisreg && inst.operands[i].shifted)  in encode_arm_addr_mode_3()
7510   if (inst.operands[i].immisreg)  in encode_arm_addr_mode_3()
7512       constraint ((inst.operands[i].imm == REG_PC  in encode_arm_addr_mode_3()
7513 		   || (is_t && inst.operands[i].reg == REG_PC)),  in encode_arm_addr_mode_3()
7515       constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,  in encode_arm_addr_mode_3()
7517       inst.instruction |= inst.operands[i].imm;  in encode_arm_addr_mode_3()
7518       if (!inst.operands[i].negative)  in encode_arm_addr_mode_3()
7523       constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel  in encode_arm_addr_mode_3()
7524 		   && inst.operands[i].writeback),  in encode_arm_addr_mode_3()
7530 	  if (!inst.operands[i].negative)  in encode_arm_addr_mode_3()
7751   bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;  in move_or_literal_pool()
7772       && !inst.operands[i].issingle)  in move_or_literal_pool()
7779 	      inst.instruction	= T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);  in move_or_literal_pool()
7810 	  unsigned immlo = inst.operands[1].imm;  in move_or_literal_pool()
7811 	  unsigned immhi = inst.operands[1].regisimm  in move_or_literal_pool()
7812 			   ? inst.operands[1].reg  in move_or_literal_pool()
7844   if (add_to_lit_pool ((!inst.operands[i].isvec  in move_or_literal_pool()
7845 			|| inst.operands[i].issingle) ? 4 : 8) == FAIL)  in move_or_literal_pool()
7848   inst.operands[1].reg = REG_PC;  in move_or_literal_pool()
7849   inst.operands[1].isreg = 1;  in move_or_literal_pool()
7850   inst.operands[1].preind = 1;  in move_or_literal_pool()
7871   if (!inst.operands[i].isreg)  in encode_arm_cp_address()
7873       gas_assert (inst.operands[0].isvec);  in encode_arm_cp_address()
7878   inst.instruction |= inst.operands[i].reg << 16;  in encode_arm_cp_address()
7880   gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));  in encode_arm_cp_address()
7882   if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */  in encode_arm_cp_address()
7884       gas_assert (!inst.operands[i].writeback);  in encode_arm_cp_address()
7890       inst.instruction |= inst.operands[i].imm;  in encode_arm_cp_address()
7895   if (inst.operands[i].preind)  in encode_arm_cp_address()
7898   if (inst.operands[i].writeback)  in encode_arm_cp_address()
7900       if (inst.operands[i].reg == REG_PC)  in encode_arm_cp_address()
7926   if (!inst.operands[i].negative)  in encode_arm_cp_address()
7944   inst.instruction |= inst.operands[0].reg << 12;  in do_rd()
7950   inst.instruction |= inst.operands[0].reg << 12;  in do_rd_rm()
7951   inst.instruction |= inst.operands[1].reg;  in do_rd_rm()
7957   inst.instruction |= inst.operands[0].reg;  in do_rm_rn()
7958   inst.instruction |= inst.operands[1].reg << 16;  in do_rm_rn()
7964   inst.instruction |= inst.operands[0].reg << 12;  in do_rd_rn()
7965   inst.instruction |= inst.operands[1].reg << 16;  in do_rd_rn()
7971   inst.instruction |= inst.operands[0].reg << 16;  in do_rn_rd()
7972   inst.instruction |= inst.operands[1].reg << 12;  in do_rn_rd()
7995   unsigned Rn = inst.operands[2].reg;  in do_rd_rm_rn()
7999       constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,  in do_rd_rm_rn()
8011   inst.instruction |= inst.operands[0].reg << 12;  in do_rd_rm_rn()
8012   inst.instruction |= inst.operands[1].reg;  in do_rd_rm_rn()
8019   inst.instruction |= inst.operands[0].reg << 12;  in do_rd_rn_rm()
8020   inst.instruction |= inst.operands[1].reg << 16;  in do_rd_rn_rm()
8021   inst.instruction |= inst.operands[2].reg;  in do_rd_rn_rm()
8027   constraint ((inst.operands[2].reg == REG_PC), BAD_PC);  in do_rm_rd_rn()
8032   inst.instruction |= inst.operands[0].reg;  in do_rm_rd_rn()
8033   inst.instruction |= inst.operands[1].reg << 12;  in do_rm_rd_rn()
8034   inst.instruction |= inst.operands[2].reg << 16;  in do_rm_rd_rn()
8040   inst.instruction |= inst.operands[0].imm;  in do_imm0()
8046   inst.instruction |= inst.operands[0].reg << 12;  in do_rd_cpaddr()
8060   inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */  in do_adr()
8077   inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */  in do_adrl()
8090   if (!inst.operands[1].present)  in do_arit()
8091     inst.operands[1].reg = inst.operands[0].reg;  in do_arit()
8092   inst.instruction |= inst.operands[0].reg << 12;  in do_arit()
8093   inst.instruction |= inst.operands[1].reg << 16;  in do_arit()
8100   if (inst.operands[0].present)  in do_barrier()
8101     inst.instruction |= inst.operands[0].imm;  in do_barrier()
8109   unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;  in do_bfc()
8113   inst.instruction |= inst.operands[0].reg << 12;  in do_bfc()
8114   inst.instruction |= inst.operands[1].imm << 7;  in do_bfc()
8125   if (!inst.operands[1].isreg)  in do_bfi()
8126     inst.operands[1].reg = REG_PC;  in do_bfi()
8128   msb = inst.operands[2].imm + inst.operands[3].imm;  in do_bfi()
8132   inst.instruction |= inst.operands[0].reg << 12;  in do_bfi()
8133   inst.instruction |= inst.operands[1].reg;  in do_bfi()
8134   inst.instruction |= inst.operands[2].imm << 7;  in do_bfi()
8141   constraint (inst.operands[2].imm + inst.operands[3].imm > 32,  in do_bfx()
8143   inst.instruction |= inst.operands[0].reg << 12;  in do_bfx()
8144   inst.instruction |= inst.operands[1].reg;  in do_bfx()
8145   inst.instruction |= inst.operands[2].imm << 7;  in do_bfx()
8146   inst.instruction |= (inst.operands[3].imm - 1) << 16;  in do_bfx()
8159   inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;  in do_bkpt()
8162   inst.instruction |= inst.operands[0].imm & 0xf;  in do_bkpt()
8168   if (inst.operands[0].hasreloc)  in encode_branch()
8170       constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32  in encode_branch()
8171 		  && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,  in encode_branch()
8173       inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32  in encode_branch()
8220   if (inst.operands[0].isreg)  in do_blx()
8224       if (inst.operands[0].reg == REG_PC)  in do_blx()
8227       inst.instruction |= inst.operands[0].reg;  in do_blx()
8246   if (inst.operands[0].reg == REG_PC)  in do_bx()
8249   inst.instruction |= inst.operands[0].reg;  in do_bx()
8271   if (inst.operands[0].reg == REG_PC)  in do_bxj()
8274   inst.instruction |= inst.operands[0].reg;  in do_bxj()
8283   inst.instruction |= inst.operands[0].reg << 8;  in do_cdp()
8284   inst.instruction |= inst.operands[1].imm << 20;  in do_cdp()
8285   inst.instruction |= inst.operands[2].reg << 12;  in do_cdp()
8286   inst.instruction |= inst.operands[3].reg << 16;  in do_cdp()
8287   inst.instruction |= inst.operands[4].reg;  in do_cdp()
8288   inst.instruction |= inst.operands[5].imm << 5;  in do_cdp()
8294   inst.instruction |= inst.operands[0].reg << 16;  in do_cmp()
8353   Rd = inst.operands[2].reg;  in do_co_reg()
8376 	if (inst.operands[0].reg == r->cp  in do_co_reg()
8377 	    && inst.operands[1].imm == r->opc1  in do_co_reg()
8378 	    && inst.operands[3].reg == r->crn  in do_co_reg()
8379 	    && inst.operands[4].reg == r->crm  in do_co_reg()
8380 	    && inst.operands[5].imm == r->opc2)  in do_co_reg()
8389   inst.instruction |= inst.operands[0].reg << 8;  in do_co_reg()
8390   inst.instruction |= inst.operands[1].imm << 21;  in do_co_reg()
8392   inst.instruction |= inst.operands[3].reg << 16;  in do_co_reg()
8393   inst.instruction |= inst.operands[4].reg;  in do_co_reg()
8394   inst.instruction |= inst.operands[5].imm << 5;  in do_co_reg()
8415   Rd = inst.operands[2].reg;  in do_co_reg2c()
8416   Rn = inst.operands[3].reg;  in do_co_reg2c()
8429   inst.instruction |= inst.operands[0].reg << 8;  in do_co_reg2c()
8430   inst.instruction |= inst.operands[1].imm << 4;  in do_co_reg2c()
8433   inst.instruction |= inst.operands[4].reg;  in do_co_reg2c()
8439   inst.instruction |= inst.operands[0].imm << 6;  in do_cpsi()
8440   if (inst.operands[1].present)  in do_cpsi()
8443       inst.instruction |= inst.operands[1].imm;  in do_cpsi()
8450   inst.instruction |= inst.operands[0].imm;  in do_dbg()
8458   Rd = inst.operands[0].reg;  in do_div()
8459   Rn = (inst.operands[1].present  in do_div()
8460 	? inst.operands[1].reg : Rd);  in do_div()
8461   Rm = inst.operands[2].reg;  in do_div()
8485       now_it.cc = inst.operands[0].imm;  in do_it()
8501   int base_reg = inst.operands[0].reg;  in encode_ldmstm()
8502   int range = inst.operands[1].imm;  in encode_ldmstm()
8508   if (inst.operands[1].writeback)  in encode_ldmstm()
8511   if (inst.operands[0].writeback)  in encode_ldmstm()
8564   constraint (inst.operands[0].reg % 2 != 0,  in do_ldrd()
8566   constraint (inst.operands[1].present  in do_ldrd()
8567 	      && inst.operands[1].reg != inst.operands[0].reg + 1,  in do_ldrd()
8569   constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));  in do_ldrd()
8570   constraint (!inst.operands[2].isreg, _("'[' expected"));  in do_ldrd()
8572   if (!inst.operands[1].present)  in do_ldrd()
8573     inst.operands[1].reg = inst.operands[0].reg + 1;  in do_ldrd()
8579   if (inst.operands[2].reg == inst.operands[1].reg  in do_ldrd()
8580       && (inst.operands[2].writeback || inst.operands[2].postind))  in do_ldrd()
8588       if (inst.operands[2].immisreg  in do_ldrd()
8589 	      && ((unsigned) inst.operands[2].imm == inst.operands[0].reg  in do_ldrd()
8590 	      || (unsigned) inst.operands[2].imm == inst.operands[1].reg))  in do_ldrd()
8593   inst.instruction |= inst.operands[0].reg << 12;  in do_ldrd()
8600   constraint (!inst.operands[1].isreg || !inst.operands[1].preind  in do_ldrex()
8601 	      || inst.operands[1].postind || inst.operands[1].writeback  in do_ldrex()
8602 	      || inst.operands[1].immisreg || inst.operands[1].shifted  in do_ldrex()
8603 	      || inst.operands[1].negative  in do_ldrex()
8615 	      || (inst.operands[1].reg == REG_PC),  in do_ldrex()
8622   constraint ((inst.operands[1].reg == REG_PC), BAD_PC);  in do_ldrex()
8624   inst.instruction |= inst.operands[0].reg << 12;  in do_ldrex()
8625   inst.instruction |= inst.operands[1].reg << 16;  in do_ldrex()
8632   constraint (inst.operands[0].reg % 2 != 0,  in do_ldrexd()
8634   constraint (inst.operands[1].present  in do_ldrexd()
8635 	      && inst.operands[1].reg != inst.operands[0].reg + 1,  in do_ldrexd()
8639   constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));  in do_ldrexd()
8641   inst.instruction |= inst.operands[0].reg << 12;  in do_ldrexd()
8642   inst.instruction |= inst.operands[2].reg << 16;  in do_ldrexd()
8650   constraint (!(inst.operands[1].immisreg)  in check_ldr_r15_aligned()
8651 	      && (inst.operands[0].reg == REG_PC  in check_ldr_r15_aligned()
8652 	      && inst.operands[1].reg == REG_PC  in check_ldr_r15_aligned()
8660   inst.instruction |= inst.operands[0].reg << 12;  in do_ldst()
8661   if (!inst.operands[1].isreg)  in do_ldst()
8673   if (inst.operands[1].preind)  in do_ldstt()
8679       inst.operands[1].preind = 0;  in do_ldstt()
8680       inst.operands[1].postind = 1;  in do_ldstt()
8681       inst.operands[1].writeback = 1;  in do_ldstt()
8683   inst.instruction |= inst.operands[0].reg << 12;  in do_ldstt()
8692   constraint (inst.operands[0].reg == REG_PC, BAD_PC);  in do_ldstv4()
8693   inst.instruction |= inst.operands[0].reg << 12;  in do_ldstv4()
8694   if (!inst.operands[1].isreg)  in do_ldstv4()
8705   if (inst.operands[1].preind)  in do_ldsttv4()
8711       inst.operands[1].preind = 0;  in do_ldsttv4()
8712       inst.operands[1].postind = 1;  in do_ldsttv4()
8713       inst.operands[1].writeback = 1;  in do_ldsttv4()
8715   inst.instruction |= inst.operands[0].reg << 12;  in do_ldsttv4()
8724   inst.instruction |= inst.operands[0].reg << 8;  in do_lstc()
8725   inst.instruction |= inst.operands[1].reg << 12;  in do_lstc()
8733   if (inst.operands[0].reg == inst.operands[1].reg  in do_mlas()
8738   inst.instruction |= inst.operands[0].reg << 16;  in do_mlas()
8739   inst.instruction |= inst.operands[1].reg;  in do_mlas()
8740   inst.instruction |= inst.operands[2].reg << 8;  in do_mlas()
8741   inst.instruction |= inst.operands[3].reg << 12;  in do_mlas()
8747   inst.instruction |= inst.operands[0].reg << 12;  in do_mov()
8763   inst.instruction |= inst.operands[0].reg << 12;  in do_mov16()
8778   if (inst.operands[0].isvec)  in do_vfp_nsyn_mrs()
8780       if (inst.operands[1].reg != 1)  in do_vfp_nsyn_mrs()
8782       memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));  in do_vfp_nsyn_mrs()
8783       memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));  in do_vfp_nsyn_mrs()
8786   else if (inst.operands[1].isvec)  in do_vfp_nsyn_mrs()
8797   if (inst.operands[0].isvec)  in do_vfp_nsyn_msr()
8808   unsigned Rt = inst.operands[0].reg;  in do_vmrs()
8817   if (!inst.operands[0].isvec && Rt == REG_PC)  in do_vmrs()
8825   inst.instruction |= (inst.operands[1].reg << 16);  in do_vmrs()
8832   unsigned Rt = inst.operands[1].reg;  in do_vmsr()
8844   inst.instruction |= (inst.operands[0].reg << 16);  in do_vmsr()
8856   constraint (inst.operands[0].reg == REG_PC, BAD_PC);  in do_mrs()
8857   inst.instruction |= inst.operands[0].reg << 12;  in do_mrs()
8859   if (inst.operands[1].isreg)  in do_mrs()
8861       br = inst.operands[1].reg;  in do_mrs()
8868       constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))  in do_mrs()
8871       br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);  in do_mrs()
8887   inst.instruction |= inst.operands[0].imm;  in do_msr()
8888   if (inst.operands[1].isreg)  in do_msr()
8889     inst.instruction |= inst.operands[1].reg;  in do_msr()
8901   constraint (inst.operands[2].reg == REG_PC, BAD_PC);  in do_mul()
8903   if (!inst.operands[2].present)  in do_mul()
8904     inst.operands[2].reg = inst.operands[0].reg;  in do_mul()
8905   inst.instruction |= inst.operands[0].reg << 16;  in do_mul()
8906   inst.instruction |= inst.operands[1].reg;  in do_mul()
8907   inst.instruction |= inst.operands[2].reg << 8;  in do_mul()
8909   if (inst.operands[0].reg == inst.operands[1].reg  in do_mul()
8923   inst.instruction |= inst.operands[0].reg << 12;  in do_mull()
8924   inst.instruction |= inst.operands[1].reg << 16;  in do_mull()
8925   inst.instruction |= inst.operands[2].reg;  in do_mull()
8926   inst.instruction |= inst.operands[3].reg << 8;  in do_mull()
8929   if (inst.operands[0].reg == inst.operands[1].reg)  in do_mull()
8933   if ((inst.operands[0].reg == inst.operands[2].reg  in do_mull()
8934       || inst.operands[1].reg == inst.operands[2].reg)  in do_mull()
8942   if (inst.operands[0].present  in do_nop()
8948       if (inst.operands[0].present)  in do_nop()
8949 	inst.instruction |= inst.operands[0].imm;  in do_nop()
8961   inst.instruction |= inst.operands[0].reg << 12;  in do_pkhbt()
8962   inst.instruction |= inst.operands[1].reg << 16;  in do_pkhbt()
8963   inst.instruction |= inst.operands[2].reg;  in do_pkhbt()
8964   if (inst.operands[3].present)  in do_pkhbt()
8973   if (!inst.operands[3].present)  in do_pkhtb()
8978       inst.instruction |= inst.operands[0].reg << 12;  in do_pkhtb()
8979       inst.instruction |= inst.operands[1].reg;  in do_pkhtb()
8980       inst.instruction |= inst.operands[2].reg << 16;  in do_pkhtb()
8984       inst.instruction |= inst.operands[0].reg << 12;  in do_pkhtb()
8985       inst.instruction |= inst.operands[1].reg << 16;  in do_pkhtb()
8986       inst.instruction |= inst.operands[2].reg;  in do_pkhtb()
9001   constraint (!inst.operands[0].isreg,  in do_pld()
9003   constraint (inst.operands[0].postind,  in do_pld()
9005   constraint (inst.operands[0].writeback,  in do_pld()
9007   constraint (!inst.operands[0].preind,  in do_pld()
9016   constraint (!inst.operands[0].isreg,  in do_pli()
9018   constraint (inst.operands[0].postind,  in do_pli()
9020   constraint (inst.operands[0].writeback,  in do_pli()
9022   constraint (!inst.operands[0].preind,  in do_pli()
9031   inst.operands[1] = inst.operands[0];  in do_push_pop()
9032   memset (&inst.operands[0], 0, sizeof inst.operands[0]);  in do_push_pop()
9033   inst.operands[0].isreg = 1;  in do_push_pop()
9034   inst.operands[0].writeback = 1;  in do_push_pop()
9035   inst.operands[0].reg = REG_SP;  in do_push_pop()
9048   inst.instruction |= inst.operands[0].reg << 16;  in do_rfe()
9049   if (inst.operands[0].writeback)  in do_rfe()
9058   inst.instruction |= inst.operands[0].reg << 12;  in do_ssat()
9059   inst.instruction |= (inst.operands[1].imm - 1) << 16;  in do_ssat()
9060   inst.instruction |= inst.operands[2].reg;  in do_ssat()
9062   if (inst.operands[3].present)  in do_ssat()
9071   inst.instruction |= inst.operands[0].reg << 12;  in do_usat()
9072   inst.instruction |= inst.operands[1].imm << 16;  in do_usat()
9073   inst.instruction |= inst.operands[2].reg;  in do_usat()
9075   if (inst.operands[3].present)  in do_usat()
9084   inst.instruction |= inst.operands[0].reg << 12;  in do_ssat16()
9085   inst.instruction |= ((inst.operands[1].imm - 1) << 16);  in do_ssat16()
9086   inst.instruction |= inst.operands[2].reg;  in do_ssat16()
9092   inst.instruction |= inst.operands[0].reg << 12;  in do_usat16()
9093   inst.instruction |= inst.operands[1].imm << 16;  in do_usat16()
9094   inst.instruction |= inst.operands[2].reg;  in do_usat16()
9110   if (inst.operands[0].imm)  in do_setend()
9117   unsigned int Rm = (inst.operands[1].present  in do_shift()
9118 		     ? inst.operands[1].reg  in do_shift()
9119 		     : inst.operands[0].reg);  in do_shift()
9121   inst.instruction |= inst.operands[0].reg << 12;  in do_shift()
9123   if (inst.operands[2].isreg)  /* Rd, {Rm,} Rs */  in do_shift()
9125       inst.instruction |= inst.operands[2].reg << 8;  in do_shift()
9128       constraint (inst.operands[2].shifted,  in do_shift()
9164   inst.instruction |= inst.operands[0].reg << 16;  in do_smla()
9165   inst.instruction |= inst.operands[1].reg;  in do_smla()
9166   inst.instruction |= inst.operands[2].reg << 8;  in do_smla()
9167   inst.instruction |= inst.operands[3].reg << 12;  in do_smla()
9178   inst.instruction |= inst.operands[0].reg << 12;  in do_smlal()
9179   inst.instruction |= inst.operands[1].reg << 16;  in do_smlal()
9180   inst.instruction |= inst.operands[2].reg;  in do_smlal()
9181   inst.instruction |= inst.operands[3].reg << 8;  in do_smlal()
9183   if (inst.operands[0].reg == inst.operands[1].reg)  in do_smlal()
9194   inst.instruction |= inst.operands[0].reg << 16;  in do_smul()
9195   inst.instruction |= inst.operands[1].reg;  in do_smul()
9196   inst.instruction |= inst.operands[2].reg << 8;  in do_smul()
9207   if (inst.operands[0].present)  in do_srs()
9209       reg = inst.operands[0].reg;  in do_srs()
9216   inst.instruction |= inst.operands[1].imm;  in do_srs()
9217   if (inst.operands[0].writeback || inst.operands[1].writeback)  in do_srs()
9226   constraint (!inst.operands[2].isreg || !inst.operands[2].preind  in do_strex()
9227 	      || inst.operands[2].postind || inst.operands[2].writeback  in do_strex()
9228 	      || inst.operands[2].immisreg || inst.operands[2].shifted  in do_strex()
9229 	      || inst.operands[2].negative  in do_strex()
9231 	      || (inst.operands[2].reg == REG_PC),  in do_strex()
9234   constraint (inst.operands[0].reg == inst.operands[1].reg  in do_strex()
9235 	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);  in do_strex()
9241   inst.instruction |= inst.operands[0].reg << 12;  in do_strex()
9242   inst.instruction |= inst.operands[1].reg;  in do_strex()
9243   inst.instruction |= inst.operands[2].reg << 16;  in do_strex()
9250   constraint (!inst.operands[2].isreg || !inst.operands[2].preind  in do_t_strexbh()
9251 	      || inst.operands[2].postind || inst.operands[2].writeback  in do_t_strexbh()
9252 	      || inst.operands[2].immisreg || inst.operands[2].shifted  in do_t_strexbh()
9253 	      || inst.operands[2].negative,  in do_t_strexbh()
9256   constraint (inst.operands[0].reg == inst.operands[1].reg  in do_t_strexbh()
9257 	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);  in do_t_strexbh()
9265   constraint (inst.operands[1].reg % 2 != 0,  in do_strexd()
9267   constraint (inst.operands[2].present  in do_strexd()
9268 	      && inst.operands[2].reg != inst.operands[1].reg + 1,  in do_strexd()
9272   constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));  in do_strexd()
9274   constraint (inst.operands[0].reg == inst.operands[1].reg  in do_strexd()
9275 	      || inst.operands[0].reg == inst.operands[1].reg + 1  in do_strexd()
9276 	      || inst.operands[0].reg == inst.operands[3].reg,  in do_strexd()
9279   inst.instruction |= inst.operands[0].reg << 12;  in do_strexd()
9280   inst.instruction |= inst.operands[1].reg;  in do_strexd()
9281   inst.instruction |= inst.operands[3].reg << 16;  in do_strexd()
9288   constraint (inst.operands[0].reg == inst.operands[1].reg  in do_stlex()
9289 	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);  in do_stlex()
9297   constraint (inst.operands[0].reg == inst.operands[1].reg  in do_t_stlex()
9298 	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);  in do_t_stlex()
9314   inst.instruction |= inst.operands[0].reg << 12;  in do_sxtah()
9315   inst.instruction |= inst.operands[1].reg << 16;  in do_sxtah()
9316   inst.instruction |= inst.operands[2].reg;  in do_sxtah()
9317   inst.instruction |= inst.operands[3].imm << 10;  in do_sxtah()
9329   inst.instruction |= inst.operands[0].reg << 12;  in do_sxth()
9330   inst.instruction |= inst.operands[1].reg;  in do_sxth()
9331   inst.instruction |= inst.operands[2].imm << 10;  in do_sxth()
9340   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_monadic()
9341   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);  in do_vfp_sp_monadic()
9347   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_dyadic()
9348   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);  in do_vfp_sp_dyadic()
9349   encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);  in do_vfp_sp_dyadic()
9355   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_compare_z()
9361   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_sp_cvt()
9362   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);  in do_vfp_dp_sp_cvt()
9368   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_dp_cvt()
9369   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);  in do_vfp_sp_dp_cvt()
9375   inst.instruction |= inst.operands[0].reg << 12;  in do_vfp_reg_from_sp()
9376   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);  in do_vfp_reg_from_sp()
9382   constraint (inst.operands[2].imm != 2,  in do_vfp_reg2_from_sp2()
9384   inst.instruction |= inst.operands[0].reg << 12;  in do_vfp_reg2_from_sp2()
9385   inst.instruction |= inst.operands[1].reg << 16;  in do_vfp_reg2_from_sp2()
9386   encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);  in do_vfp_reg2_from_sp2()
9392   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);  in do_vfp_sp_from_reg()
9393   inst.instruction |= inst.operands[1].reg << 12;  in do_vfp_sp_from_reg()
9399   constraint (inst.operands[0].imm != 2,  in do_vfp_sp2_from_reg2()
9401   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);  in do_vfp_sp2_from_reg2()
9402   inst.instruction |= inst.operands[1].reg << 12;  in do_vfp_sp2_from_reg2()
9403   inst.instruction |= inst.operands[2].reg << 16;  in do_vfp_sp2_from_reg2()
9409   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_ldst()
9416   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_ldst()
9424   if (inst.operands[0].writeback)  in vfp_sp_ldstm()
9429   inst.instruction |= inst.operands[0].reg << 16;  in vfp_sp_ldstm()
9430   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);  in vfp_sp_ldstm()
9431   inst.instruction |= inst.operands[1].imm;  in vfp_sp_ldstm()
9439   if (inst.operands[0].writeback)  in vfp_dp_ldstm()
9445   inst.instruction |= inst.operands[0].reg << 16;  in vfp_dp_ldstm()
9446   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);  in vfp_dp_ldstm()
9448   count = inst.operands[1].imm << 1;  in vfp_dp_ldstm()
9494   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_rd_rm()
9495   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);  in do_vfp_dp_rd_rm()
9501   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);  in do_vfp_dp_rn_rd()
9502   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);  in do_vfp_dp_rn_rd()
9508   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_rd_rn()
9509   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);  in do_vfp_dp_rd_rn()
9515   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_rd_rn_rm()
9516   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);  in do_vfp_dp_rd_rn_rm()
9517   encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);  in do_vfp_dp_rd_rn_rm()
9523   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_rd()
9529   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);  in do_vfp_dp_rm_rd_rn()
9530   encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);  in do_vfp_dp_rm_rd_rn()
9531   encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);  in do_vfp_dp_rm_rd_rn()
9538   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_const()
9539   inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;  in do_vfp_sp_const()
9540   inst.instruction |= (inst.operands[1].imm & 0x0f);  in do_vfp_sp_const()
9546   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_const()
9547   inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;  in do_vfp_dp_const()
9548   inst.instruction |= (inst.operands[1].imm & 0x0f);  in do_vfp_dp_const()
9554   int immbits = srcsize - inst.operands[1].imm;  in vfp_conv()
9578   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_conv_16()
9585   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_conv_16()
9592   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_sp_conv_32()
9599   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);  in do_vfp_dp_conv_32()
9608   inst.instruction |= inst.operands[0].reg << 16;  in do_fpa_cmp()
9609   inst.instruction |= inst.operands[1].reg;  in do_fpa_cmp()
9615   inst.instruction |= inst.operands[0].reg << 12;  in do_fpa_ldmstm()
9616   switch (inst.operands[1].imm)  in do_fpa_ldmstm()
9635       if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)  in do_fpa_ldmstm()
9636 	inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;  in do_fpa_ldmstm()
9641       if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)  in do_fpa_ldmstm()
9643 	  inst.operands[2].preind = 0;  in do_fpa_ldmstm()
9644 	  inst.operands[2].postind = 1;  in do_fpa_ldmstm()
9656   constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));  in do_iwmmxt_tandorc()
9662   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_textrc()
9663   inst.instruction |= inst.operands[1].imm;  in do_iwmmxt_textrc()
9669   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_textrm()
9670   inst.instruction |= inst.operands[1].reg << 16;  in do_iwmmxt_textrm()
9671   inst.instruction |= inst.operands[2].imm;  in do_iwmmxt_textrm()
9677   inst.instruction |= inst.operands[0].reg << 16;  in do_iwmmxt_tinsr()
9678   inst.instruction |= inst.operands[1].reg << 12;  in do_iwmmxt_tinsr()
9679   inst.instruction |= inst.operands[2].imm;  in do_iwmmxt_tinsr()
9685   inst.instruction |= inst.operands[0].reg << 5;  in do_iwmmxt_tmia()
9686   inst.instruction |= inst.operands[1].reg;  in do_iwmmxt_tmia()
9687   inst.instruction |= inst.operands[2].reg << 12;  in do_iwmmxt_tmia()
9693   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_waligni()
9694   inst.instruction |= inst.operands[1].reg << 16;  in do_iwmmxt_waligni()
9695   inst.instruction |= inst.operands[2].reg;  in do_iwmmxt_waligni()
9696   inst.instruction |= inst.operands[3].imm << 20;  in do_iwmmxt_waligni()
9702   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wmerge()
9703   inst.instruction |= inst.operands[1].reg << 16;  in do_iwmmxt_wmerge()
9704   inst.instruction |= inst.operands[2].reg;  in do_iwmmxt_wmerge()
9705   inst.instruction |= inst.operands[3].imm << 21;  in do_iwmmxt_wmerge()
9712   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wmov()
9713   inst.instruction |= inst.operands[1].reg << 16;  in do_iwmmxt_wmov()
9714   inst.instruction |= inst.operands[1].reg;  in do_iwmmxt_wmov()
9721   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wldstbh()
9733   if (!inst.operands[0].isreg)  in do_iwmmxt_wldstw()
9739   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wldstw()
9746   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wldstd()
9748       && inst.operands[1].immisreg)  in do_iwmmxt_wldstd()
9752       if (inst.operands[1].preind)  in do_iwmmxt_wldstd()
9754       if (!inst.operands[1].negative)  in do_iwmmxt_wldstd()
9756       if (inst.operands[1].writeback)  in do_iwmmxt_wldstd()
9758       inst.instruction |= inst.operands[1].reg << 16;  in do_iwmmxt_wldstd()
9760       inst.instruction |= inst.operands[1].imm;  in do_iwmmxt_wldstd()
9769   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wshufh()
9770   inst.instruction |= inst.operands[1].reg << 16;  in do_iwmmxt_wshufh()
9771   inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);  in do_iwmmxt_wshufh()
9772   inst.instruction |= (inst.operands[2].imm & 0x0f);  in do_iwmmxt_wshufh()
9779   inst.instruction |= inst.operands[0].reg;  in do_iwmmxt_wzero()
9780   inst.instruction |= inst.operands[0].reg << 12;  in do_iwmmxt_wzero()
9781   inst.instruction |= inst.operands[0].reg << 16;  in do_iwmmxt_wzero()
9787   if (inst.operands[2].isreg)  in do_iwmmxt_wrwrwr_or_imm5()
9793     if (inst.operands[2].imm == 0)  in do_iwmmxt_wrwrwr_or_imm5()
9802 	    inst.operands[2].imm = 16;  in do_iwmmxt_wrwrwr_or_imm5()
9810 	    inst.operands[2].imm = 32;  in do_iwmmxt_wrwrwr_or_imm5()
9829     inst.operands[2].imm &= 0x1f;  in do_iwmmxt_wrwrwr_or_imm5()
9830 …inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0…  in do_iwmmxt_wrwrwr_or_imm5()
9842   inst.instruction |= inst.operands[0].reg << 16;  in do_mav_triple()
9843   inst.instruction |= inst.operands[1].reg;  in do_mav_triple()
9844   inst.instruction |= inst.operands[2].reg << 12;  in do_mav_triple()
9853   inst.instruction |= inst.operands[0].reg << 5;  in do_mav_quad()
9854   inst.instruction |= inst.operands[1].reg << 12;  in do_mav_quad()
9855   inst.instruction |= inst.operands[2].reg << 16;  in do_mav_quad()
9856   inst.instruction |= inst.operands[3].reg;  in do_mav_quad()
9863   inst.instruction |= inst.operands[1].reg << 12;  in do_mav_dspsc()
9873   int imm = inst.operands[2].imm;  in do_mav_shift()
9875   inst.instruction |= inst.operands[0].reg << 12;  in do_mav_shift()
9876   inst.instruction |= inst.operands[1].reg << 16;  in do_mav_shift()
9896   inst.instruction |= inst.operands[1].reg;  in do_xsc_mia()
9897   inst.instruction |= inst.operands[2].reg << 12;  in do_xsc_mia()
9907   inst.instruction |= inst.operands[1].reg << 12;  in do_xsc_mar()
9908   inst.instruction |= inst.operands[2].reg << 16;  in do_xsc_mar()
9918   constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);  in do_xsc_mra()
9919   inst.instruction |= inst.operands[0].reg << 12;  in do_xsc_mra()
9920   inst.instruction |= inst.operands[1].reg << 16;  in do_xsc_mra()
9932   unsigned int shift = inst.operands[i].shift_kind;  in encode_thumb32_shifted_operand()
9934   constraint (inst.operands[i].immisreg,  in encode_thumb32_shifted_operand()
9936   inst.instruction |= inst.operands[i].reg;  in encode_thumb32_shifted_operand()
9971   const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);  in encode_thumb32_addr_mode()
9973   constraint (!inst.operands[i].isreg,  in encode_thumb32_addr_mode()
9976   inst.instruction |= inst.operands[i].reg << 16;  in encode_thumb32_addr_mode()
9977   if (inst.operands[i].immisreg)  in encode_thumb32_addr_mode()
9981       constraint (inst.operands[i].negative,  in encode_thumb32_addr_mode()
9983       constraint (inst.operands[i].postind,  in encode_thumb32_addr_mode()
9985       constraint (inst.operands[i].writeback,  in encode_thumb32_addr_mode()
9987       constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,  in encode_thumb32_addr_mode()
9990       inst.instruction |= inst.operands[i].imm;  in encode_thumb32_addr_mode()
9991       if (inst.operands[i].shifted)  in encode_thumb32_addr_mode()
10002   else if (inst.operands[i].preind)  in encode_thumb32_addr_mode()
10004       constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);  in encode_thumb32_addr_mode()
10005       constraint (is_t && inst.operands[i].writeback,  in encode_thumb32_addr_mode()
10013 	  if (inst.operands[i].writeback)  in encode_thumb32_addr_mode()
10019 	  if (inst.operands[i].writeback)  in encode_thumb32_addr_mode()
10024   else if (inst.operands[i].postind)  in encode_thumb32_addr_mode()
10026       gas_assert (inst.operands[i].writeback);  in encode_thumb32_addr_mode()
10155   Rd = inst.operands[0].reg;  in do_t_add_sub_w()
10156   Rn = inst.operands[1].reg;  in do_t_add_sub_w()
10177   Rd = inst.operands[0].reg;  in do_t_add_sub()
10178   Rs = (inst.operands[1].present  in do_t_add_sub()
10179 	? inst.operands[1].reg    /* Rd, Rs, foo */  in do_t_add_sub()
10180 	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */  in do_t_add_sub()
10197       if (!inst.operands[2].isreg)  in do_t_add_sub()
10275 	  unsigned int shift = inst.operands[2].shift_kind;  in do_t_add_sub()
10277 	  Rn = inst.operands[2].reg;  in do_t_add_sub()
10279 	  if (!inst.operands[2].shifted && inst.size_req != 4)  in do_t_add_sub()
10322 	  constraint (inst.operands[2].shifted && inst.operands[2].immisreg,  in do_t_add_sub()
10340       if (!inst.operands[2].isreg) /* Rd, Rs, #imm */  in do_t_add_sub()
10353       Rn = inst.operands[2].reg;  in do_t_add_sub()
10354       constraint (inst.operands[2].shifted, _("unshifted register required"));  in do_t_add_sub()
10385   Rd = inst.operands[0].reg;  in do_t_adr()
10426   Rd = inst.operands[0].reg;  in do_t_arit3()
10427   Rs = (inst.operands[1].present  in do_t_arit3()
10428 	? inst.operands[1].reg    /* Rd, Rs, foo */  in do_t_arit3()
10429 	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */  in do_t_arit3()
10430   Rn = inst.operands[2].reg;  in do_t_arit3()
10434   if (inst.operands[2].isreg)  in do_t_arit3()
10439       if (!inst.operands[2].isreg)  in do_t_arit3()
10461 	  if (inst.operands[2].shifted)  in do_t_arit3()
10476 	  constraint (inst.operands[2].shifted  in do_t_arit3()
10477 		      && inst.operands[2].immisreg,  in do_t_arit3()
10492       constraint (!inst.operands[2].isreg || inst.operands[2].shifted,  in do_t_arit3()
10514   Rd = inst.operands[0].reg;  in do_t_arit3c()
10515   Rs = (inst.operands[1].present  in do_t_arit3c()
10516 	? inst.operands[1].reg    /* Rd, Rs, foo */  in do_t_arit3c()
10517 	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */  in do_t_arit3c()
10518   Rn = inst.operands[2].reg;  in do_t_arit3c()
10522   if (inst.operands[2].isreg)  in do_t_arit3c()
10527       if (!inst.operands[2].isreg)  in do_t_arit3c()
10549 	  if (inst.operands[2].shifted)  in do_t_arit3c()
10573 	  constraint (inst.operands[2].shifted  in do_t_arit3c()
10574 		      && inst.operands[2].immisreg,  in do_t_arit3c()
10589       constraint (!inst.operands[2].isreg || inst.operands[2].shifted,  in do_t_arit3c()
10609   unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;  in do_t_bfc()
10613   Rd = inst.operands[0].reg;  in do_t_bfc()
10616   inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;  in do_t_bfc()
10617   inst.instruction |= (inst.operands[1].imm & 0x03) << 6;  in do_t_bfc()
10627   Rd = inst.operands[0].reg;  in do_t_bfi()
10632   if (!inst.operands[1].isreg)  in do_t_bfi()
10636       Rn = inst.operands[1].reg;  in do_t_bfi()
10640   msb = inst.operands[2].imm + inst.operands[3].imm;  in do_t_bfi()
10646   inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;  in do_t_bfi()
10647   inst.instruction |= (inst.operands[2].imm & 0x03) << 6;  in do_t_bfi()
10656   Rd = inst.operands[0].reg;  in do_t_bfx()
10657   Rn = inst.operands[1].reg;  in do_t_bfx()
10662   constraint (inst.operands[2].imm + inst.operands[3].imm > 32,  in do_t_bfx()
10666   inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;  in do_t_bfx()
10667   inst.instruction |= (inst.operands[2].imm & 0x03) << 6;  in do_t_bfx()
10668   inst.instruction |= inst.operands[3].imm - 1;  in do_t_bfx()
10686   if (inst.operands[0].isreg)  in do_t_blx()
10688       constraint (inst.operands[0].reg == REG_PC, BAD_PC);  in do_t_blx()
10690       inst.instruction |= inst.operands[0].reg << 3;  in do_t_blx()
10727 	      && (inst.operands[0].hasreloc  in do_t_branch()
10766   if (inst.operands[0].present)  in do_t_bkpt_hlt1()
10768       constraint (inst.operands[0].imm > range,  in do_t_bkpt_hlt1()
10770       inst.instruction |= inst.operands[0].imm;  in do_t_bkpt_hlt1()
10820   inst.instruction |= inst.operands[0].reg << 3;  in do_t_bx()
10832   Rm = inst.operands[0].reg;  in do_t_bxj()
10843   Rd = inst.operands[0].reg;  in do_t_clz()
10844   Rm = inst.operands[1].reg;  in do_t_clz()
10858   inst.instruction |= inst.operands[0].imm;  in do_t_cps()
10866       && (inst.operands[1].present || inst.size_req == 4)  in do_t_cpsi()
10872       inst.instruction |= inst.operands[0].imm << 5;  in do_t_cpsi()
10873       if (inst.operands[1].present)  in do_t_cpsi()
10874 	inst.instruction |= 0x100 | inst.operands[1].imm;  in do_t_cpsi()
10879 		  && (inst.operands[0].imm & 4),  in do_t_cpsi()
10882       constraint (inst.operands[1].present || inst.size_req == 4,  in do_t_cpsi()
10885       inst.instruction |= inst.operands[0].imm;  in do_t_cpsi()
10897       inst.instruction |= inst.operands[0].reg << 8;  in do_t_cpy()
10898       inst.instruction |= inst.operands[1].reg;  in do_t_cpy()
10902       inst.instruction |= (inst.operands[0].reg & 0x8) << 4;  in do_t_cpy()
10903       inst.instruction |= (inst.operands[0].reg & 0x7);  in do_t_cpy()
10904       inst.instruction |= inst.operands[1].reg << 3;  in do_t_cpy()
10912   constraint (inst.operands[0].reg > 7, BAD_HIREG);  in do_t_cbz()
10913   inst.instruction |= inst.operands[0].reg;  in do_t_cbz()
10921   inst.instruction |= inst.operands[0].imm;  in do_t_dbg()
10929   Rd = inst.operands[0].reg;  in do_t_div()
10930   Rn = (inst.operands[1].present  in do_t_div()
10931 	? inst.operands[1].reg : Rd);  in do_t_div()
10932   Rm = inst.operands[2].reg;  in do_t_div()
10955   unsigned int cond = inst.operands[0].imm;  in do_t_it()
11065   constraint (inst.operands[1].writeback,  in do_t_ldmstm()
11077 	  && !(inst.operands[1].imm & ~0xff))  in do_t_ldmstm()
11079 	  mask = 1 << inst.operands[0].reg;  in do_t_ldmstm()
11081 	  if (inst.operands[0].reg <= 7)  in do_t_ldmstm()
11084 		  ? inst.operands[0].writeback  in do_t_ldmstm()
11085 		  : (inst.operands[0].writeback  in do_t_ldmstm()
11086 		     == !(inst.operands[1].imm & mask)))  in do_t_ldmstm()
11089 		      && (inst.operands[1].imm & mask)  in do_t_ldmstm()
11090 		      && (inst.operands[1].imm & (mask - 1)))  in do_t_ldmstm()
11092 			     inst.operands[0].reg);  in do_t_ldmstm()
11095 		  inst.instruction |= inst.operands[0].reg << 8;  in do_t_ldmstm()
11096 		  inst.instruction |= inst.operands[1].imm;  in do_t_ldmstm()
11099 	      else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)  in do_t_ldmstm()
11111 		  if (inst.operands[1].imm & mask  in do_t_ldmstm()
11112 		      && inst.operands[0].writeback)  in do_t_ldmstm()
11120 		  inst.instruction |= inst.operands[0].reg << 3;  in do_t_ldmstm()
11121 		  inst.instruction |= (ffs (inst.operands[1].imm)-1);  in do_t_ldmstm()
11125 	  else if (inst.operands[0] .reg == REG_SP)  in do_t_ldmstm()
11127 	      if (inst.operands[0].writeback)  in do_t_ldmstm()
11132 		  inst.instruction |= inst.operands[1].imm;  in do_t_ldmstm()
11135 	      else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)  in do_t_ldmstm()
11140 		  inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);  in do_t_ldmstm()
11151 	  encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,  in do_t_ldmstm()
11152 				inst.operands[0].writeback);  in do_t_ldmstm()
11157       constraint (inst.operands[0].reg > 7  in do_t_ldmstm()
11158 		  || (inst.operands[1].imm & ~0xff), BAD_HIREG);  in do_t_ldmstm()
11164 	  if (!inst.operands[0].writeback)  in do_t_ldmstm()
11166 	  if ((inst.operands[1].imm & (1 << inst.operands[0].reg))  in do_t_ldmstm()
11167 	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))  in do_t_ldmstm()
11169 		     inst.operands[0].reg);  in do_t_ldmstm()
11173 	  if (!inst.operands[0].writeback  in do_t_ldmstm()
11174 	      && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))  in do_t_ldmstm()
11176 	  else if (inst.operands[0].writeback  in do_t_ldmstm()
11177 		   && (inst.operands[1].imm & (1 << inst.operands[0].reg)))  in do_t_ldmstm()
11182       inst.instruction |= inst.operands[0].reg << 8;  in do_t_ldmstm()
11183       inst.instruction |= inst.operands[1].imm;  in do_t_ldmstm()
11190   constraint (!inst.operands[1].isreg || !inst.operands[1].preind  in do_t_ldrex()
11191 	      || inst.operands[1].postind || inst.operands[1].writeback  in do_t_ldrex()
11192 	      || inst.operands[1].immisreg || inst.operands[1].shifted  in do_t_ldrex()
11193 	      || inst.operands[1].negative,  in do_t_ldrex()
11196   constraint ((inst.operands[1].reg == REG_PC), BAD_PC);  in do_t_ldrex()
11198   inst.instruction |= inst.operands[0].reg << 12;  in do_t_ldrex()
11199   inst.instruction |= inst.operands[1].reg << 16;  in do_t_ldrex()
11206   if (!inst.operands[1].present)  in do_t_ldrexd()
11208       constraint (inst.operands[0].reg == REG_LR,  in do_t_ldrexd()
11211       inst.operands[1].reg = inst.operands[0].reg + 1;  in do_t_ldrexd()
11213   constraint (inst.operands[0].reg == inst.operands[1].reg,  in do_t_ldrexd()
11216   inst.instruction |= inst.operands[0].reg << 12;  in do_t_ldrexd()
11217   inst.instruction |= inst.operands[1].reg << 8;  in do_t_ldrexd()
11218   inst.instruction |= inst.operands[2].reg << 16;  in do_t_ldrexd()
11227   if (inst.operands[0].isreg  in do_t_ldst()
11228       && !inst.operands[0].preind  in do_t_ldst()
11229       && inst.operands[0].reg == REG_PC)  in do_t_ldst()
11235       if (!inst.operands[1].isreg)  in do_t_ldst()
11242       if (inst.operands[1].isreg  in do_t_ldst()
11243 	  && !inst.operands[1].writeback  in do_t_ldst()
11244 	  && !inst.operands[1].shifted && !inst.operands[1].postind  in do_t_ldst()
11245 	  && !inst.operands[1].negative && inst.operands[0].reg <= 7  in do_t_ldst()
11250 	  Rn = inst.operands[1].reg;  in do_t_ldst()
11251 	  if (inst.operands[1].immisreg)  in do_t_ldst()
11255 	      if (Rn <= 7 && inst.operands[1].imm <= 7)  in do_t_ldst()
11258 		reject_bad_reg (inst.operands[1].imm);  in do_t_ldst()
11282 		  inst.instruction = inst.operands[0].reg << 8;  in do_t_ldst()
11286 		  inst.instruction = inst.operands[0].reg;  in do_t_ldst()
11287 		  inst.instruction |= inst.operands[1].reg << 3;  in do_t_ldst()
11301 	  && inst.operands[0].reg == REG_SP  in do_t_ldst()
11302 	  && inst.operands[1].writeback == 1  in do_t_ldst()
11303 	  && !inst.operands[1].immisreg)  in do_t_ldst()
11315       if (inst.operands[1].immisreg)  in do_t_ldst()
11316 	reject_bad_reg (inst.operands[1].imm);  in do_t_ldst()
11318       constraint (inst.operands[1].writeback == 1  in do_t_ldst()
11319 		  && inst.operands[0].reg == inst.operands[1].reg,  in do_t_ldst()
11323       inst.instruction |= inst.operands[0].reg << 12;  in do_t_ldst()
11329   constraint (inst.operands[0].reg > 7, BAD_HIREG);  in do_t_ldst()
11334       constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);  in do_t_ldst()
11335       constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg  in do_t_ldst()
11336 		  || inst.operands[1].postind || inst.operands[1].shifted  in do_t_ldst()
11337 		  || inst.operands[1].negative,  in do_t_ldst()
11344   if (!inst.operands[1].isreg)  in do_t_ldst()
11348   constraint (!inst.operands[1].preind  in do_t_ldst()
11349 	      || inst.operands[1].shifted  in do_t_ldst()
11350 	      || inst.operands[1].writeback,  in do_t_ldst()
11352   if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)  in do_t_ldst()
11356       constraint (inst.operands[1].reg == REG_PC  in do_t_ldst()
11359       constraint (inst.operands[1].immisreg,  in do_t_ldst()
11362       if (inst.operands[1].reg == REG_PC)  in do_t_ldst()
11369       inst.instruction |= inst.operands[0].reg << 8;  in do_t_ldst()
11374   constraint (inst.operands[1].reg > 7, BAD_HIREG);  in do_t_ldst()
11375   if (!inst.operands[1].immisreg)  in do_t_ldst()
11378       inst.instruction |= inst.operands[0].reg;  in do_t_ldst()
11379       inst.instruction |= inst.operands[1].reg << 3;  in do_t_ldst()
11385   constraint (inst.operands[1].imm > 7, BAD_HIREG);  in do_t_ldst()
11386   constraint (inst.operands[1].negative,  in do_t_ldst()
11403   inst.instruction |= inst.operands[0].reg;  in do_t_ldst()
11404   inst.instruction |= inst.operands[1].reg << 3;  in do_t_ldst()
11405   inst.instruction |= inst.operands[1].imm << 6;  in do_t_ldst()
11411   if (!inst.operands[1].present)  in do_t_ldstd()
11413       inst.operands[1].reg = inst.operands[0].reg + 1;  in do_t_ldstd()
11414       constraint (inst.operands[0].reg == REG_LR,  in do_t_ldstd()
11416       constraint (inst.operands[0].reg == REG_R12,  in do_t_ldstd()
11420   if (inst.operands[2].writeback  in do_t_ldstd()
11421       && (inst.operands[0].reg == inst.operands[2].reg  in do_t_ldstd()
11422       || inst.operands[1].reg == inst.operands[2].reg))  in do_t_ldstd()
11426   inst.instruction |= inst.operands[0].reg << 12;  in do_t_ldstd()
11427   inst.instruction |= inst.operands[1].reg << 8;  in do_t_ldstd()
11434   inst.instruction |= inst.operands[0].reg << 12;  in do_t_ldstt()
11443   Rd = inst.operands[0].reg;  in do_t_mla()
11444   Rn = inst.operands[1].reg;  in do_t_mla()
11445   Rm = inst.operands[2].reg;  in do_t_mla()
11446   Ra = inst.operands[3].reg;  in do_t_mla()
11464   RdLo = inst.operands[0].reg;  in do_t_mlal()
11465   RdHi = inst.operands[1].reg;  in do_t_mlal()
11466   Rn = inst.operands[2].reg;  in do_t_mlal()
11467   Rm = inst.operands[3].reg;  in do_t_mlal()
11485   Rn = inst.operands[0].reg;  in do_t_mov_cmp()
11486   Rm = inst.operands[1].reg;  in do_t_mov_cmp()
11506 	  || inst.operands[1].shifted)  in do_t_mov_cmp()
11510       if (opcode == T_MNEM_movs && inst.operands[1].isreg  in do_t_mov_cmp()
11511 	  && !inst.operands[1].shifted  in do_t_mov_cmp()
11538 	  if (inst.operands[1].isreg)  in do_t_mov_cmp()
11568       if (!inst.operands[1].isreg)  in do_t_mov_cmp()
11590       else if (inst.operands[1].shifted && inst.operands[1].immisreg  in do_t_mov_cmp()
11605 	  if (!low_regs || inst.operands[1].imm > 7)  in do_t_mov_cmp()
11611 	  switch (inst.operands[1].shift_kind)  in do_t_mov_cmp()
11633 	      inst.instruction |= inst.operands[1].imm << 3;  in do_t_mov_cmp()
11642 	      inst.instruction |= inst.operands[1].imm;  in do_t_mov_cmp()
11649 	  if (low_regs && inst.operands[1].shifted  in do_t_mov_cmp()
11661 	      switch (inst.operands[1].shift_kind)  in do_t_mov_cmp()
11741   constraint (inst.operands[1].shifted,  in do_t_mov_cmp()
11744   if (inst.operands[1].isreg)  in do_t_mov_cmp()
11795   Rd = inst.operands[0].reg;  in do_t_mov16()
11814   Rn = inst.operands[0].reg;  in do_t_mvn_tst()
11815   Rm = inst.operands[1].reg;  in do_t_mvn_tst()
11832 	  || inst.operands[1].shifted  in do_t_mvn_tst()
11843       if (!inst.operands[1].isreg)  in do_t_mvn_tst()
11864 	      constraint (inst.operands[1].shifted  in do_t_mvn_tst()
11865 			  && inst.operands[1].immisreg,  in do_t_mvn_tst()
11878       constraint (!inst.operands[1].isreg || inst.operands[1].shifted,  in do_t_mvn_tst()
11897   Rd = inst.operands[0].reg;  in do_t_mrs()
11901   if (inst.operands[1].isreg)  in do_t_mrs()
11903       unsigned br = inst.operands[1].reg;  in do_t_mrs()
11913       int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);  in do_t_mrs()
11931       inst.instruction |= inst.operands[1].imm & 0xff;  in do_t_mrs()
11945   constraint (!inst.operands[1].isreg,  in do_t_msr()
11948   if (inst.operands[0].isreg)  in do_t_msr()
11949     flags = (int)(inst.operands[0].reg);  in do_t_msr()
11951     flags = inst.operands[0].imm;  in do_t_msr()
11955       int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);  in do_t_msr()
11972   Rn = inst.operands[1].reg;  in do_t_msr()
11988   if (!inst.operands[2].present)  in do_t_mul()
11989     inst.operands[2].reg = inst.operands[0].reg;  in do_t_mul()
11991   Rd = inst.operands[0].reg;  in do_t_mul()
11992   Rn = inst.operands[1].reg;  in do_t_mul()
11993   Rm = inst.operands[2].reg;  in do_t_mul()
12050   RdLo = inst.operands[0].reg;  in do_t_mull()
12051   RdHi = inst.operands[1].reg;  in do_t_mull()
12052   Rn = inst.operands[2].reg;  in do_t_mull()
12053   Rm = inst.operands[3].reg;  in do_t_mull()
12076       if (inst.size_req == 4 || inst.operands[0].imm > 15)  in do_t_nop()
12079 	  inst.instruction |= inst.operands[0].imm;  in do_t_nop()
12088 	      inst.instruction |= inst.operands[0].imm << 4;  in do_t_nop()
12096       constraint (inst.operands[0].present,  in do_t_nop()
12113       if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)  in do_t_neg()
12121 	  inst.instruction |= inst.operands[0].reg << 8;  in do_t_neg()
12122 	  inst.instruction |= inst.operands[1].reg << 16;  in do_t_neg()
12127 	  inst.instruction |= inst.operands[0].reg;  in do_t_neg()
12128 	  inst.instruction |= inst.operands[1].reg << 3;  in do_t_neg()
12133       constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,  in do_t_neg()
12138       inst.instruction |= inst.operands[0].reg;  in do_t_neg()
12139       inst.instruction |= inst.operands[1].reg << 3;  in do_t_neg()
12148   Rd = inst.operands[0].reg;  in do_t_orn()
12149   Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;  in do_t_orn()
12158   if (!inst.operands[2].isreg)  in do_t_orn()
12167       Rm = inst.operands[2].reg;  in do_t_orn()
12170       constraint (inst.operands[2].shifted  in do_t_orn()
12171 		  && inst.operands[2].immisreg,  in do_t_orn()
12182   Rd = inst.operands[0].reg;  in do_t_pkhbt()
12183   Rn = inst.operands[1].reg;  in do_t_pkhbt()
12184   Rm = inst.operands[2].reg;  in do_t_pkhbt()
12193   if (inst.operands[3].present)  in do_t_pkhbt()
12206   if (!inst.operands[3].present)  in do_t_pkhtb()
12213       Rtmp = inst.operands[1].reg;  in do_t_pkhtb()
12214       inst.operands[1].reg = inst.operands[2].reg;  in do_t_pkhtb()
12215       inst.operands[2].reg = Rtmp;  in do_t_pkhtb()
12223   if (inst.operands[0].immisreg)  in do_t_pld()
12224     reject_bad_reg (inst.operands[0].imm);  in do_t_pld()
12234   constraint (inst.operands[0].writeback,  in do_t_push_pop()
12239   mask = inst.operands[0].imm;  in do_t_push_pop()
12267   Rd = inst.operands[0].reg;  in do_t_rbit()
12268   Rm = inst.operands[1].reg;  in do_t_rbit()
12283   Rd = inst.operands[0].reg;  in do_t_rev()
12284   Rm = inst.operands[1].reg;  in do_t_rev()
12312   Rd = inst.operands[0].reg;  in do_t_rrx()
12313   Rm = inst.operands[1].reg;  in do_t_rrx()
12327   Rd = inst.operands[0].reg;  in do_t_rsb()
12328   Rs = (inst.operands[1].present  in do_t_rsb()
12329 	? inst.operands[1].reg    /* Rd, Rs, foo */  in do_t_rsb()
12330 	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */  in do_t_rsb()
12334   if (inst.operands[2].isreg)  in do_t_rsb()
12335     reject_bad_reg (inst.operands[2].reg);  in do_t_rsb()
12339   if (!inst.operands[2].isreg)  in do_t_rsb()
12385   if (inst.operands[0].imm)  in do_t_setend()
12392   if (!inst.operands[1].present)  in do_t_shift()
12393     inst.operands[1].reg = inst.operands[0].reg;  in do_t_shift()
12417       if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)  in do_t_shift()
12419       if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)  in do_t_shift()
12421       if (inst.operands[2].isreg  in do_t_shift()
12422 	  && (inst.operands[1].reg != inst.operands[0].reg  in do_t_shift()
12423 	      || inst.operands[2].reg > 7))  in do_t_shift()
12428       reject_bad_reg (inst.operands[0].reg);  in do_t_shift()
12429       reject_bad_reg (inst.operands[1].reg);  in do_t_shift()
12433 	  if (inst.operands[2].isreg)  in do_t_shift()
12435 	      reject_bad_reg (inst.operands[2].reg);  in do_t_shift()
12437 	      inst.instruction |= inst.operands[0].reg << 8;  in do_t_shift()
12438 	      inst.instruction |= inst.operands[1].reg << 16;  in do_t_shift()
12439 	      inst.instruction |= inst.operands[2].reg;  in do_t_shift()
12442 	      constraint (inst.operands[2].shifted,  in do_t_shift()
12447 	      inst.operands[1].shifted = 1;  in do_t_shift()
12448 	      inst.operands[1].shift_kind = shift_kind;  in do_t_shift()
12451 	      inst.instruction |= inst.operands[0].reg << 8;  in do_t_shift()
12459 	  if (inst.operands[2].isreg)  in do_t_shift()
12470 	      inst.instruction |= inst.operands[0].reg;  in do_t_shift()
12471 	      inst.instruction |= inst.operands[2].reg << 3;  in do_t_shift()
12474 	      constraint (inst.operands[2].shifted,  in do_t_shift()
12487 	      inst.instruction |= inst.operands[0].reg;  in do_t_shift()
12488 	      inst.instruction |= inst.operands[1].reg << 3;  in do_t_shift()
12494       constraint (inst.operands[0].reg > 7  in do_t_shift()
12495 		  || inst.operands[1].reg > 7, BAD_HIREG);  in do_t_shift()
12498       if (inst.operands[2].isreg)  /* Rd, {Rs,} Rn */  in do_t_shift()
12500 	  constraint (inst.operands[2].reg > 7, BAD_HIREG);  in do_t_shift()
12501 	  constraint (inst.operands[0].reg != inst.operands[1].reg,  in do_t_shift()
12513 	  inst.instruction |= inst.operands[0].reg;  in do_t_shift()
12514 	  inst.instruction |= inst.operands[2].reg << 3;  in do_t_shift()
12517 	  constraint (inst.operands[2].shifted,  in do_t_shift()
12531 	  inst.instruction |= inst.operands[0].reg;  in do_t_shift()
12532 	  inst.instruction |= inst.operands[1].reg << 3;  in do_t_shift()
12542   Rd = inst.operands[0].reg;  in do_t_simd()
12543   Rn = inst.operands[1].reg;  in do_t_simd()
12544   Rm = inst.operands[2].reg;  in do_t_simd()
12560   Rd = inst.operands[0].reg;  in do_t_simd2()
12561   Rm = inst.operands[1].reg;  in do_t_simd2()
12562   Rn = inst.operands[2].reg;  in do_t_simd2()
12604   Rd = inst.operands[0].reg;  in do_t_ssat_usat()
12605   Rn = inst.operands[2].reg;  in do_t_ssat_usat()
12611   inst.instruction |= inst.operands[1].imm - bias;  in do_t_ssat_usat()
12614   if (inst.operands[3].present)  in do_t_ssat_usat()
12628 	  if (inst.operands[3].shift_kind == SHIFT_ASR)  in do_t_ssat_usat()
12648   Rd = inst.operands[0].reg;  in do_t_ssat16()
12649   Rn = inst.operands[2].reg;  in do_t_ssat16()
12655   inst.instruction |= inst.operands[1].imm - 1;  in do_t_ssat16()
12662   constraint (!inst.operands[2].isreg || !inst.operands[2].preind  in do_t_strex()
12663 	      || inst.operands[2].postind || inst.operands[2].writeback  in do_t_strex()
12664 	      || inst.operands[2].immisreg || inst.operands[2].shifted  in do_t_strex()
12665 	      || inst.operands[2].negative,  in do_t_strex()
12668   constraint (inst.operands[2].reg == REG_PC, BAD_PC);  in do_t_strex()
12670   inst.instruction |= inst.operands[0].reg << 8;  in do_t_strex()
12671   inst.instruction |= inst.operands[1].reg << 12;  in do_t_strex()
12672   inst.instruction |= inst.operands[2].reg << 16;  in do_t_strex()
12679   if (!inst.operands[2].present)  in do_t_strexd()
12680     inst.operands[2].reg = inst.operands[1].reg + 1;  in do_t_strexd()
12682   constraint (inst.operands[0].reg == inst.operands[1].reg  in do_t_strexd()
12683 	      || inst.operands[0].reg == inst.operands[2].reg  in do_t_strexd()
12684 	      || inst.operands[0].reg == inst.operands[3].reg,  in do_t_strexd()
12687   inst.instruction |= inst.operands[0].reg;  in do_t_strexd()
12688   inst.instruction |= inst.operands[1].reg << 12;  in do_t_strexd()
12689   inst.instruction |= inst.operands[2].reg << 8;  in do_t_strexd()
12690   inst.instruction |= inst.operands[3].reg << 16;  in do_t_strexd()
12698   Rd = inst.operands[0].reg;  in do_t_sxtah()
12699   Rn = inst.operands[1].reg;  in do_t_sxtah()
12700   Rm = inst.operands[2].reg;  in do_t_sxtah()
12709   inst.instruction |= inst.operands[3].imm << 4;  in do_t_sxtah()
12717   Rd = inst.operands[0].reg;  in do_t_sxth()
12718   Rm = inst.operands[1].reg;  in do_t_sxth()
12726       && (!inst.operands[2].present || inst.operands[2].imm == 0))  in do_t_sxth()
12738       inst.instruction |= inst.operands[2].imm << 4;  in do_t_sxth()
12742       constraint (inst.operands[2].present && inst.operands[2].imm != 0,  in do_t_sxth()
12773   constraint (inst.operands[0].immisreg,  in do_t_tb()
12776   Rn = inst.operands[0].reg;  in do_t_tb()
12777   Rm = inst.operands[0].imm;  in do_t_tb()
12782   constraint (!half && inst.operands[0].shifted,  in do_t_tb()
12790   if (!inst.operands[0].present)  in do_t_udf()
12791     inst.operands[0].imm = 0;  in do_t_udf()
12793   if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)  in do_t_udf()
12798       inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;  in do_t_udf()
12799       inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;  in do_t_udf()
12804       inst.instruction |= inst.operands[0].imm;  in do_t_udf()
12822   Rd = inst.operands[0].reg;  in do_t_usat16()
12823   Rn = inst.operands[2].reg;  in do_t_usat16()
12829   inst.instruction |= inst.operands[1].imm;  in do_t_usat16()
13185   if (!inst.operands[1].present)  in neon_select_shape()
13186     inst.operands[1] = inst.operands[0];  in neon_select_shape()
13197 	  if (!inst.operands[j].present)  in neon_select_shape()
13206 	      if (!(inst.operands[j].isreg  in neon_select_shape()
13207 		    && inst.operands[j].isvec  in neon_select_shape()
13208 		    && inst.operands[j].issingle  in neon_select_shape()
13209 		    && !inst.operands[j].isquad))  in neon_select_shape()
13214 	      if (!(inst.operands[j].isreg  in neon_select_shape()
13215 		    && inst.operands[j].isvec  in neon_select_shape()
13216 		    && !inst.operands[j].isquad  in neon_select_shape()
13217 		    && !inst.operands[j].issingle))  in neon_select_shape()
13222 	      if (!(inst.operands[j].isreg  in neon_select_shape()
13223 		    && !inst.operands[j].isvec))  in neon_select_shape()
13228 	      if (!(inst.operands[j].isreg  in neon_select_shape()
13229 		    && inst.operands[j].isvec  in neon_select_shape()
13230 		    && inst.operands[j].isquad  in neon_select_shape()
13231 		    && !inst.operands[j].issingle))  in neon_select_shape()
13236 	      if (!(!inst.operands[j].isreg  in neon_select_shape()
13237 		    && !inst.operands[j].isscalar))  in neon_select_shape()
13242 	      if (!(!inst.operands[j].isreg  in neon_select_shape()
13243 		    && inst.operands[j].isscalar))  in neon_select_shape()
13253       if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))  in neon_select_shape()
13484   if (els > 1 && !inst.operands[1].present)  in neon_check_type()
13485     inst.operands[1] = inst.operands[0];  in neon_check_type()
13505       if (inst.operands[i].vectype.type != NT_invtype)  in neon_check_type()
13532 	if (inst.operands[j].vectype.type != NT_invtype)  in neon_check_type()
13533 	  inst.vectype.el[j] = inst.operands[j].vectype;  in neon_check_type()
13535       if (inst.operands[key_el].vectype.type != NT_invtype)  in neon_check_type()
13538 	    if (inst.operands[j].vectype.type == NT_invtype)  in neon_check_type()
13901   if (inst.operands[1].isreg)  in do_vfp_nsyn_cmp()
13951   inst.operands[1] = inst.operands[0];  in nsyn_insert_sp()
13952   memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));  in nsyn_insert_sp()
13953   inst.operands[0].reg = REG_SP;  in nsyn_insert_sp()
13954   inst.operands[0].isreg = 1;  in nsyn_insert_sp()
13955   inst.operands[0].writeback = 1;  in nsyn_insert_sp()
13956   inst.operands[0].present = 1;  in nsyn_insert_sp()
13963   if (inst.operands[1].issingle)  in do_vfp_nsyn_push()
13973   if (inst.operands[1].issingle)  in do_vfp_nsyn_pop()
14027   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_three_same()
14028   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_three_same()
14029   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;  in neon_three_same()
14030   inst.instruction |= HI1 (inst.operands[1].reg) << 7;  in neon_three_same()
14031   inst.instruction |= LOW4 (inst.operands[2].reg);  in neon_three_same()
14032   inst.instruction |= HI1 (inst.operands[2].reg) << 5;  in neon_three_same()
14051   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_two_same()
14052   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_two_same()
14053   inst.instruction |= LOW4 (inst.operands[1].reg);  in neon_two_same()
14054   inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in neon_two_same()
14089   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_imm_shift()
14090   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_imm_shift()
14091   inst.instruction |= LOW4 (inst.operands[1].reg);  in neon_imm_shift()
14092   inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in neon_imm_shift()
14106   if (!inst.operands[2].isreg)  in do_neon_shl_imm()
14111       neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);  in do_neon_shl_imm()
14127       tmp = inst.operands[2].reg;  in do_neon_shl_imm()
14128       inst.operands[2].reg = inst.operands[1].reg;  in do_neon_shl_imm()
14129       inst.operands[1].reg = tmp;  in do_neon_shl_imm()
14138   if (!inst.operands[2].isreg)  in do_neon_qshl_imm()
14145 		      inst.operands[2].imm);  in do_neon_qshl_imm()
14155       tmp = inst.operands[2].reg;  in do_neon_qshl_imm()
14156       inst.operands[2].reg = inst.operands[1].reg;  in do_neon_qshl_imm()
14157       inst.operands[1].reg = tmp;  in do_neon_qshl_imm()
14171   tmp = inst.operands[2].reg;  in do_neon_rshl()
14172   inst.operands[2].reg = inst.operands[1].reg;  in do_neon_rshl()
14173   inst.operands[1].reg = tmp;  in do_neon_rshl()
14236   if (inst.operands[2].present && inst.operands[2].isreg)  in do_neon_logic()
14246       const int three_ops_form = (inst.operands[2].present  in do_neon_logic()
14247 				  && !inst.operands[2].isreg);  in do_neon_logic()
14262 	constraint (inst.operands[0].reg != inst.operands[1].reg,  in do_neon_logic()
14267       immbits = inst.operands[immoperand].imm;  in do_neon_logic()
14272 	  if (immbits != (inst.operands[immoperand].regisimm ?  in do_neon_logic()
14273 			  inst.operands[immoperand].reg : 0))  in do_neon_logic()
14310       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_logic()
14311       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_logic()
14452   void *scratch = alloca (sizeof (inst.operands[0]));  in neon_exchange_operands()
14453   if (inst.operands[1].present)  in neon_exchange_operands()
14456       memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));  in neon_exchange_operands()
14457       inst.operands[1] = inst.operands[2];  in neon_exchange_operands()
14458       memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));  in neon_exchange_operands()
14462       inst.operands[1] = inst.operands[2];  in neon_exchange_operands()
14463       inst.operands[2] = inst.operands[0];  in neon_exchange_operands()
14470   if (inst.operands[2].isreg)  in neon_compare()
14483       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_compare()
14484       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_compare()
14485       inst.instruction |= LOW4 (inst.operands[1].reg);  in neon_compare()
14486       inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in neon_compare()
14556   scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);  in neon_mul_mac()
14557   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_mul_mac()
14558   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_mul_mac()
14559   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;  in neon_mul_mac()
14560   inst.instruction |= HI1 (inst.operands[1].reg) << 7;  in neon_mul_mac()
14579   if (inst.operands[2].isscalar)  in do_neon_mac_maybe_scalar()
14629   if (inst.operands[2].isscalar)  in do_neon_mul()
14638   if (inst.operands[2].isscalar)  in do_neon_qdmulh()
14696   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_abs_neg()
14697   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_abs_neg()
14698   inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_abs_neg()
14699   inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_abs_neg()
14713   int imm = inst.operands[2].imm;  in do_neon_sli()
14725   int imm = inst.operands[2].imm;  in do_neon_sri()
14737   int imm = inst.operands[2].imm;  in do_neon_qshlu_imm()
14780   int imm = inst.operands[2].imm;  in do_neon_rshift_sat_narrow()
14789       inst.operands[2].present = 0;  in do_neon_rshift_sat_narrow()
14807   int imm = inst.operands[2].imm;  in do_neon_rshift_sat_narrow_u()
14816       inst.operands[2].present = 0;  in do_neon_rshift_sat_narrow_u()
14844   int imm = inst.operands[2].imm;  in do_neon_rshift_narrow()
14853       inst.operands[2].present = 0;  in do_neon_rshift_narrow()
14870   unsigned imm = inst.operands[2].imm;  in do_neon_shll()
14876       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_shll()
14877       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_shll()
14878       inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_shll()
14879       inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_shll()
14993 	  constraint (inst.operands[0].reg != inst.operands[1].reg,  in do_vfp_nsyn_cvt()
14995 	  inst.operands[1] = inst.operands[2];  in do_vfp_nsyn_cvt()
14996 	  memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));  in do_vfp_nsyn_cvt()
15077   encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);  in do_vfp_nsyn_cvt_fpv8()
15078   encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);  in do_vfp_nsyn_cvt_fpv8()
15130 	if (inst.operands[2].present && inst.operands[2].imm == 0)  in do_neon_cvt_1()
15132        immbits = 32 - inst.operands[2].imm;  in do_neon_cvt_1()
15136 	inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_cvt_1()
15137 	inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_cvt_1()
15138 	inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_cvt_1()
15139 	inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_cvt_1()
15158 	  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_cvt_1()
15159 	  inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_cvt_1()
15160 	  inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_cvt_1()
15161 	  inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_cvt_1()
15184 	    inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_cvt_1()
15185 	    inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_cvt_1()
15186 	    inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_cvt_1()
15187 	    inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_cvt_1()
15219       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_cvt_1()
15220       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_cvt_1()
15221       inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_cvt_1()
15222       inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_cvt_1()
15277   encode_arm_vfp_reg (inst.operands[0].reg,  in do_neon_cvttb_2()
15279   encode_arm_vfp_reg (inst.operands[1].reg,  in do_neon_cvttb_2()
15346   immlo = inst.operands[1].imm;  in neon_move_immediate()
15347   if (inst.operands[1].regisimm)  in neon_move_immediate()
15348     immhi = inst.operands[1].reg;  in neon_move_immediate()
15353   float_p = inst.operands[1].immisfloat;  in neon_move_immediate()
15375   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_move_immediate()
15376   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_move_immediate()
15386   if (inst.operands[1].isreg)  in do_neon_mvn()
15391       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_mvn()
15392       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_mvn()
15393       inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_mvn()
15394       inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_mvn()
15414   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in neon_mixed_length()
15415   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in neon_mixed_length()
15416   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;  in neon_mixed_length()
15417   inst.instruction |= HI1 (inst.operands[1].reg) << 7;  in neon_mixed_length()
15418   inst.instruction |= LOW4 (inst.operands[2].reg);  in neon_mixed_length()
15419   inst.instruction |= HI1 (inst.operands[2].reg) << 5;  in neon_mixed_length()
15446   if (inst.operands[2].isscalar)  in neon_mac_reg_scalar_long()
15496   if (inst.operands[2].isscalar)  in do_neon_vmull()
15531   unsigned imm = (inst.operands[3].imm * et.size) / 8;  in do_neon_ext()
15535   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_ext()
15536   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_ext()
15537   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;  in do_neon_ext()
15538   inst.instruction |= HI1 (inst.operands[1].reg) << 7;  in do_neon_ext()
15539   inst.instruction |= LOW4 (inst.operands[2].reg);  in do_neon_ext()
15540   inst.instruction |= HI1 (inst.operands[2].reg) << 5;  in do_neon_ext()
15567   if (inst.operands[1].isscalar)  in do_neon_dup()
15573       unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);  in do_neon_dup()
15575       unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;  in do_neon_dup()
15581       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_dup()
15582       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_dup()
15605       inst.instruction |= LOW4 (inst.operands[1].reg) << 12;  in do_neon_dup()
15606       inst.instruction |= LOW4 (inst.operands[0].reg) << 16;  in do_neon_dup()
15607       inst.instruction |= HI1 (inst.operands[0].reg) << 7;  in do_neon_dup()
15686 	inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_mov()
15687 	inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_mov()
15688 	inst.instruction |= LOW4 (inst.operands[1].reg);  in do_neon_mov()
15689 	inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_neon_mov()
15690 	inst.instruction |= LOW4 (inst.operands[1].reg) << 16;  in do_neon_mov()
15691 	inst.instruction |= HI1 (inst.operands[1].reg) << 7;  in do_neon_mov()
15721 	unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);  in do_neon_mov()
15722 	unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);  in do_neon_mov()
15726 	    && inst.operands[0].vectype.type == NT_invtype  in do_neon_mov()
15727 	    && inst.operands[1].vectype.type == NT_invtype)  in do_neon_mov()
15758 	inst.instruction |= inst.operands[1].reg << 12;  in do_neon_mov()
15770       inst.instruction |= LOW4 (inst.operands[0].reg);  in do_neon_mov()
15771       inst.instruction |= HI1 (inst.operands[0].reg) << 5;  in do_neon_mov()
15772       inst.instruction |= inst.operands[1].reg << 12;  in do_neon_mov()
15773       inst.instruction |= inst.operands[2].reg << 16;  in do_neon_mov()
15779 	unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);  in do_neon_mov()
15780 	unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);  in do_neon_mov()
15785 	    && inst.operands[0].vectype.type == NT_invtype  in do_neon_mov()
15786 	    && inst.operands[1].vectype.type == NT_invtype)  in do_neon_mov()
15817 	inst.instruction |= inst.operands[0].reg << 12;  in do_neon_mov()
15829       inst.instruction |= inst.operands[0].reg << 12;  in do_neon_mov()
15830       inst.instruction |= inst.operands[1].reg << 16;  in do_neon_mov()
15831       inst.instruction |= LOW4 (inst.operands[2].reg);  in do_neon_mov()
15832       inst.instruction |= HI1 (inst.operands[2].reg) << 5;  in do_neon_mov()
15842       if (is_quarter_float (inst.operands[1].imm))  in do_neon_mov()
15844 	  inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);  in do_neon_mov()
15864       constraint (inst.operands[3].reg != inst.operands[2].reg + 1,  in do_neon_mov()
15866       inst.operands[2].imm = 2;  in do_neon_mov()
15867       memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));  in do_neon_mov()
15872       constraint (inst.operands[1].reg != inst.operands[0].reg + 1,  in do_neon_mov()
15874       inst.operands[1] = inst.operands[2];  in do_neon_mov()
15875       inst.operands[2] = inst.operands[3];  in do_neon_mov()
15876       inst.operands[0].imm = 2;  in do_neon_mov()
15877       memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));  in do_neon_mov()
15896   int imm = inst.operands[2].imm;  in do_neon_rshift_round_imm()
15901       inst.operands[2].present = 0;  in do_neon_rshift_round_imm()
16017   if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)  in do_neon_tbl_tbx()
16023   listlenbits = inst.operands[1].imm - 1;  in do_neon_tbl_tbx()
16024   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_tbl_tbx()
16025   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_tbl_tbx()
16026   inst.instruction |= LOW4 (inst.operands[1].reg) << 16;  in do_neon_tbl_tbx()
16027   inst.instruction |= HI1 (inst.operands[1].reg) << 7;  in do_neon_tbl_tbx()
16028   inst.instruction |= LOW4 (inst.operands[2].reg);  in do_neon_tbl_tbx()
16029   inst.instruction |= HI1 (inst.operands[2].reg) << 5;  in do_neon_tbl_tbx()
16040   unsigned offsetbits = inst.operands[1].imm * 2;  in do_neon_ldm_stm()
16042   if (inst.operands[1].issingle)  in do_neon_ldm_stm()
16048   constraint (is_dbmode && !inst.operands[0].writeback,  in do_neon_ldm_stm()
16051   constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,  in do_neon_ldm_stm()
16055   inst.instruction |= inst.operands[0].reg << 16;  in do_neon_ldm_stm()
16056   inst.instruction |= inst.operands[0].writeback << 21;  in do_neon_ldm_stm()
16057   inst.instruction |= LOW4 (inst.operands[1].reg) << 12;  in do_neon_ldm_stm()
16058   inst.instruction |= HI1 (inst.operands[1].reg) << 22;  in do_neon_ldm_stm()
16073       && inst.operands[1].reg == REG_PC  in do_neon_ldr_str()
16082   if (inst.operands[0].issingle)  in do_neon_ldr_str()
16125   if (inst.operands[1].immisalign)  in do_neon_ld_st_interleave()
16126     switch (inst.operands[1].imm >> 8)  in do_neon_ld_st_interleave()
16130 	if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2  in do_neon_ld_st_interleave()
16131 	    && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)  in do_neon_ld_st_interleave()
16136 	if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)  in do_neon_ld_st_interleave()
16154   idx = ((inst.operands[0].imm >> 4) & 7)  in do_neon_ld_st_interleave()
16178   if (!inst.operands[1].immisalign)  in neon_alignment_bit()
16214   int align = inst.operands[1].imm >> 8;  in do_neon_ld_st_lane()
16221   constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,  in do_neon_ld_st_lane()
16223   constraint (NEON_LANE (inst.operands[0].imm) >= max_el,  in do_neon_ld_st_lane()
16225   constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2  in do_neon_ld_st_lane()
16259       constraint (inst.operands[1].immisalign,  in do_neon_ld_st_lane()
16286   if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)  in do_neon_ld_st_lane()
16289   inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);  in do_neon_ld_st_lane()
16307       gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);  in do_neon_ld_dup()
16308       align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,  in do_neon_ld_dup()
16312       switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))  in do_neon_ld_dup()
16322       align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,  in do_neon_ld_dup()
16326       constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,  in do_neon_ld_dup()
16328       if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)  in do_neon_ld_dup()
16334       constraint (inst.operands[1].immisalign,  in do_neon_ld_dup()
16336       constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,  in do_neon_ld_dup()
16338       if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)  in do_neon_ld_dup()
16345 	int align = inst.operands[1].imm >> 8;  in do_neon_ld_dup()
16350 	constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,  in do_neon_ld_dup()
16352 	if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)  in do_neon_ld_dup()
16373   if (inst.operands[1].isreg)  in do_neon_ldx_stx()
16374     constraint (inst.operands[1].reg == REG_PC, BAD_PC);  in do_neon_ldx_stx()
16376   switch (NEON_LANE (inst.operands[0].imm))  in do_neon_ldx_stx()
16399   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_neon_ldx_stx()
16400   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_neon_ldx_stx()
16401   inst.instruction |= inst.operands[1].reg << 16;  in do_neon_ldx_stx()
16403   if (inst.operands[1].postind)  in do_neon_ldx_stx()
16405       int postreg = inst.operands[1].imm & 0xf;  in do_neon_ldx_stx()
16406       constraint (!inst.operands[1].immisreg,  in do_neon_ldx_stx()
16414       constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);  in do_neon_ldx_stx()
16419       if (inst.operands[1].writeback)  in do_neon_ldx_stx()
16526       inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_vrint_1()
16527       inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_vrint_1()
16528       inst.instruction |= LOW4 (inst.operands[1].reg);  in do_vrint_1()
16529       inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_vrint_1()
16605   inst.instruction |= LOW4 (inst.operands[0].reg) << 12;  in do_crypto_2op_1()
16606   inst.instruction |= HI1 (inst.operands[0].reg) << 22;  in do_crypto_2op_1()
16607   inst.instruction |= LOW4 (inst.operands[1].reg);  in do_crypto_2op_1()
16608   inst.instruction |= HI1 (inst.operands[1].reg) << 5;  in do_crypto_2op_1()
16720   unsigned int Rd = inst.operands[0].reg;  in do_crc32_1()
16721   unsigned int Rn = inst.operands[1].reg;  in do_crc32_1()
16722   unsigned int Rm = inst.operands[2].reg;  in do_crc32_1()
17651       if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))  in md_assemble()
17724       if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))  in md_assemble()