Lines Matching refs:code

20 The i386 version @code{@value{AS}} supports both the original Intel 386
52 The i386 version of @code{@value{AS}} has a few machine
76 alignment within code sections with multi-byte nop instructions such
94 @code{i8086},
95 @code{i186},
96 @code{i286},
97 @code{i386},
98 @code{i486},
99 @code{i586},
100 @code{i686},
101 @code{pentium},
102 @code{pentiumpro},
103 @code{pentiumii},
104 @code{pentiumiii},
105 @code{pentium4},
106 @code{prescott},
107 @code{nocona},
108 @code{core},
109 @code{core2},
110 @code{corei7},
111 @code{l1om},
112 @code{k1om},
113 @code{k6},
114 @code{k6_2},
115 @code{athlon},
116 @code{opteron},
117 @code{k8},
118 @code{amdfam10},
119 @code{bdver1},
120 @code{bdver2},
121 @code{bdver3},
122 @code{bdver4},
123 @code{btver1},
124 @code{btver2},
125 @code{generic32} and
126 @code{generic64}.
130 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
132 @code{8087},
133 @code{287},
134 @code{387},
135 @code{no87},
136 @code{mmx},
137 @code{nommx},
138 @code{sse},
139 @code{sse2},
140 @code{sse3},
141 @code{ssse3},
142 @code{sse4.1},
143 @code{sse4.2},
144 @code{sse4},
145 @code{nosse},
146 @code{avx},
147 @code{avx2},
148 @code{adx},
149 @code{rdseed},
150 @code{prfchw},
151 @code{smap},
152 @code{mpx},
153 @code{sha},
154 @code{prefetchwt1},
155 @code{clflushopt},
156 @code{se1},
157 @code{clwb},
158 @code{pcommit},
159 @code{avx512f},
160 @code{avx512cd},
161 @code{avx512er},
162 @code{avx512pf},
163 @code{avx512vl},
164 @code{avx512bw},
165 @code{avx512dq},
166 @code{avx512ifma},
167 @code{avx512vbmi},
168 @code{noavx},
169 @code{vmx},
170 @code{vmfunc},
171 @code{smx},
172 @code{xsave},
173 @code{xsaveopt},
174 @code{xsavec},
175 @code{xsaves},
176 @code{aes},
177 @code{pclmul},
178 @code{fsgsbase},
179 @code{rdrnd},
180 @code{f16c},
181 @code{bmi2},
182 @code{fma},
183 @code{movbe},
184 @code{ept},
185 @code{lzcnt},
186 @code{hle},
187 @code{rtm},
188 @code{invpcid},
189 @code{clflush},
190 @code{lwp},
191 @code{fma4},
192 @code{xop},
193 @code{cx16},
194 @code{syscall},
195 @code{rdtscp},
196 @code{3dnow},
197 @code{3dnowa},
198 @code{sse4a},
199 @code{sse5},
200 @code{svme},
201 @code{abm} and
202 @code{padlock}.
204 mnemonics starting with @code{no} revoke the respective functionality.
206 When the @code{.arch} directive is used with @option{-march}, the
207 @code{.arch} directive will take precedent.
275 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
283 The @code{.att_syntax} and @code{.intel_syntax} directives will
290 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
296 if such prefix was not explicitly specified in the source code.
336 @table @code
338 @cindex @code{lcomm} directive, COFF
345 @code{@value{LD}}.  The optional third parameter, @var{alignment},
378 @code{@value{AS}} now supports assembly using Intel assembler syntax.
379 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
381 @code{@value{GCC}}.  Either of these directives may have an optional
382 argument, @code{prefix}, or @code{noprefix} specifying whether registers
439 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
498 no suffix is specified by an instruction then @code{@value{AS}} tries to
561 @samp{cqto} in AT&T naming.  @code{@value{AS}} accepts either naming for these
577 @code{@value{AS}} supports assembly using Intel mnemonic.
578 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
579 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
580 syntax for compatibility with the output of @code{@value{GCC}}.
585 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
614 the 6 section registers @samp{%cs} (code section), @samp{%ds}
693 instruction, but this circumvents checks that @code{@value{AS}} does
710 @code{.code16} section) into 32-bit operands/addresses.  These prefixes
711 @emph{must} appear on the same line of code as the instruction they
712 modify. For example, in a 16-bit @code{.code16} section, you might
741 bits --- an operand size overwrite (@code{64}) used to change operand size
747 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
783 coincides with the default section register, @code{@value{AS}} does @emph{not}
812 prefixed with @samp{*}.  If no @samp{*} is specified, @code{@value{AS}}
830 Points to the @code{symbol} in RIP relative way, this is shorter than
855 displacements, so that if you use these instructions (@code{@value{GCC}} does
856 not use them) you may get an error message (and incorrect code).  The AT&T
882 @cindex @code{float} directive, i386
883 @cindex @code{single} directive, i386
884 @cindex @code{double} directive, i386
885 @cindex @code{tfloat} directive, i386
886 @cindex @code{float} directive, x86-64
887 @cindex @code{single} directive, x86-64
888 @cindex @code{double} directive, x86-64
889 @cindex @code{tfloat} directive, x86-64
899 @cindex @code{word} directive, i386
900 @cindex @code{long} directive, i386
901 @cindex @code{int} directive, i386
902 @cindex @code{quad} directive, i386
903 @cindex @code{word} directive, x86-64
904 @cindex @code{long} directive, x86-64
905 @cindex @code{int} directive, x86-64
906 @cindex @code{quad} directive, x86-64
934 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
941 Currently, @code{@value{AS}} does not support Intel's floating point
959 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
978 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
992 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1005 @cindex i386 16-bit code
1006 @cindex 16-bit code, i386
1007 @cindex real-mode code, i386
1008 @cindex @code{code16gcc} directive, i386
1009 @cindex @code{code16} directive, i386
1010 @cindex @code{code32} directive, i386
1011 @cindex @code{code64} directive, i386
1012 @cindex @code{code64} directive, x86-64
1013 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1014 or 64-bit x86-64 code depending on the default configuration,
1015 it also supports writing code to run in real mode or in 16-bit protected
1016 mode code segments.  To do this, put a @samp{.code16} or
1018 be run in 16-bit mode.  You can switch @code{@value{AS}} to writing
1019 32-bit code with the @samp{.code32} directive or 64-bit code with the
1023 code from gcc, and differs from @samp{.code16} in that @samp{call},
1032 The code which @code{@value{AS}} generates in 16-bit mode will not
1033 necessarily run on a 16-bit pre-80386 processor.  To write code that
1035 constructs which require @code{@value{AS}} to output address or operand
1038 Note that writing 16-bit code instructions by explicitly specifying a
1039 prefix or an instruction mnemonic suffix within a 32-bit code section
1041 16-bit code segment.  In a 32-bit code section, the following code
1049 The same code in a 16-bit code section would generate the machine
1052 bits in a 16-bit code section.
1083 @code{@value{AS}} may be told to assemble for a particular CPU
1084 (sub-)architecture with the @code{.arch @var{cpu_type}} directive.  This
1118 @code{@value{AS}} operation;  Firstly, if you specify a CPU other than
1137 @code{@value{AS}} promotes.
1149 @cindex i386 @code{mul}, @code{imul} instructions
1150 @cindex @code{mul} instruction, i386
1151 @cindex @code{imul} instruction, i386
1152 @cindex @code{mul} instruction, x86-64
1153 @cindex @code{imul} instruction, x86-64
1160 would confuse @code{@value{GCC}} output.  Use @samp{imul %ebx} to get the