Lines Matching refs:instructions
29 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
35 generation of MIPS ASE instructions
119 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
164 provides a number of new instructions which target smartcard and
172 This tells the assembler to accept MIPS-3D instructions.
178 This tells the assembler to accept MDMX instructions.
184 This tells the assembler to accept DSP Release 1 instructions.
191 This tells the assembler to accept DSP Release 2 instructions.
197 This tells the assembler to accept MT instructions.
203 This tells the assembler to accept MCU instructions.
209 This tells the assembler to accept MSA instructions.
215 This tells the assembler to accept XPA instructions.
221 This tells the assembler to accept MXU instructions.
227 This tells the assembler to accept Virtualization instructions.
234 instructions. This is equivalent to putting @code{.set insn32} at
238 selected, allowing all instructions to be used.
243 of an mfhi or mflo instruction occurs in the following two instructions.
253 Loongson2F @samp{jump} instructions. Without it, under extreme cases,
286 accept the R4010-specific instructions (@samp{addciu}, @samp{ffc},
287 etc.), and to not schedule @samp{nop} instructions around accesses to
295 instructions around accesses to the @samp{HI} and @samp{LO} registers.
303 R@var{nnnn} chip. This tells the assembler to accept instructions
424 Disable or enable floating-point instructions. Note that by default
425 floating-point instructions are always allowed even with CPU targets
426 that don't have support for these instructions.
454 target is inserted between the two instructions. In PIC code the jump
455 will involve further instructions for address calculation.
458 @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from
482 @c (2) stop teasing, say _which_ instructions expanded _how_.
484 multiplication instructions to check for overflow and division by zero. This
486 rather than a break exception when an error is detected. The trap instructions
514 instructions than the MIPS architecture itself. These extra
515 instructions are usually referred to as ``macro'' instructions
520 Some MIPS macro instructions extend an underlying architectural instruction
544 to several machine instructions. The directive @code{.set nomacro}
550 Some macro instructions need a temporary register to store intermediate
632 It often takes several instructions to load the address of a symbol.
690 The values other than 0 make the assembler accept instructions
692 assembly. @code{.set mips@var{n}} affects not only which instructions
697 instructions while assembling in 32 bit mode. Use this directive with
704 instructions specific to a particular CPU. All CPUs supported by the
709 in which it will assemble instructions for the MIPS 16 processor. Use
715 in which it will assemble instructions for the microMIPS processor. Use
742 This directive inhibits the use of any 16-bit instructions from that
744 16-bit instructions to be accepted.
749 @section Directives for extending MIPS 16 bit instructions
753 By default, MIPS 16 instructions are automatically extended to 32 bits
758 to once again automatically extend instructions when necessary.
768 data is actually instructions. This makes a difference in MIPS 16 and
770 instructions, @code{@value{AS}} automatically adds 1 to the value, so
777 instructions following such a symbol will not be disassembled by
968 @section Directives to control generation of MIPS ASE instructions
973 The directive @code{.set mips3d} makes the assembler accept instructions
976 instructions from being accepted.
982 instructions from the SmartMIPS Application Specific Extension to the
984 @code{.set nosmartmips} directive prevents SmartMIPS instructions from
990 The directive @code{.set mdmx} makes the assembler accept instructions
993 instructions from being accepted.
998 The directive @code{.set dsp} makes the assembler accept instructions
1001 Release 1 instructions from being accepted.
1006 The directive @code{.set dspr2} makes the assembler accept instructions
1009 @code{.set nodspr2} directive prevents DSP Release 2 instructions from
1015 The directive @code{.set mt} makes the assembler accept instructions
1018 instructions from being accepted.
1023 The directive @code{.set mcu} makes the assembler accept instructions
1026 instructions from being accepted.
1031 The directive @code{.set msa} makes the assembler accept instructions
1034 instructions from being accepted.
1039 The directive @code{.set virt} makes the assembler accept instructions
1042 instructions from being accepted.
1047 The directive @code{.set xpa} makes the assembler accept instructions
1049 @code{.set noxpa} directive prevents XPA instructions from being accepted.
1054 The directive @code{.set mxu} makes the assembler accept instructions
1056 @code{.set nomxu} directive prevents MXU instructions from being accepted.
1063 @cindex Disable floating-point instructions
1067 finer control of disabling and enabling float-point instructions.
1069 instructions are accepted) or the command-line options