Lines Matching refs:h
3 * nios2.h (nios2_find_opcode_hash): Add mach parameter to
8 * nios2.h (enum iw_format_type): New.
48 Include nios2r1.h to define new instruction opcode constants
54 * nios2r1.h: New file.
58 * sparc.h (HWCAP2_VIS3B): Documentation improved.
62 * sparc.h (sparc_opcode): new field `hwcaps2'.
82 * nds32.h: Add new opcode declaration.
87 * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
106 * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
114 * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
119 * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
129 * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
138 * msp430.h (struct msp430_operand_s): Add vshift field.
142 * mips.h (INSN_ISA_MASK): Updated.
166 * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
170 * or32.h: Delete.
178 * mips.h: Updated description of +o, +u, +v and +w for MIPS and
184 * nds32.h: New file for Andes NDS32.
188 * bfin.h: Remove +x file mode.
192 * aarch64.h (aarch64_pstatefields): Change element type to
197 * arm.h (ARM_AEXT_V7VE): New define.
207 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
212 * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
217 * aarch64.h (aarch64_sys_reg): New typedef.
223 * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
228 * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
230 For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
235 For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
242 * i960.h: Fix typos.
246 * mips.h: Remove references to "+I" and imm2_expr.
250 * mips.h (M_DEXT, M_DINS): Delete.
254 * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
260 * mips.h: Document new VU0 operand characters.
269 * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
275 * mips.h (mips_decode_reg_operand): New function.
301 * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
309 * i386.h (BND_PREFIX_OPCODE): New.
313 * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
319 * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
329 * mips.h: Document MIPS16 "I" opcode.
333 * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
352 * mips.h: Remove documentation of "[" and "]". Update documentation
357 * mips.h: Update documentation of "+s" and "+S".
361 * mips.h: Document "+i".
365 * mips.h: Remove "mi" documentation. Update "mh" documentation.
373 * mips.h: Remove documentation of "+D" and "+T".
377 * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
382 * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
387 * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
393 * mips.h (OP_SH_EVAOFFSET): Define.
418 * nios2.h (OP_MATCH_ERET): Correct eret encoding.
422 * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
426 * mips.h (OP_MASK_CODE10): Correct definition.
435 * msp430.h: Add patterns for MSP430X instructions.
439 * sparc.h (F_PREFERRED): Define.
444 * v850.h (V850_INVERSE_PCREL): Define.
449 * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
454 * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
456 * tic6xc-opcode-table.h: Add 16-bit insns.
457 * tic6x.h: Add support for 16-bit insns.
461 * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
467 * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
477 * tic6x.h (enum tic6x_coding_method): Add
481 * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
486 * arm.h (CRC_EXT_ARMV8): New constant.
491 * aarch64.h (AARCH64_FEATURE_CRC): New macro.
498 * nios2.h: New file.
502 * aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
507 * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
511 * v850.h: Add e3v5 support.
515 * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
519 * ppc.h (PPC_OPCODE_POWER8): New define.
524 * metag.h: New file.
528 * cr16.h (make_instruction): Rename to cr16_make_instruction.
533 * mips.h: Add support for r5900 instructions including lq and sq.
537 * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
543 * ppc.h (ppc_parse_cpu): Update prototype.
547 * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
552 * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
556 * ia64.h (ia64_opnd): Add new operand types.
560 * sparc.h (F3F4): New macro.
573 * aarch64.h: New file.
578 * mips.h (mips_opcode): Add the exclusions field.
587 * mips.h: Document microMIPS DSP ASE usage.
600 * mips.h: Fix a typo in description.
604 * avr.h: (AVR_ISA_XCH): New define.
610 * m68hc11.h: Add XGate definitions.
617 * ppc.h (PPC_OPCODE_VLE): New definition.
630 * xgate.h: Header file for XGATE assembler.
634 * sparc.h: Document new arg code' )' for crypto RS3
637 * sparc.h (struct sparc_opcode): New field 'hwcaps'.
651 * ppc.h: Add PPC_OPCODE_ALTIVEC2, PPC_OPCODE_E6500, PPC_OPCODE_TMR.
655 * crx.h (cst4_map): Update declaration.
659 * tilegx.h (tilegx_mnemonic): Add TILEGX_OPC_LD4S_TLS,
661 * tilepro.h (tilepro_mnemonic): Add TILEPRO_OPC_LW_TLS,
666 * i386.h (XACQUIRE_PREFIX_OPCODE): New.
672 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
679 * mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEONP.
687 * rl78.h: New file.
691 * mips.h: Fix a typo in description.
695 * sparc.h (struct sparc_opcode): Expand 'flags' to unsigned int.
703 * mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
712 * mips.h (INSN_WRITE_GPR_S, INSN2_WRITE_GPR_MB): New macros.
732 * sparc.h: Document new format codes '4', '5', and '('.
737 * mips.h: Document the use of FP_D in MIPS16 mode. Adjust the
742 * mips.h: Clarify the description of microMIPS instruction
749 * mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
892 * mips.h (INSN_TRAP): Rename to...
898 * avr.h (AVR_ISA_AVR6): Remove AVR_ISA_SPMX as it was actually
903 * avr.h (AVR_ISA_AVR6): Fix typo, adding AVR_ISA_SPMX.
907 * bfin.h (is_macmod_signed): New func
911 * bfin.h (is_macmod_pmove): Add missing space before func args.
916 * tilegx.h: New file.
917 * tilepro.h: New file.
921 * arm.h (ARM_ARCH_V7R_IDIV): Define.
925 * s390.h: Replace S390_OPERAND_REG_EVEN with
930 * s390.h: Add S390_OPCODE_REG_EVEN flag.
934 * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
939 * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
943 * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
949 * mips.h (M_PREF_AB): New enum value.
953 * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
959 * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
963 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
964 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
969 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
975 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
979 * mips.h: Update commentary after last commit.
983 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
989 * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
993 * mips.h: Fix previous commit.
997 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
1003 * arm.h (ARM_AEXT_V6M_ONLY): New define.
1009 * mips.h (INSN_LOONGSON_3A): Defined.
1015 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
1020 * arm.h (ARM_EXT_VIRT): New define.
1027 * arm.h (ARM_AEXT_ADIV): New define.
1032 * arm.h (ARM_EXT_OS): New define.
1038 * arm.h (ARM_EXT_MP): Add.
1043 * bfin.h: Declare pseudoChr structs/defines.
1047 * bfin.h: Strip trailing whitespace.
1051 * rx.h (RX_Operand_Type): Add TwoReg.
1056 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
1061 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
1078 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
1084 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
1089 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
1093 * maxq.h: Delete file.
1097 * ppc.h (PPC_OPCODE_E500): Define.
1101 * opcode/mips.h (INSN_MIPS16): Remove.
1105 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
1109 * alpha.h: Update copyright notice to use GPLv3.
1110 * arc.h: Likewise.
1111 * arm.h: Likewise.
1112 * avr.h: Likewise.
1113 * bfin.h: Likewise.
1114 * cgen.h: Likewise.
1115 * convex.h: Likewise.
1116 * cr16.h: Likewise.
1117 * cris.h: Likewise.
1118 * crx.h: Likewise.
1119 * d10v.h: Likewise.
1120 * d30v.h: Likewise.
1121 * dlx.h: Likewise.
1122 * h8300.h: Likewise.
1123 * hppa.h: Likewise.
1124 * i370.h: Likewise.
1125 * i386.h: Likewise.
1126 * i860.h: Likewise.
1127 * i960.h: Likewise.
1128 * ia64.h: Likewise.
1129 * m68hc11.h: Likewise.
1130 * m68k.h: Likewise.
1131 * m88k.h: Likewise.
1132 * maxq.h: Likewise.
1133 * mips.h: Likewise.
1134 * mmix.h: Likewise.
1135 * mn10200.h: Likewise.
1136 * mn10300.h: Likewise.
1137 * msp430.h: Likewise.
1138 * np1.h: Likewise.
1139 * ns32k.h: Likewise.
1140 * or32.h: Likewise.
1141 * pdp11.h: Likewise.
1142 * pj.h: Likewise.
1143 * pn.h: Likewise.
1144 * ppc.h: Likewise.
1145 * pyr.h: Likewise.
1146 * rx.h: Likewise.
1147 * s390.h: Likewise.
1148 * score-datadep.h: Likewise.
1149 * score-inst.h: Likewise.
1150 * sparc.h: Likewise.
1151 * spu-insns.h: Likewise.
1152 * spu.h: Likewise.
1153 * tic30.h: Likewise.
1154 * tic4x.h: Likewise.
1155 * tic54x.h: Likewise.
1156 * tic80.h: Likewise.
1157 * v850.h: Likewise.
1158 * vax.h: Likewise.
1162 * tic6x-control-registers.h, tic6x-insn-formats.h,
1163 tic6x-opcode-table.h, tic6x.h: New.
1167 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
1171 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
1175 * ia64.h (ia64_find_opcode): Remove argument name.
1183 * cgen.h: Include bfd_stdint.h.
1188 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
1193 * arm.h (ARM_EXT_V6_DSP): Define.
1199 * rx.h (rx_decode_opcode) (mvtipl): Add.
1204 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
1212 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
1213 * cgen.h: Update. Improve multi-inclusion macro name.
1217 * ppc.h (PPC_OPCODE_476): Define.
1221 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
1225 * rx.h: New file.
1229 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
1233 * ppc.h (PPC_OPCODE_PPCA2): New.
1237 * ia64.h (struct ia64_operand): Renamed member class to op_class.
1241 * tic30.h (template): Rename type template to
1243 * tic54x.h (template): Rename type template to
1248 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
1252 * moxie.h (MOXIE_F3_PCREL): Define.
1257 * moxie.h (MOXIE_F1_M): Define.
1261 * moxie.h: Created.
1265 * h8300.h: Add relaxation attributes to MOVA opcodes.
1269 * ppc.h (ppc_parse_cpu): Declare.
1273 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
1275 * score-datadep.h: Update dependency information.
1279 * ppc.h (PPC_OPCODE_POWER7): New.
1283 * i386.h: Add comment regarding sse* insns and prefixes.
1287 * mips.h (INSN_XLR): Define.
1295 * opcode/i386.h: Add multiple inclusion protection.
1304 * ppc.h (struct powerpc_opcode): New field "deprecated".
1309 * mips.h: Define CPU_R14000, CPU_R16000.
1314 * arm.h (FPU_NEON_FP16): New.
1319 * mips.h: Doucument '1' for 5-bit sync type.
1323 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
1328 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
1332 * ppc.h (PPC_OPCODE_405): Define.
1337 * ppc.h (ppc_cpu_t): New typedef.
1344 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
1351 * mips.h: Document new field descriptors +Q.
1356 * mips.h (INSN_MACRO): Move it up to the pinfo macros.
1361 * ppc.h: (PPC_OPCODE_E500MC): New.
1365 * i386.h (MAX_OPERANDS): Set to 5.
1370 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
1374 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
1378 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
1386 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
1392 * cr16.h (cr16_num_optab): Declared.
1397 * avr.h (AVR_ISA_2xxe): Define.
1401 * mips.h: Update copyright.
1409 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
1413 * avr.h (AVR_ISA_USB162): Add new opcode set.
1418 * mips.h (INSN_LOONGSON_2E): New.
1426 * mips.h (INSN_ISA*): Redefine certain values as an
1435 * ppc.h (PPC_OPCODE_PPCPS): New.
1439 * m68k.h: Document j K & E.
1443 * cr16.h: New file for CR16 target.
1447 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
1451 * m68k.h (mcfisa_c): New.
1456 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
1463 * i386.h (REX_MODE64): Renamed to ...
1474 * i386.h: Add entries from config/tc-i386.h and move tables
1475 to opcodes/i386-opc.h.
1479 * i386.h (FloatDR): Removed.
1484 * spu-insns.h: Add soma double-float insns.
1489 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
1495 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
1501 * i386.h (i386_optab): Put the real "test" before the pseudo
1506 * m68k.h (m68010up): OR fido_a.
1510 * m68k.h (fido_a): New.
1514 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
1520 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
1524 * score-inst.h (enum score_insn_type): Add Insn_internal.
1532 * spu-insns.h: New file.
1533 * spu.h: New file.
1537 * ppc.h (PPC_OPCODE_CELL): Define.
1541 * i386.h : Modify opcode to support for the change in POPCNT opcode
1546 * i386.h: Replace CpuMNI with CpuSSSE3.
1553 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
1557 * score-datadep.h: New file.
1558 * score-inst.h: New file.
1562 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
1569 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
1573 * i386.h (i386_optab): Add "nop" with memory reference.
1577 * i386.h (i386_optab): Update comment for 64bit NOP.
1582 * ppc.h (PPC_OPCODE_POWER6): Define.
1587 * mips.h: Improve description of MT flags.
1591 * m68k.h (mcf_mask): Define.
1596 * mips.h (enum): Add macro M_CACHE_AB.
1602 * mips.h: Add INSN_SMARTMIPS define.
1607 * mips.h: Defines udi bits and masks. Add description of
1613 * mips.h: Improve comments describing the bitfield instruction
1618 * arm.h (FPU_VFP_EXT_V3): Define constant.
1626 * avr.h (AVR_ISA_PWMx): New.
1630 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
1638 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
1642 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
1647 * i386.h (i386_optab): Support Intel Merom New Instructions.
1651 * arm.h: Add V7 feature bits.
1655 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
1660 * arm.h: Use ARM_CPU_FEATURE.
1668 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
1675 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
1679 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
1688 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
1690 * cgen.h: Likewise.
1694 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
1700 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
1706 * cgen.h (symcat.h): #include it.
1707 (cgen-bitset.h): #include it.
1709 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
1712 * cgen-bitset.h: New file.
1716 * bfin.h: New file.
1720 * ia64.h (enum ia64_opnd): Move memory operand out of set of
1725 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
1730 * hppa.h (pa_opcodes): Remove lha entries.
1734 * hppa.h (FLAG_STRICT): Revise comment.
1741 * bfin.h: New file.
1745 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
1749 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
1758 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
1769 * a29k.h: Delete.
1773 * ppc.h (PPC_OPCODE_E300): Define.
1777 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
1782 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
1787 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
1793 * hppa.h: Fix punctuation in comment.
1795 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
1804 * i386.h (i386_optab): Operands of aam and aad are unsigned.
1808 * i386.h (i386_optab): Support Intel VMX Instructions.
1812 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
1816 * i386.h (i386_optab): Add new insns.
1820 * sparc.h: Add typedefs to structure declarations.
1825 * i386.h (i386_optab): Update comments for 64bit addressing on
1830 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
1835 * hppa.h (FLAG_STRICT): Correct comment.
1842 * ppc.h (PPC_OPCODE_POWER5): Define.
1848 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
1849 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
1850 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
1851 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
1852 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
1853 tic54x.h, tic80.h, v850.h, vax.h
1857 * i386.h (i386_optab): Add ht and hnt.
1861 * i386.h: Insert hyphens into selected VIA PadLock extensions.
1869 * m88k.h: Rename psr macros to avoid conflicts.
1872 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
1877 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
1884 * crx.h (enum argtype): Rename types, remove unused types.
1887 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
1900 * crx.h (operand_type): Remove redundant types i3, i4,
1906 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1911 * i386.h (i386_optab): Add rdtscp.
1915 * i386.h (i386_optab): Don't allow the `l' suffix for moving
1922 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1928 * m68k.h (m68008, m68ec030, m68882): Remove.
1937 * cgen.h (enum cgen_parse_operand_type): Add
1942 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1948 * mips.h (struct mips_opcode): Add new pinfo2 member.
1957 * mips.h (CPU_RM9000): Define.
1962 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1971 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1979 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1985 * maxq.h: New file: Disassembly information for the maxq port.
1989 * i386.h (i386_optab): Put back "movzb".
1993 * cris.h (enum cris_insn_version_usage): Tweak formatting and
2008 * i386.h (sldx_Suf): Remove.
2024 * crx.h: Add COPS_REG_INS - Coprocessor Special register
2029 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
2034 * avr.h: Add support for
2039 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
2043 * msp430.h (msp430_opc): Add new instructions.
2050 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
2055 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
2059 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
2063 * i386.h: Adjust instruction descriptions to better match the
2068 * arm.h: Remove all old content. Replace with architecture defines
2073 * m68k.h: Fix comment.
2077 * crx.h: New file.
2081 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
2085 * m68k.h: Add 'size' to m68k_opcode.
2089 * m68k.h: Switch from ColdFire chip name to core variant.
2093 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
2101 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
2105 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
2109 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
2113 * i386.h (i386_optab): Added xstore/xcrypt insns.
2117 * h8300.h (32bit ldc/stc): Add relaxing support.
2121 * h8300.h (BITOP): Pass MEMRELAX flag.
2125 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32