Lines Matching refs:opc
3 * mips-opc.c: Add FP_D to s.d instruction flags.
7 * m68k-opc.c (halt, pulse): Enable them on the 68060.
11 * tic80-opc.c (tic80_opcodes): Revert change that put the 32 bit
17 * d30v-opc.c (d30v_opcode_table): Set new flags bits
31 * tic80-opc.c (OFF_SL_PC, OFF_SL_BR): Minor formatting change.
37 * alpha-opc.c (cvttq/*u*): Remove, as that suffix is invalid.
48 * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
64 * arm-opc.h: Display nop pseudo ops alongside equivalent disassembly.
69 * m68k-opc.c (btst): Change Dd@s to Dd;b.
76 * m68k-opc.c: Add argument for lpstop. From Olivier Carmona
83 * d30v-opc.c (d30v_opcode_table, case cmpu): Immediate field is
94 * d10v-opc.c (OPERAND_FLAG): Split into:
101 * mips-opc.c: Move the INSN_MACRO ISA value to the membership
103 * mips16-opc.c: same
107 * mips-opc.c (sync,cache): These are 3900 insns.
111 sh-opc.h (sh_table): Remove ftst/nan.
115 * mips-opc.c (ffc, ffs): Fix mask.
119 * d30v-opc.c (pre_defined_registers): Add eit_vb, int_s, and int_m
124 * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
129 * mips-opc.c: Fix bug in mask for "not" pseudo-instruction.
138 * sparc-opc.c: Add wr & rd for v9a asr's.
145 * sparc-opc.c (v9notv9a): New insn type.
151 * mips-opc.c (bnezl,beqzl): Mark these as also tx39.
155 * mips-opc.c: Note that 'jalx' is (probably incorrectly) marked I1.
168 * v850-opc.c (extract_d22): Use signed arithmatic.
172 * mips-opc.c: Three op mult is not an ISA insn.
176 * mips-opc.c: Fix formatting.
192 * v850-opc.c: Fix typo in comment.
205 * m68k-opc.c (TBL1): Use ! rather than `.
210 * m68k-opc.c: Correct bchg, bclr, bset, and btst on ColdFire.
212 * m68k-opc.c: Accept tst{b,w,l} with immediate operands on cpu32.
214 * m68k-opc.c: Correct movew of an immediate operand to %sr or %ccr
223 * v850-opc.c ("cmov"): Order reg param r1, r2 not r2, r2.
227 * sparc-opc.c (sparclet_cpreg_table): Add %ccsr2, %cccrr, %ccrstr.
231 * v850-opc.c (v850_opcodes): Further rearrangements.
235 * d30v-opc.c (rot2h, sra2h, srl2h insns): Revert last change.
239 * v850-opc.c (v850_opcodes): Fields reordered to allow assembler
244 * mips-opc.c: Added tx39 insns sdbbp, rfe, and deret.
248 * v850-opc.c: Initialise processors field of v850_opcode structure.
254 * d30v-opc.c: Change mvfacc to accept 6-bit unsigned values.
256 * d30v-opc.c (pre_defined_registers): Add control registers from 0-63.
265 * d30v-opc.c (d30v_opcode_table): Change form for repeati.
272 * d30v-opc.c: Correct entries for repeat*, and sat*.
276 * d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
278 * d30v-opc.c (pre_defined_registers): Change control registers.
280 * d30v-opc.c (d30v_format_table): Correct SHORT_C1 and
290 * d30v-opc.c: Change mulx2h to require an even register.
298 * d30v-opc.c (SHORT_M2, LONG_M2): Two new forms.
306 * sparc-opc.c (sparc_opcodes): Fix assembler args to
313 * sparc-opc.c (sparc_opcodes): Fix op3 field for fcmpq/fcmpeq.
334 * v850-opc.c: Update comments. Remove use of
339 * v850-opc.c (MOVHI): Immediate parameter is unsigned.
350 * v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
355 * v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other.
359 * alpha-opc.c (alpha_opcodes): Fix hw_rei_stall mungage.
363 * v850-opc.c (v850_opcodes[]): Remove use of flag field.
364 * v850-opc.c (v850_opcodes[]): Add support for reversed short load
381 * Makefile.am (ALL_MACHINES): Add arc-dis.lo, arc-opc.lo.
383 * arc-dis.c, arc-opc.c: New files.
391 * v850-opc.c (insert_i5div, extract_i5div): New Functions.
396 * v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
401 * v850-opc.c: Reorganised and re-layed out to improve readability
437 * mips-opc.c: Fix typo/thinko in "eret" instruction.
441 * sparc-opc.c (sparc_opcodes): Fix spelling on fpaddX, fpsubX insns.
451 * cgen-opc.c: #include <ctype.h>.
458 * mips-opc.c (mips_builtin_opcodes): If an insn uses single
465 * ppc-opc.c (extract_nsi): make unsigned expression signed before
472 * sparc-opc.c: The fcmp v9a instructions take an integer register
495 * mips-opc.c: Add r3900 insns.
524 * m32r-opc.c (m32r_cgen_insn_table, cmpui): Undo patch of May 2.
528 * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
530 * mips16-opc.c (mip16_opcodes): same.
534 * m68k-opc.c (moveb): Change $d to %d.
548 * m32r-opc.c (m32r_cgen_insn_table, cmpui): Use $uimm16 instead
553 * m32r-opc.h (CGEN_ARCH): Renamed from CGEN_CPU.
600 * cgen-opc.c (hash_keyword_name): Improve algorithm.
606 * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: New files.
607 * cgen-asm.c, cgen-dis.c, cgen-opc.c: New files.
634 * m10200-opc.c: Rename from mn10200-opc.c.
636 * m10300-opc.c: Rename from mn10300-opc.c.
639 * mips16-opc.c: Add mul and dmul macros.
647 * mips-opc.c: Add "wait". From Ralf Baechle
659 * ppc-opc.c: Add PPC 403 instructions and extended opcodes. From
662 * mips-opc.c: Add cast when setting mips_opcodes.
667 * v850-opc.c (extract_d*): Fix sign extension problems to make
672 * sh-opc.h: Add bf/s and bt/s as synonyms for bf.s and bt.s.
674 * mips-opc.c: Add dctr and dctw.
692 * m68k-opc.c (m68k_opcode_aliases): Added blo and blo{s,b,w,l}.
696 * mn10200-opc.c: Change "trap" to "syscall".
697 * mn10300-opc.c: Add new "syscall" instruction.
701 * m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
716 * ppc-opc.c (valid_bo): Add prototype.
721 * sparc-opc.c (arg): Change name field to be const.
740 * mn10300-opc.c (IMM16_PCREL, SD8N_PCREL, D16_SHIFT): Mark these
745 * m68k-opc.c (m68k_opcodes): Fix last change for the mc68010.
749 * m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
754 * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
762 * tic80-opc.c (tic80_predefined_symbols): Define r25 properly.
773 * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes,
778 * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
783 * tic80-opc.c (LSI_SCALED): Renamed from this ...
791 * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
799 * tic80-opc.c (tic80_predefined_symbols): Revert change to
807 * d30v-opc.c: Removed references to FLAG_X.
819 * d30v-opc.c: New file.
824 * tic80-opc.c (tic80_predefined_symbols): Add symbolic
829 * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values
846 * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
850 * mn10200-opc.c (IMM16_PCREL): This is a signed operand.
866 * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'.
879 * tic80-opc.c (tic80_symbol_to_value): Changed to accept
885 * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E,
896 * mips16-opc.c: Add new cases of exit instruction for
904 * tic80-opc.c (tic80_predefined_symbols): Table of name/value
920 * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
933 * m68k-opc.c (m68k_opcodes): Changed operand specifier for the
942 * tic80-opc.c (tic80_opcodes): Expand comment to note that the
967 * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
972 * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
977 * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
982 * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V):
992 * tic80-opc.c (tic80_operands): Reorder some table entries to make
1001 * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS.
1020 * tic80-opc.c (SPFI): Add single precision floating point
1041 * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
1057 * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
1069 * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
1076 * ppc-opc.c (powerpc_operands): Make comment match the
1078 * sparc-opc.c (sparc_opcodes): Document why this cannot be "const".
1081 * tic80-opc.c (tic80_operands): Begin construction operands table.
1088 * m68k-opc.c: Add #B case for moveq.
1097 * v850-opc.c (v850_opcodes): Put curly-braces around operands
1107 * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY
1112 * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.
1113 (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
1117 * mips16-opc.c: Add "abs".
1121 * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
1132 * tic80-opc.c: Add file.
1136 * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link.
1140 * mn10200-opc.c (mn10200_operands): Add SIMM16N.
1144 * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.
1146 * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".
1157 * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
1163 * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".
1167 * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
1170 * mn10200-opc.c (mn10200_operands): Fix insertion position
1175 * mn10200-opc.c: Create mn10200 opcode table.
1181 * Makefile.in (ALL_MACHINES): Add mips16-opc.o.
1185 * m68k-opc.c (m68k_opcodes): Revert change to use < and >
1194 * mips16-opc.c: Change opcode for entry/exit to avoid conflicting
1199 * mn10300-opc.c: Add some comments explaining the various
1209 * m68k-opc.c (m68k_opcodes): Simplify table by using < and >
1214 * ppc-opc.c (insert_li): Give an error if the offset has the two
1227 * mn10300-opc.c (mn10300_opcodes): Fix mask field for
1235 * mips16-opc.c: New file.
1243 * mips-opc.c: Add jalx instruction.
1244 * Makefile.in (mips16-opc.o): New target.
1245 * configure.in: Use mips16-opc.o for bfd_mips_arch.
1250 * m68k-opc.c (m68k_opcodes): Simplify table by using < and >
1253 * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
1256 * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
1260 * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
1267 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
1279 * mn10300-opc.c: Fix handling of register list operand for
1284 * mn10300-opc.c: Distinguish between absolute memory addresses,
1296 * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
1298 * mn10300-opc.c (mn10300_operands): Add "REGS" for a register
1304 * d10v-opc.c (d10v_opcodes): Add3 sets the carry.
1308 * mn10300-opc.c (mn10300_opcodes): Demand parens around
1313 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and
1318 * mn10300-opc.c (mn10300_operands): Hijack "bits" field
1324 * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
1328 * mn10300-opc.c (mn10300_operands): Remove many redundant
1335 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
1345 * d10v-opc.c (d10v_opcodes): Declare the trap instruction
1351 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
1361 * alpha-opc.c (alpha_operands): Rearrange flags slot.
1367 * v850-opc.c (v850_opcodes): Add relaxing "jbr".
1376 * v850-opc.c (D9_RELAX): Renamed from D9, all references
1386 * v850-opc.c (insert_d8_6): Fix operand insertion for sld.w
1389 * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
1399 * ppc-opc.c (PPCPWR2): Define.
1405 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode
1414 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field
1417 * mn10300-opc.c (FMT*): Remove definitions.
1419 * mn10300-opc.c (mn10300_opcodes): Fix destination register
1422 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM
1428 * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
1433 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
1439 * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's
1444 * mn10300-opc.c (FMT_XX): Renumber starting at one.
1454 * m68k-opc.c (plusha): Prefer encoding for m68040up, in case
1459 * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for
1462 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the
1467 * mn10200-opc.c, mn10300-opc.c: New files.
1469 * mn10x00-opc.c, mn10x00-dis.c: Deleted.
1481 * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita
1499 * v850-opc.c (v850_operand): Add displacement flag to 9 and 22
1505 * m68k-opc.c: Move the fmovemx data register cases before the
1511 * mips-opc.c: Add a case for "div" and "divu" with two registers
1526 * sparc-opc.c (sparc_opcodes): Add setuw, setsw, setx.
1534 * v850-opc.c (insert_d9, insert_d22): Fix boundary case
1541 * v850-opc.c (v850_opcodes: Remove size field from all opcodes.
1558 * v850-opc.c (BOP_MASK): Fix.
1567 * v850-opc.c (insert_d8_7, extract_d8_7): New functions.
1578 * v850-opc.c (insert_d16_15, extract_d16_15): New functions.
1585 * v850-opc.c (insert_d9, insert_d22): Slightly improve error
1588 * v850-opc.c: Add notes about needing special insert/extract
1591 * v850-opc.c (insert_d22, extract_d22): New functions.
1598 * v850-opc.c (v850_operands): Add V850_OPERAND_SIGNED flag
1603 * v850-opc.c (v850_operands): Define SR2 operand.
1606 * v850-opc.c (v850_opcodes): Fix opcode specs for
1611 * v850-opc.c (v850_opcodes): Add null opcode to mark the
1616 * d10v-opc.c (pre_defined_registers): Added register pairs,
1621 * v850-opc.c (v850_operands): Make I16 be a signed operand.
1625 * v850-opc.c (v850_operands): Define EP operand.
1628 * v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"
1631 * v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]
1634 * v850-opc.c (v850_operands): "not" is a two byte insn
1636 * v850-opc.c (v850_opcodes): Correct bit pattern for setf.
1638 * v850-opc.c (v850_operands): D16 inserts at offset 16!
1640 * v850-opc.c (two): Get order of words correct.
1642 * v850-opc.c (v850_operands): I16 inserts at offset 16!
1644 * v850-opc.c (v850_operands): Add "SR1" and "SR2" for system
1648 * v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode. Fix
1651 * v850-opc.c (v850_opcodes): Add initializer for size field
1654 * v850-opc.c (v850_operands): D6 -> DS7. References changed.
1661 * v850-opc.c (v850_operands): 3-bit immediate for bit insns
1664 * v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
1669 * v850-opc.c (v850_operands): Added insert and extract fields,
1674 * v850-opc.c (v850_opcodes): Enable "trap".
1676 * v850-opc.c (v850_opcodes): Fix order of displacement
1681 * v850-opc.c (v850_operands): Add "B3" support.
1685 * v850-opc.c (v850_opcodes): "jmp" has only an R1 operand.
1687 * v850-opc.c: Close unterminated comment.
1691 * v850-opc.c (v850_operands): Add flags field.
1696 * Makefile.in (ALL_MACHINES): Add v850-opc.o.
1699 * v850-opc.c: New file.
1707 * d10v-opc.c: Add additional information to the opcode
1718 * arm-opc.h: Added "bx" instruction definition.
1722 * alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
1726 * d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
1730 * d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
1734 * makefile.vms: Update for alpha-opc changes.
1743 * d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
1748 * m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose
1753 * arm-opc.h: (arm_opcodes): Added halfword and sign-extension
1760 * d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
1777 * d10v-opc.c: Changes to support signed and unsigned numbers.
1788 * m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
1793 * d10v-opc.c (pre_defined_registers): Declare.
1799 * sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix
1824 * d10v-opc.c: New file.
1829 * m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
1872 * alpha-opc.c: Add new case of "mov". From Klaus Kaempf
1877 * alpha-opc.c: Correct second case of "mov" to use OPRL.
1886 * m68k-opc.c (m68k_opcodes): Add coldfire support.
1890 * sparc-opc.c (asi_table): Add #ASI_N, #ASI_N_L, #ASI_NUCLEUS,
1903 * alpha-opc.c: New file.
1904 * alpha-opc.h: Remove.
1906 * configure.in: For bfd_alpha_arch, use alpha-opc.o.
1908 * Makefile.in (ALL_MACHINES): Add alpha-opc.o.
1910 alpha-opc.h.
1911 (alpha-opc.o): New target.
1919 * sparc-opc.c: Add some two operand forms of the wr instruction.
1931 * sparc-opc.c: Add beq/teq as aliases for be/te.
1933 * ppc-opc.c: Fix fcmpo opcode. From Sergei Steshenko
1953 * ppc-opc.c (instruction encoding macros): Add explicit casts to
1959 * sparc-opc.c (sparc_opcodes): Add ultrasparc vis extensions.
1966 * sparc-opc.c (sparc_opcodes): Use X for 5 bit shift constants,
1976 * sparc-opc.c: Set F_FBR on floating point branch instructions.
1981 * ppc-opc.c (PPC860): Macro for 860/821 specific instructions and
2010 * sparc-opc.c (MASK_*): Use SPARC_OPCODE_ARCH_MASK.
2021 * sparc-opc.c (sparc_opcodes): rd must be 0 for
2047 * sparc-opc.c (sparc_opcodes): Use 'O' operand char for `neg reg'.
2061 * sparc-opc.c (v8,v6notv9): Add MASK_SPARCLET.
2094 * sparc-opc.c (MASK_<ARCH>): Define.
2120 * ppc-opc.c (PPC): Undef, so default defination on Windows NT
2125 * m68k-opc.c (m68k_opcodes): The bkpt instruction is supported on
2177 * sparc-opc.c (sparc_opcode_archs): Mark v8/sparclite as conflicting.
2189 * sparc-opc.c (sparc_opcode_archs): Replaces architecture_pname.
2203 * sparc-opc.c (architecture_pname): Add v9a.
2207 * alpha-opc.h (alpha_insn_set): VAX floating point opcode was
2224 * ppc-opc.c (powerpc_opcodes): tlbi POWER opcode form different
2233 * ppc-opc.c (fsqrt{,.}): Duplicate for PowerPC in addition to
2238 * sh-opc.h (sh_nibble_type): Added REG_B.
2261 * sh-opc.h (sh_arg_type): Added A_SSR and A_SPC.
2267 * ppc-opc.c (subfc., subfco): Mark this PPCCOM, not PPC.
2304 * m68k-opc.c (m68k_opcodes): Correct fmoveml operands.
2313 * m68k-opc.c: Use #W rather than #w.
2318 * m68k-opc.c (m68k_opcode_aliases): Add dbfw as an alias for dbf,
2327 * mips-opc.c: Added shorthand (V1) for INSN_4100 manifest. Added
2337 * ppc-opc.c (whole file): Add flags for common/any support.
2365 * alpha-opc.h (MEMORY_FUNCTION_FORMAT_MASK): added.
2375 * mpw-config.in: Add m68k-opc.c.o to BFD_MACHINES for m68k,
2376 no longer create sysdep.h, sed ppc-opc.c to work around a
2388 * m68k-opc.c: Split pmove patterns which use 'P' into patterns
2396 * sparc-opc.c (sparc_opcodes): Mark all insns that reference
2409 * mips-opc.c: Change unaligned loads and stores with "t,A"
2432 * sh-opc.h (sh_arg_type): Add F_FR0.
2437 * sh-opc.h (sh_opcode_info): Increase arg array size to 4.
2477 * sh-opc.h (ftrc): Change FPUL_N to FPUL_M.
2481 * sparc-opc.c (sparc_opcodes): Delete duplicate wr %y insn.
2485 * sparc-opc.c (sparc_opcodes): Fix prefetcha insn.
2493 * sh-opc.h: Add blank lines to improve readabililty of sh3e
2504 * sparc-opc.c (asi, membar): New static locals.
2513 * m68k-opc.c (m68k_opcode_aliases): Add br, brs, brb, brw, brl.
2517 * m68k-opc.c (m68k_opcode_aliases): Add bhib as an alias for bhis,
2524 * sh-opc.h (FP sts instructions): Update to match reality.
2540 * m68k-opc.c (m68k_opcode_aliases): Add jsrl and jsrs as aliases
2547 * sh-opc.h (sh_arg_type): Add new operand types.
2560 * m68k-opc.c: New file, holding tables from include/opcode/m68k.h.
2568 * Makefile.in (ALL_MACHINES): Add m68k-opc.o.
2569 (m68k-opc.o): New target.
2570 * configure.in: Build m68k-opc.o for bfd_m68k_arch.
2586 * sparc-opc.c (all non-v9 insns): Use flag F_NOTV9 instead of F_ALIAS.
2593 * sh-opc.h (sh_table): Fully bracket last entry.
2597 * sparc-opc.c (sllx, srax, srlx): Fix disassembly.
2615 * mips-opc.c (L1): Define.
2622 * mips-opc.c (mips_opcodes): For the move pseudo-op, prefer daddu
2626 * ppc-opc.c (powerpc_operands): Change CR to use a bitsize of 3,
2638 * sh-opc.h: Add copyright.
2647 * sh-opc.h (sh_table): Add SH3 support.
2651 * sh-opc.h: Added bsrf and braf.
2655 * arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete
2658 * arm-opc.h (arm_opcodes): Correct typos in stm, ldm, std, and ldc.
2667 * sh-opc.h (sh_nibble_type, sh_arg_type): remove trailing , from
2736 * alpha-opc.h (OSF_ASMCODE): define
2746 * mips-opc.c: Add new mips4 instructions. Don't set INSN_RFE for
2765 * ppc-opc.c: Sort recently added instructions by minor opcode
2774 * mips-opc.c: Change dli to use M_DLI, and add dla.
2782 * mips-opc.c: Add r4650 mul instruction.
2786 * mips-opc.c: Add uld and usd macros for unaligned double load and
2791 * ppc-opc.c (powerpc_opcodes): Add 403GA opcodes rfci, dccci,
2812 * ppc-opc.c (extract_bdm): Correct parenthezisation.
2818 * ppc-opc.c: Changes based on patch from David Edelsohn
2832 * mips-opc.c (P3): Define.
2839 * w65-opc.h, w65-dis.c: New files.
2848 * mips-opc.c: Add dli as a synonym for li.
2864 * sh-opc.h (mov.l gbr): Get direction right.
2882 * mips-opc.c: Use or instead of addu for pseudo-op move, since
2906 * mips-opc.c (mips_opcodes): "dabs" is only available with -mips3.
2914 * mips-opc.c (mips_opcodes): Set WR_t for sc and scd.
2922 * mips-opc.c: Set INSN_STORE_MEMORY flag for all instructions
2928 * arm-dis.c, arm-opc.h: New files.
2940 * sparc-opc.c: Added sparclite extended FP operations, and
3030 * z8k-opc.h: (resflg): Fix patterns.
3031 * h8500-opc.h Fix CR insn patterns.
3035 * ppc-opc.c (powerpc_opcodes): Put PowerPC versions of "cmp" and
3051 * ppc-opc.c (powerpc_operands): Added RAL, RAM and RAS.
3058 * ppc-opc.c (powerpc_opcodes): Correct fcir. From David Edelsohn
3063 * mips-opc.c (mips_opcodes): Correct operands of "nor" with an
3068 * sparc-opc.c (sparc_opcodes): Fix "rd %fprs,%l0".
3072 * ppc-opc.c (powerpc_operands): The signedp field has been
3092 * ppc-opc.c: Define POWER2 as short alias flag.
3119 * mips-opc.c: It's sqrt.s, not sqrt.w. From
3124 * ppc-opc.c (powerpc_opcodes): The POWER uses bdn[l][a] where the
3133 * configure.in (bfd_powerpc_arch): Use ppc-dis.o and ppc-opc.o.
3135 * ppc-opc.c (powerpc_opcodes): Mark POWER instructions supported
3163 * ppc-opc.c (powerpc_operands): New operand type MBE to handle a
3189 * ppc-opc.c: New file. Opcode table for PowerPC, including
3192 * Makefile.in (ALL_MACHINES): Add ppc-dis.o and ppc-opc.o.
3194 (ppc-dis.o, ppc-opc.o): New targets.
3195 * configure.in: Build ppc-dis.o and ppc-opc.o for bfd_rs6000_arch.
3220 * mips-opc.c: Use macro for j instruction, to support SVR4 PIC.
3227 * mips-opc.c: Make cache use k, not t.
3231 * alpha-opc.h, alpha-dis.c (print_insn_alpha): Add
3237 * mips-opc.c: Use macros for jal variants, to support SVR4 PIC.
3245 * mips-opc.c (dsll, dsra, dsrl): Added '>' cases for shift counts
3250 * z8kgen.c, z8k-opc.h: Add full lda information.
3260 * mips-opc.c: Moved l.d down so that it disassembles as ldc1.
3264 * alpha-opc.h: Add ldl_l, fix typo for ldq_u.
3269 * mips-opc.c: Correct lwu opcode value (book had it wrong).
3290 * mips-opc.c: Set hazard information correctly for branch
3295 * alpha-dis.c (print_insn_alpha), alpha-opc.h: Fix bugs, use
3301 * mips-opc.c: Set INSN_TRAP for tXX instructions.
3305 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson):
3315 * mips-opc.c: Change div machine instruction to be z,s,t rather
3326 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Set
3341 * mips-opc.c ("absu"): Removed.
3346 * mips-opc.c: Added r6000 and r4000 instructions and macros.
3352 * mips-opc.c: li.d uses "T,L", not "S,F". Added li.s.
3377 * mips-opc.c: Added lwc1 E,A(b) to go with lwc1 T,A(b). Similarly
3382 * sparc-opc.c: Change CONST to const to deal with gcc
3387 * mips-opc.c: From davidj@ICSI.Berkeley.EDU (David Johnson): Took
3397 * sparc-opc.c: Add F_JSR, F_UNBR, or F_CONDBR flags to each branch
3408 * sparc-opc.c (call): Accept all 6 addressing modes valid for
3433 * mips-opc.c: New file, containing opcode table from
3478 * sh-dis.c, sh-opc.h: Understand some more opcodes.
3539 * h8500-opc.h (addr_class_type): No comma at end of enumerator.
3540 * sh-opc.h (sh_nibble_type, sh_arg_type): Ditto.
3580 * sh-dis.c, sh-opc.h: New files.
3584 * alpha-dis.c, alpha-opc.h: New files.
3597 * a29k-dis.c, sparc-dis.c, sparc-opc.c: Use CONST rather than
3621 * sparc-opc.c: Add ALIAS bit to aliases. Fix up opcode tables.
3654 * h8500-opc.h: Fix couple of opcodes.
3666 * h8500-dis.c, h8500-opc.h: New files
3701 * z8kgen.c, z8k-opc.h: fix sizes of some shifts.
3715 * z8k-dis.c z8k-opc.h z8kgen.c: checkpoint
3738 * z8kgen.c z8k-opc.h: bug fixes in tables
3758 (sparc-opc.o): Avoid Sun Make VPATH bug.
3772 * sparc-opc.c: New file, moved from BFD.
3786 * z8k-opc.h: new file full of z8000 opcodes
3790 * Renamed opc-sparc.c to sparc-opc.c for systems with short