Lines Matching refs:v850_opcodes

231 	* v850-opc.c (v850_opcodes): Further rearrangements.
239 	* v850-opc.c (v850_opcodes): Fields reordered to allow assembler
350 	* v850-opc.c (v850_opcodes[]): Add NOT_R0 flag to decect cases
355 	* v850-opc.c (v850_opcodes[]): Move divh opcodes next to each other.
363 	* v850-opc.c (v850_opcodes[]): Remove use of flag field.
364 	* v850-opc.c (v850_opcodes[]): Add support for reversed short load
392 	(v850_opcodes): Add v850EA instructions.
399 	(v850_opcodes): Add v850E instructions.
1097 	* v850-opc.c (v850_opcodes): Put curly-braces around operands
1367 	* v850-opc.c (v850_opcodes): Add relaxing "jbr".
1389 	* v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for
1501 	* (v850_opcodes):  Add breakpoint insn.
1541 	* v850-opc.c (v850_opcodes: Remove size field from all opcodes.
1559 	(v850_opcodes): Fix mask for jarl and jr.
1575 	(v850_opcodes): Use IF4A/IF4B for sld.b/sst.b.  Use IF4C/IF4D for
1583 	(v850_opcodes): Use IF7C and IF7D for ld.b and st.b.
1604 	(v850_opcodes): "ldsr" uses R1,SR2.
1606 	* v850-opc.c (v850_opcodes): Fix opcode specs for
1611 	* v850-opc.c (v850_opcodes): Add null opcode to mark the
1623 	(v850_opcodes): Use I16U for "ori", "andi" and "xori".
1628 	* v850-opc.c (v850_opcodes): Fix opcode numbers for "mov"
1631 	* v850-opc.c (v850_opcodes): Get ld.[bhw] and st.[bhw]
1636 	* v850-opc.c (v850_opcodes): Correct bit pattern for setf.
1646 	(v850_opcodes): Use SR1 and SR2 for "ldsr" and "stsr".
1648 	* v850-opc.c (v850_opcodes): Fix thinko in "jmp" opcode.  Fix
1651 	* v850-opc.c (v850_opcodes): Add initializer for size field
1658 	(v850_opcodes): For "sld.h", "sld.w", "sst.h", "sst.w", use
1664 	* v850-opc.c (v850_opcodes): Correct short store half (sst.h) and
1674 	* v850-opc.c (v850_opcodes): Enable "trap".
1676 	* v850-opc.c (v850_opcodes): Fix order of displacement
1682 	(v850_opcodes): Fix and enable "set1", "clr1", "not1"
1685 	* v850-opc.c (v850_opcodes): "jmp" has only an R1 operand.
1692 	(v850_opcodes): add move opcodes.