Lines Matching refs:ZA
222 #define ZA (FC + 1) macro
224 #define ZB (ZA + 1)
412 #define ARG_FPZ1 { ZA, FB, DFC1 }
417 #define ARG_OPRZ1 { ZA, RB, DRC1 }
418 #define ARG_OPRLZ1 { ZA, LIT, RC }
490 MEM_MASK, BASE, { ZA } }, /* pseudo */
562 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
563 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
564 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
566 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
1019 { "fnop", FP(0x17,0x020), BASE, { ZA, ZB, ZC } }, /* pseudo */
1020 { "fclr", FP(0x17,0x020), BASE, { ZA, ZB, FC } }, /* pseudo */
1044 { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } },
1045 { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } },
1049 { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */
1051 { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */
1052 { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */
1067 BASE, { ZA, CPRB } },
1315 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
1327 { "hw_jmp", EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
1328 { "hw_jsr", EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
1329 { "hw_ret", EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
1330 { "hw_jcr", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
1331 { "hw_coroutine", EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
1332 { "hw_jmp/stall", EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
1333 { "hw_jsr/stall", EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
1334 { "hw_ret/stall", EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
1335 { "hw_jcr/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
1336 { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
1478 { "br", BRA(0x30), BASE, { ZA, BDISP } }, /* pseudo */