Lines Matching refs:OP_MASK

29 #define OP_MASK		OP (0x3f)  macro
1345 { "add",	OP  (0x0e),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1346 { "add",	OP  (0x12),		OP_MASK,		IF2, 			0, PROCESSOR_ALL },
1348 { "addi",	OP  (0x30),		OP_MASK,		IF6, 			0, PROCESSOR_ALL },
1352 { "and",	OP (0x0a),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1354 { "andi",	OP (0x36),		OP_MASK,		IF6U, 			0, PROCESSOR_ALL },
1463 { "cmp",	OP  (0x0f),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1464 { "cmp",	OP  (0x13),		OP_MASK,		IF2, 			0, PROCESSOR_ALL },
1488 { "divh",	OP  (0x02),		OP_MASK,		{R1_NOTR0, R2_NOTR0},	0, PROCESSOR_ALL },
1629 { "mov",        OP  (0x00),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
1630 { "mov",	OP  (0x10),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
1635 { "movea",	OP  (0x31),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
1637 { "movhi",	OP  (0x32),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
1642 { "mulh",	OP  (0x17),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
1643 { "mulh",	OP  (0x07),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
1645 { "mulhi",	OP  (0x37),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
1652 { "not",	OP (0x01),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1657 { "or",		OP (0x08),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1659 { "ori",	OP (0x34),		OP_MASK,		IF6U, 			0, PROCESSOR_ALL },
1679 { "sar",	OP (0x15),		OP_MASK,		{I5U, R2}, 		0, PROCESSOR_ALL },
1685 { "satadd",	OP (0x11),		OP_MASK,		{I5, R2_NOTR0},		0, PROCESSOR_ALL },
1686 { "satadd",	OP (0x06),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
1689 { "satsub",	OP (0x05),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
1691 { "satsubi",	OP (0x33),		OP_MASK,		{I16, R1, R2_NOTR0},	0, PROCESSOR_ALL },
1693 { "satsubr",	OP (0x04),		OP_MASK,		{R1, R2_NOTR0},		0, PROCESSOR_ALL },
1716 { "shl",	OP  (0x16),		OP_MASK,	      	{I5U, R2}, 		0, PROCESSOR_ALL },
1720 { "shr",	OP  (0x14),		OP_MASK,	      	{I5U, R2}, 		0, PROCESSOR_ALL },
1774 { "sub",	OP  (0x0d),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1776 { "subr", 	OP  (0x0c),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1792 { "tst",	OP (0x0b),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1797 { "xor",	OP (0x09),		OP_MASK,		IF1, 			0, PROCESSOR_ALL },
1799 { "xori",	OP (0x35),		OP_MASK,		IF6U, 			0, PROCESSOR_ALL },