| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 306 unsigned BaseReg, in isFrameOffsetLegal()
317 unsigned BaseReg, in materializeFrameBaseRegister()
338 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | AArch64LoadStoreOptimizer.cpp | 880 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg(); in findMatchingInsn() local
1105 unsigned BaseReg, int Offset) { in isMatchingUpdateInsn()
1163 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnForward() local
1219 unsigned BaseReg = getLdStBaseOp(MemMI).getReg(); in findMatchingUpdateInsnBackward() local
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| D | AArch64StorePairSuppress.cpp | 143 unsigned BaseReg; in runOnMachineFunction() local
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
372 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 127 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg()
183 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate()
423 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | ARMBaseRegisterInfo.cpp | 558 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
582 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
610 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
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| D | Thumb2SizeReduction.cpp | 421 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
450 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
463 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| D | ARMLoadStoreOptimizer.cpp | 1494 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR()
1521 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
2011 unsigned &BaseReg, int &Offset, in CanFormLdStDWord()
2170 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
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| D | Thumb2InstrInfo.cpp | 218 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate()
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
330 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| D | ImplicitNullChecks.cpp | 327 unsigned BaseReg, Offset; in analyzeBlockForNullChecks() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 822 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
830 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
837 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
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| D | TargetInstrInfo.h | 920 RegSubRegPair &BaseReg, in getInsertSubregLikeInputs()
977 virtual bool getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg, in getMemOpBaseRegImmOfs()
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 245 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference() local
310 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference() local
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| D | X86SelectionDAGInfo.cpp | 40 unsigned BaseReg = TRI->getBaseRegister(); in isBaseRegConflictPossible() local
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| D | X86InstrInfo.cpp | 2269 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { in regIsPICBase()
2354 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable() local
2376 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable() local
4579 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg, in getMemOpBaseRegImmOfs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 980 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
1000 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
1025 unsigned BaseReg, in isFrameOffsetLegal()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86ATTInstPrinter.cpp | 189 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| D | X86IntelInstPrinter.cpp | 159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 266 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
833 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexReg()
1068 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm()
1340 int BaseReg = SM.getBaseReg(); in ParseIntelBracExpression() local
1955 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 460 for (const SCEV *BaseReg : BaseRegs) in hasRegsUsedByUsesOtherThan() local
476 for (const SCEV *BaseReg : BaseRegs) { in print() local
1009 for (const SCEV *BaseReg : F.BaseRegs) { in RateFormula() local
1296 for (const SCEV *BaseReg : F.BaseRegs) in InsertFormula() local
3063 for (const SCEV *BaseReg : F.BaseRegs) in CountRegisters() local
3239 const SCEV *BaseReg = IsScaledReg ? Base.ScaledReg : Base.BaseRegs[Idx]; in GenerateReassociationsImpl() local
3347 for (const SCEV *BaseReg : Base.BaseRegs) { in GenerateCombinations() local
3621 for (const SCEV *&BaseReg : F.BaseRegs) in GenerateTruncates() local
3787 const SCEV *BaseReg = F.BaseRegs[N]; in GenerateCrossUseConstantOffsets() local
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | Store.cpp | 274 const MemRegion *BaseReg = in evalDerivedToBase() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 40 unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonStoreWidening.cpp | 243 unsigned BaseReg = getBaseAddressRegister(BaseStore); in createStoreGroup() local
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