1 //===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H 17 18 #include "MCTargetDesc/MipsABIInfo.h" 19 #include "MCTargetDesc/MipsBaseInfo.h" 20 #include "Mips.h" 21 #include "llvm/CodeGen/CallingConvLower.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/IR/Function.h" 24 #include "llvm/Target/TargetLowering.h" 25 #include <deque> 26 #include <string> 27 28 namespace llvm { 29 namespace MipsISD { 30 enum NodeType : unsigned { 31 // Start the numbering from where ISD NodeType finishes. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 // Jump and link (call) 35 JmpLink, 36 37 // Tail call 38 TailCall, 39 40 // Get the Higher 16 bits from a 32-bit immediate 41 // No relation with Mips Hi register 42 Hi, 43 44 // Get the Lower 16 bits from a 32-bit immediate 45 // No relation with Mips Lo register 46 Lo, 47 48 // Handle gp_rel (small data/bss sections) relocation. 49 GPRel, 50 51 // Thread Pointer 52 ThreadPointer, 53 54 // Floating Point Branch Conditional 55 FPBrcond, 56 57 // Floating Point Compare 58 FPCmp, 59 60 // Floating Point Conditional Moves 61 CMovFP_T, 62 CMovFP_F, 63 64 // FP-to-int truncation node. 65 TruncIntFP, 66 67 // Return 68 Ret, 69 70 // Interrupt, exception, error trap Return 71 ERet, 72 73 // Software Exception Return. 74 EH_RETURN, 75 76 // Node used to extract integer from accumulator. 77 MFHI, 78 MFLO, 79 80 // Node used to insert integers to accumulator. 81 MTLOHI, 82 83 // Mult nodes. 84 Mult, 85 Multu, 86 87 // MAdd/Sub nodes 88 MAdd, 89 MAddu, 90 MSub, 91 MSubu, 92 93 // DivRem(u) 94 DivRem, 95 DivRemU, 96 DivRem16, 97 DivRemU16, 98 99 BuildPairF64, 100 ExtractElementF64, 101 102 Wrapper, 103 104 DynAlloc, 105 106 Sync, 107 108 Ext, 109 Ins, 110 111 // EXTR.W instrinsic nodes. 112 EXTP, 113 EXTPDP, 114 EXTR_S_H, 115 EXTR_W, 116 EXTR_R_W, 117 EXTR_RS_W, 118 SHILO, 119 MTHLIP, 120 121 // DPA.W intrinsic nodes. 122 MULSAQ_S_W_PH, 123 MAQ_S_W_PHL, 124 MAQ_S_W_PHR, 125 MAQ_SA_W_PHL, 126 MAQ_SA_W_PHR, 127 DPAU_H_QBL, 128 DPAU_H_QBR, 129 DPSU_H_QBL, 130 DPSU_H_QBR, 131 DPAQ_S_W_PH, 132 DPSQ_S_W_PH, 133 DPAQ_SA_L_W, 134 DPSQ_SA_L_W, 135 DPA_W_PH, 136 DPS_W_PH, 137 DPAQX_S_W_PH, 138 DPAQX_SA_W_PH, 139 DPAX_W_PH, 140 DPSX_W_PH, 141 DPSQX_S_W_PH, 142 DPSQX_SA_W_PH, 143 MULSA_W_PH, 144 145 MULT, 146 MULTU, 147 MADD_DSP, 148 MADDU_DSP, 149 MSUB_DSP, 150 MSUBU_DSP, 151 152 // DSP shift nodes. 153 SHLL_DSP, 154 SHRA_DSP, 155 SHRL_DSP, 156 157 // DSP setcc and select_cc nodes. 158 SETCC_DSP, 159 SELECT_CC_DSP, 160 161 // Vector comparisons. 162 // These take a vector and return a boolean. 163 VALL_ZERO, 164 VANY_ZERO, 165 VALL_NONZERO, 166 VANY_NONZERO, 167 168 // These take a vector and return a vector bitmask. 169 VCEQ, 170 VCLE_S, 171 VCLE_U, 172 VCLT_S, 173 VCLT_U, 174 175 // Element-wise vector max/min. 176 VSMAX, 177 VSMIN, 178 VUMAX, 179 VUMIN, 180 181 // Vector Shuffle with mask as an operand 182 VSHF, // Generic shuffle 183 SHF, // 4-element set shuffle. 184 ILVEV, // Interleave even elements 185 ILVOD, // Interleave odd elements 186 ILVL, // Interleave left elements 187 ILVR, // Interleave right elements 188 PCKEV, // Pack even elements 189 PCKOD, // Pack odd elements 190 191 // Vector Lane Copy 192 INSVE, // Copy element from one vector to another 193 194 // Combined (XOR (OR $a, $b), -1) 195 VNOR, 196 197 // Extended vector element extraction 198 VEXTRACT_SEXT_ELT, 199 VEXTRACT_ZEXT_ELT, 200 201 // Load/Store Left/Right nodes. 202 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE, 203 LWR, 204 SWL, 205 SWR, 206 LDL, 207 LDR, 208 SDL, 209 SDR 210 }; 211 } 212 213 //===--------------------------------------------------------------------===// 214 // TargetLowering Implementation 215 //===--------------------------------------------------------------------===// 216 class MipsFunctionInfo; 217 class MipsSubtarget; 218 class MipsCCState; 219 220 class MipsTargetLowering : public TargetLowering { 221 bool isMicroMips; 222 public: 223 explicit MipsTargetLowering(const MipsTargetMachine &TM, 224 const MipsSubtarget &STI); 225 226 static const MipsTargetLowering *create(const MipsTargetMachine &TM, 227 const MipsSubtarget &STI); 228 229 /// createFastISel - This method returns a target specific FastISel object, 230 /// or null if the target does not support "fast" ISel. 231 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 232 const TargetLibraryInfo *libInfo) const override; 233 getScalarShiftAmountTy(const DataLayout &,EVT)234 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 235 return MVT::i32; 236 } 237 238 bool isCheapToSpeculateCttz() const override; 239 bool isCheapToSpeculateCtlz() const override; 240 241 void LowerOperationWrapper(SDNode *N, 242 SmallVectorImpl<SDValue> &Results, 243 SelectionDAG &DAG) const override; 244 245 /// LowerOperation - Provide custom lowering hooks for some operations. 246 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 247 248 /// ReplaceNodeResults - Replace the results of node with an illegal result 249 /// type with new values built out of custom code. 250 /// 251 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 252 SelectionDAG &DAG) const override; 253 254 /// getTargetNodeName - This method returns the name of a target specific 255 // DAG node. 256 const char *getTargetNodeName(unsigned Opcode) const override; 257 258 /// getSetCCResultType - get the ISD::SETCC result ValueType 259 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 260 EVT VT) const override; 261 262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 263 264 MachineBasicBlock * 265 EmitInstrWithCustomInserter(MachineInstr *MI, 266 MachineBasicBlock *MBB) const override; 267 268 void HandleByVal(CCState *, unsigned &, unsigned) const override; 269 270 unsigned getRegisterByName(const char* RegName, EVT VT, 271 SelectionDAG &DAG) const override; 272 273 /// If a physical register, this returns the register that receives the 274 /// exception address on entry to an EH pad. 275 unsigned getExceptionPointerRegister(const Constant * PersonalityFn)276 getExceptionPointerRegister(const Constant *PersonalityFn) const override { 277 return ABI.IsN64() ? Mips::A0_64 : Mips::A0; 278 } 279 280 /// If a physical register, this returns the register that receives the 281 /// exception typeid on entry to a landing pad. 282 unsigned getExceptionSelectorRegister(const Constant * PersonalityFn)283 getExceptionSelectorRegister(const Constant *PersonalityFn) const override { 284 return ABI.IsN64() ? Mips::A1_64 : Mips::A1; 285 } 286 287 /// Returns true if a cast between SrcAS and DestAS is a noop. isNoopAddrSpaceCast(unsigned SrcAS,unsigned DestAS)288 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 289 // Mips doesn't have any special address spaces so we just reserve 290 // the first 256 for software use (e.g. OpenCL) and treat casts 291 // between them as noops. 292 return SrcAS < 256 && DestAS < 256; 293 } 294 295 protected: 296 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; 297 298 // This method creates the following nodes, which are necessary for 299 // computing a local symbol's address: 300 // 301 // (add (load (wrapper $gp, %got(sym)), %lo(sym)) 302 template <class NodeTy> getAddrLocal(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,bool IsN32OrN64)303 SDValue getAddrLocal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 304 bool IsN32OrN64) const { 305 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT; 306 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 307 getTargetNode(N, Ty, DAG, GOTFlag)); 308 SDValue Load = 309 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, 310 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 311 false, false, false, 0); 312 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO; 313 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, 314 getTargetNode(N, Ty, DAG, LoFlag)); 315 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); 316 } 317 318 // This method creates the following nodes, which are necessary for 319 // computing a global symbol's address: 320 // 321 // (load (wrapper $gp, %got(sym))) 322 template <class NodeTy> getAddrGlobal(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned Flag,SDValue Chain,const MachinePointerInfo & PtrInfo)323 SDValue getAddrGlobal(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG, 324 unsigned Flag, SDValue Chain, 325 const MachinePointerInfo &PtrInfo) const { 326 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), 327 getTargetNode(N, Ty, DAG, Flag)); 328 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo, false, false, false, 0); 329 } 330 331 // This method creates the following nodes, which are necessary for 332 // computing a global symbol's address in large-GOT mode: 333 // 334 // (load (wrapper (add %hi(sym), $gp), %lo(sym))) 335 template <class NodeTy> getAddrGlobalLargeGOT(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG,unsigned HiFlag,unsigned LoFlag,SDValue Chain,const MachinePointerInfo & PtrInfo)336 SDValue getAddrGlobalLargeGOT(NodeTy *N, SDLoc DL, EVT Ty, 337 SelectionDAG &DAG, unsigned HiFlag, 338 unsigned LoFlag, SDValue Chain, 339 const MachinePointerInfo &PtrInfo) const { 340 SDValue Hi = 341 DAG.getNode(MipsISD::Hi, DL, Ty, getTargetNode(N, Ty, DAG, HiFlag)); 342 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty)); 343 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi, 344 getTargetNode(N, Ty, DAG, LoFlag)); 345 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo, false, false, false, 346 0); 347 } 348 349 // This method creates the following nodes, which are necessary for 350 // computing a symbol's address in non-PIC mode: 351 // 352 // (add %hi(sym), %lo(sym)) 353 template <class NodeTy> getAddrNonPIC(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG)354 SDValue getAddrNonPIC(NodeTy *N, SDLoc DL, EVT Ty, 355 SelectionDAG &DAG) const { 356 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI); 357 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); 358 return DAG.getNode(ISD::ADD, DL, Ty, 359 DAG.getNode(MipsISD::Hi, DL, Ty, Hi), 360 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); 361 } 362 363 // This method creates the following nodes, which are necessary for 364 // computing a symbol's address using gp-relative addressing: 365 // 366 // (add $gp, %gp_rel(sym)) 367 template <class NodeTy> getAddrGPRel(NodeTy * N,SDLoc DL,EVT Ty,SelectionDAG & DAG)368 SDValue getAddrGPRel(NodeTy *N, SDLoc DL, EVT Ty, SelectionDAG &DAG) const { 369 assert(Ty == MVT::i32); 370 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); 371 return DAG.getNode(ISD::ADD, DL, Ty, 372 DAG.getRegister(Mips::GP, Ty), 373 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), 374 GPRel)); 375 } 376 377 /// This function fills Ops, which is the list of operands that will later 378 /// be used when a function call node is created. It also generates 379 /// copyToReg nodes to set up argument registers. 380 virtual void 381 getOpndList(SmallVectorImpl<SDValue> &Ops, 382 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 383 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 384 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 385 SDValue Chain) const; 386 387 protected: 388 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 389 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 390 391 // Subtarget Info 392 const MipsSubtarget &Subtarget; 393 // Cache the ABI from the TargetMachine, we use it everywhere. 394 const MipsABIInfo &ABI; 395 396 private: 397 // Create a TargetGlobalAddress node. 398 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 399 unsigned Flag) const; 400 401 // Create a TargetExternalSymbol node. 402 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG, 403 unsigned Flag) const; 404 405 // Create a TargetBlockAddress node. 406 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG, 407 unsigned Flag) const; 408 409 // Create a TargetJumpTable node. 410 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG, 411 unsigned Flag) const; 412 413 // Create a TargetConstantPool node. 414 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, 415 unsigned Flag) const; 416 417 // Lower Operand helpers 418 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 419 CallingConv::ID CallConv, bool isVarArg, 420 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, 421 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, 422 TargetLowering::CallLoweringInfo &CLI) const; 423 424 // Lower Operand specifics 425 SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 426 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 427 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 428 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 429 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 430 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 431 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 432 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const; 433 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 434 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; 435 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; 436 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; 437 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 438 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; 439 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 440 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 441 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 442 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const; 443 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const; 444 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG, 445 bool IsSRA) const; 446 SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const; 447 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 448 449 /// isEligibleForTailCallOptimization - Check whether the call is eligible 450 /// for tail call optimization. 451 virtual bool 452 isEligibleForTailCallOptimization(const CCState &CCInfo, 453 unsigned NextStackOffset, 454 const MipsFunctionInfo &FI) const = 0; 455 456 /// copyByValArg - Copy argument registers which were used to pass a byval 457 /// argument to the stack. Create a stack frame object for the byval 458 /// argument. 459 void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, 460 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, 461 SmallVectorImpl<SDValue> &InVals, 462 const Argument *FuncArg, unsigned FirstReg, 463 unsigned LastReg, const CCValAssign &VA, 464 MipsCCState &State) const; 465 466 /// passByValArg - Pass a byval argument in registers or on stack. 467 void passByValArg(SDValue Chain, SDLoc DL, 468 std::deque<std::pair<unsigned, SDValue>> &RegsToPass, 469 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, 470 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 471 unsigned FirstReg, unsigned LastReg, 472 const ISD::ArgFlagsTy &Flags, bool isLittle, 473 const CCValAssign &VA) const; 474 475 /// writeVarArgRegs - Write variable function arguments passed in registers 476 /// to the stack. Also create a stack frame object for the first variable 477 /// argument. 478 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, 479 SDLoc DL, SelectionDAG &DAG, CCState &State) const; 480 481 SDValue 482 LowerFormalArguments(SDValue Chain, 483 CallingConv::ID CallConv, bool isVarArg, 484 const SmallVectorImpl<ISD::InputArg> &Ins, 485 SDLoc dl, SelectionDAG &DAG, 486 SmallVectorImpl<SDValue> &InVals) const override; 487 488 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain, 489 SDValue Arg, SDLoc DL, bool IsTailCall, 490 SelectionDAG &DAG) const; 491 492 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, 493 SmallVectorImpl<SDValue> &InVals) const override; 494 495 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 496 bool isVarArg, 497 const SmallVectorImpl<ISD::OutputArg> &Outs, 498 LLVMContext &Context) const override; 499 500 SDValue LowerReturn(SDValue Chain, 501 CallingConv::ID CallConv, bool isVarArg, 502 const SmallVectorImpl<ISD::OutputArg> &Outs, 503 const SmallVectorImpl<SDValue> &OutVals, 504 SDLoc dl, SelectionDAG &DAG) const override; 505 506 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps, SDLoc DL, 507 SelectionDAG &DAG) const; 508 509 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override; 510 511 // Inline asm support 512 ConstraintType getConstraintType(StringRef Constraint) const override; 513 514 /// Examine constraint string and operand type and determine a weight value. 515 /// The operand object must already have been set up with the operand type. 516 ConstraintWeight getSingleConstraintMatchWeight( 517 AsmOperandInfo &info, const char *constraint) const override; 518 519 /// This function parses registers that appear in inline-asm constraints. 520 /// It returns pair (0, 0) on failure. 521 std::pair<unsigned, const TargetRegisterClass *> 522 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; 523 524 std::pair<unsigned, const TargetRegisterClass *> 525 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 526 StringRef Constraint, MVT VT) const override; 527 528 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 529 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 530 /// true it means one of the asm constraint of the inline asm instruction 531 /// being processed is 'm'. 532 void LowerAsmOperandForConstraint(SDValue Op, 533 std::string &Constraint, 534 std::vector<SDValue> &Ops, 535 SelectionDAG &DAG) const override; 536 537 unsigned getInlineAsmMemConstraint(StringRef ConstraintCode)538 getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 539 if (ConstraintCode == "R") 540 return InlineAsm::Constraint_R; 541 else if (ConstraintCode == "ZC") 542 return InlineAsm::Constraint_ZC; 543 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 544 } 545 546 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 547 Type *Ty, unsigned AS) const override; 548 549 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 550 551 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, 552 unsigned SrcAlign, 553 bool IsMemset, bool ZeroMemset, 554 bool MemcpyStrSrc, 555 MachineFunction &MF) const override; 556 557 /// isFPImmLegal - Returns true if the target can instruction select the 558 /// specified FP immediate natively. If false, the legalizer will 559 /// materialize the FP immediate as a load from a constant pool. 560 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 561 562 unsigned getJumpTableEncoding() const override; 563 bool useSoftFloat() const override; 564 565 /// Emit a sign-extension using sll/sra, seb, or seh appropriately. 566 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI, 567 MachineBasicBlock *BB, 568 unsigned Size, unsigned DstReg, 569 unsigned SrcRec) const; 570 571 MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 572 unsigned Size, unsigned BinOpcode, bool Nand = false) const; 573 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI, 574 MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, 575 bool Nand = false) const; 576 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI, 577 MachineBasicBlock *BB, unsigned Size) const; 578 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI, 579 MachineBasicBlock *BB, unsigned Size) const; 580 MachineBasicBlock *emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const; 581 MachineBasicBlock *emitPseudoSELECT(MachineInstr *MI, 582 MachineBasicBlock *BB, bool isFPCmp, 583 unsigned Opc) const; 584 }; 585 586 /// Create MipsTargetLowering objects. 587 const MipsTargetLowering * 588 createMips16TargetLowering(const MipsTargetMachine &TM, 589 const MipsSubtarget &STI); 590 const MipsTargetLowering * 591 createMipsSETargetLowering(const MipsTargetMachine &TM, 592 const MipsSubtarget &STI); 593 594 namespace Mips { 595 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 596 const TargetLibraryInfo *libInfo); 597 } 598 } 599 600 #endif 601