1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
17 
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 
21 #define GET_REGINFO_HEADER
22 #include "HexagonGenRegisterInfo.inc"
23 
24 //
25 //  We try not to hard code the reserved registers in our code,
26 //  so the following two macros were defined. However, there
27 //  are still a few places that R11 and R10 are hard wired.
28 //  See below. If, in the future, we decided to change the reserved
29 //  register. Don't forget changing the following places.
30 //
31 //  1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
32 //  2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
33 //  3. the definition of "IntRegs" in HexagonRegisterInfo.td
34 //  4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
35 //
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
38 
39 namespace llvm {
40 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
41 public:
42   HexagonRegisterInfo();
43 
44   /// Code Generation virtual methods...
45   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
46         const override;
47 
48 
49   BitVector getReservedRegs(const MachineFunction &MF) const override;
50 
51   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
52         unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
53 
54   /// Returns true since we may need scavenging for a temporary register
55   /// when generating hardware loop instructions.
requiresRegisterScavenging(const MachineFunction & MF)56   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
57     return true;
58   }
59 
60   /// Returns true. Spill code for predicate registers might need an extra
61   /// register.
requiresFrameIndexScavenging(const MachineFunction & MF)62   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
63     return true;
64   }
65 
66   /// Returns true if the frame pointer is valid.
67   bool useFPForScavengingIndex(const MachineFunction &MF) const override;
68 
trackLivenessAfterRegAlloc(const MachineFunction & MF)69   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
70     return true;
71   }
72 
73   // Debug information queries.
74   unsigned getRARegister() const;
75   unsigned getFrameRegister(const MachineFunction &MF) const override;
76   unsigned getFrameRegister() const;
77   unsigned getStackRegister() const;
78 
79   const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF) const;
80 
81   unsigned getFirstCallerSavedNonParamReg() const;
82 
83   bool isEHReturnCalleeSaveReg(unsigned Reg) const;
84   bool isCalleeSaveReg(unsigned Reg) const;
85 };
86 
87 } // end namespace llvm
88 
89 #endif
90