1 /* 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 */ 27 28 #ifndef _INTEL_CHIPSET_H 29 #define _INTEL_CHIPSET_H 30 31 #define PCI_CHIP_I810 0x7121 32 #define PCI_CHIP_I810_DC100 0x7123 33 #define PCI_CHIP_I810_E 0x7125 34 #define PCI_CHIP_I815 0x1132 35 36 #define PCI_CHIP_I830_M 0x3577 37 #define PCI_CHIP_845_G 0x2562 38 #define PCI_CHIP_I855_GM 0x3582 39 #define PCI_CHIP_I865_G 0x2572 40 41 #define PCI_CHIP_I915_G 0x2582 42 #define PCI_CHIP_E7221_G 0x258A 43 #define PCI_CHIP_I915_GM 0x2592 44 #define PCI_CHIP_I945_G 0x2772 45 #define PCI_CHIP_I945_GM 0x27A2 46 #define PCI_CHIP_I945_GME 0x27AE 47 48 #define PCI_CHIP_Q35_G 0x29B2 49 #define PCI_CHIP_G33_G 0x29C2 50 #define PCI_CHIP_Q33_G 0x29D2 51 52 #define PCI_CHIP_IGD_GM 0xA011 53 #define PCI_CHIP_IGD_G 0xA001 54 55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM) 56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G) 57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) 58 59 #define PCI_CHIP_I965_G 0x29A2 60 #define PCI_CHIP_I965_Q 0x2992 61 #define PCI_CHIP_I965_G_1 0x2982 62 #define PCI_CHIP_I946_GZ 0x2972 63 #define PCI_CHIP_I965_GM 0x2A02 64 #define PCI_CHIP_I965_GME 0x2A12 65 66 #define PCI_CHIP_GM45_GM 0x2A42 67 68 #define PCI_CHIP_IGD_E_G 0x2E02 69 #define PCI_CHIP_Q45_G 0x2E12 70 #define PCI_CHIP_G45_G 0x2E22 71 #define PCI_CHIP_G41_G 0x2E32 72 73 #define PCI_CHIP_ILD_G 0x0042 74 #define PCI_CHIP_ILM_G 0x0046 75 76 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */ 77 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 78 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 79 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */ 80 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 81 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 82 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */ 83 84 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */ 85 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 86 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */ 87 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 88 #define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */ 89 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */ 90 91 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ 92 #define PCI_CHIP_HASWELL_GT2 0x0412 93 #define PCI_CHIP_HASWELL_GT3 0x0422 94 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ 95 #define PCI_CHIP_HASWELL_M_GT2 0x0416 96 #define PCI_CHIP_HASWELL_M_GT3 0x0426 97 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ 98 #define PCI_CHIP_HASWELL_S_GT2 0x041A 99 #define PCI_CHIP_HASWELL_S_GT3 0x042A 100 #define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */ 101 #define PCI_CHIP_HASWELL_B_GT2 0x041B 102 #define PCI_CHIP_HASWELL_B_GT3 0x042B 103 #define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */ 104 #define PCI_CHIP_HASWELL_E_GT2 0x041E 105 #define PCI_CHIP_HASWELL_E_GT3 0x042E 106 #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ 107 #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 108 #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22 109 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ 110 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 111 #define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26 112 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ 113 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A 114 #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A 115 #define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */ 116 #define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B 117 #define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B 118 #define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */ 119 #define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E 120 #define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E 121 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ 122 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 123 #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22 124 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ 125 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 126 #define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26 127 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ 128 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A 129 #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A 130 #define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */ 131 #define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B 132 #define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B 133 #define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */ 134 #define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E 135 #define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E 136 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */ 137 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12 138 #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22 139 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */ 140 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16 141 #define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26 142 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */ 143 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A 144 #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A 145 #define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */ 146 #define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B 147 #define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B 148 #define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */ 149 #define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E 150 #define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E 151 #define BDW_SPARE 0x2 152 #define BDW_ULT 0x6 153 #define BDW_SERVER 0xa 154 #define BDW_IRIS 0xb 155 #define BDW_WORKSTATION 0xd 156 #define BDW_ULX 0xe 157 158 #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */ 159 #define PCI_CHIP_VALLEYVIEW_1 0x0f31 160 #define PCI_CHIP_VALLEYVIEW_2 0x0f32 161 #define PCI_CHIP_VALLEYVIEW_3 0x0f33 162 163 #define PCI_CHIP_CHERRYVIEW_0 0x22b0 164 #define PCI_CHIP_CHERRYVIEW_1 0x22b1 165 #define PCI_CHIP_CHERRYVIEW_2 0x22b2 166 #define PCI_CHIP_CHERRYVIEW_3 0x22b3 167 168 #define PCI_CHIP_SKYLAKE_DT_GT1 0x1902 169 #define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906 170 #define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A /* Reserved */ 171 #define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E /* Reserved */ 172 #define PCI_CHIP_SKYLAKE_DT_GT2 0x1912 173 #define PCI_CHIP_SKYLAKE_FUSED0_GT2 0x1913 /* Reserved */ 174 #define PCI_CHIP_SKYLAKE_FUSED1_GT2 0x1915 /* Reserved */ 175 #define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916 176 #define PCI_CHIP_SKYLAKE_FUSED2_GT2 0x1917 /* Reserved */ 177 #define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A /* Reserved */ 178 #define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B 179 #define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D 180 #define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E 181 #define PCI_CHIP_SKYLAKE_MOBILE_GT2 0x1921 /* Reserved */ 182 #define PCI_CHIP_SKYLAKE_GT3 0x1926 183 #define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B /* Reserved */ 184 #define PCI_CHIP_SKYLAKE_SRV_GT4 0x192A 185 #define PCI_CHIP_SKYLAKE_DT_GT4 0x1932 186 #define PCI_CHIP_SKYLAKE_SRV_GT4X 0x193A 187 #define PCI_CHIP_SKYLAKE_H_GT4 0x193B 188 #define PCI_CHIP_SKYLAKE_WKS_GT4 0x193D 189 190 #define PCI_CHIP_BROXTON_0 0x0A84 191 #define PCI_CHIP_BROXTON_1 0x1A84 192 #define PCI_CHIP_BROXTON_2 0x5A84 193 194 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ 195 (devid) == PCI_CHIP_I915_GM || \ 196 (devid) == PCI_CHIP_I945_GM || \ 197 (devid) == PCI_CHIP_I945_GME || \ 198 (devid) == PCI_CHIP_I965_GM || \ 199 (devid) == PCI_CHIP_I965_GME || \ 200 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \ 201 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ 202 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2) 203 204 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \ 205 (devid) == PCI_CHIP_Q45_G || \ 206 (devid) == PCI_CHIP_G45_G || \ 207 (devid) == PCI_CHIP_G41_G) 208 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM) 209 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) 210 211 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G) 212 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G) 213 214 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \ 215 (devid) == PCI_CHIP_E7221_G || \ 216 (devid) == PCI_CHIP_I915_GM) 217 218 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \ 219 (devid) == PCI_CHIP_I945_GME) 220 221 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \ 222 (devid) == PCI_CHIP_I945_GM || \ 223 (devid) == PCI_CHIP_I945_GME || \ 224 IS_G33(devid)) 225 226 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \ 227 (devid) == PCI_CHIP_Q33_G || \ 228 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid)) 229 230 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \ 231 (devid) == PCI_CHIP_845_G || \ 232 (devid) == PCI_CHIP_I855_GM || \ 233 (devid) == PCI_CHIP_I865_G) 234 235 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid)) 236 237 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \ 238 (devid) == PCI_CHIP_I965_Q || \ 239 (devid) == PCI_CHIP_I965_G_1 || \ 240 (devid) == PCI_CHIP_I965_GM || \ 241 (devid) == PCI_CHIP_I965_GME || \ 242 (devid) == PCI_CHIP_I946_GZ || \ 243 IS_G4X(devid)) 244 245 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) 246 247 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \ 248 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \ 249 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ 250 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ 251 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ 252 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \ 253 (devid) == PCI_CHIP_SANDYBRIDGE_S) 254 255 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ 256 IS_HASWELL(devid) || \ 257 IS_VALLEYVIEW(devid)) 258 259 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \ 260 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \ 261 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \ 262 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \ 263 (devid) == PCI_CHIP_IVYBRIDGE_S || \ 264 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2) 265 266 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \ 267 (devid) == PCI_CHIP_VALLEYVIEW_1 || \ 268 (devid) == PCI_CHIP_VALLEYVIEW_2 || \ 269 (devid) == PCI_CHIP_VALLEYVIEW_3) 270 271 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \ 272 (devid) == PCI_CHIP_HASWELL_M_GT1 || \ 273 (devid) == PCI_CHIP_HASWELL_S_GT1 || \ 274 (devid) == PCI_CHIP_HASWELL_B_GT1 || \ 275 (devid) == PCI_CHIP_HASWELL_E_GT1 || \ 276 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \ 277 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \ 278 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \ 279 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \ 280 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \ 281 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \ 282 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \ 283 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \ 284 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \ 285 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \ 286 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \ 287 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \ 288 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \ 289 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \ 290 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1) 291 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \ 292 (devid) == PCI_CHIP_HASWELL_M_GT2 || \ 293 (devid) == PCI_CHIP_HASWELL_S_GT2 || \ 294 (devid) == PCI_CHIP_HASWELL_B_GT2 || \ 295 (devid) == PCI_CHIP_HASWELL_E_GT2 || \ 296 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \ 297 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \ 298 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \ 299 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \ 300 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \ 301 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \ 302 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \ 303 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \ 304 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \ 305 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \ 306 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \ 307 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \ 308 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \ 309 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \ 310 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2) 311 #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \ 312 (devid) == PCI_CHIP_HASWELL_M_GT3 || \ 313 (devid) == PCI_CHIP_HASWELL_S_GT3 || \ 314 (devid) == PCI_CHIP_HASWELL_B_GT3 || \ 315 (devid) == PCI_CHIP_HASWELL_E_GT3 || \ 316 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \ 317 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \ 318 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \ 319 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \ 320 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \ 321 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \ 322 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \ 323 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \ 324 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \ 325 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \ 326 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \ 327 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \ 328 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \ 329 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \ 330 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3) 331 332 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ 333 IS_HSW_GT2(devid) || \ 334 IS_HSW_GT3(devid)) 335 336 #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \ 337 (((devid & 0x00f0) >> 4) > 3) ? 0 : \ 338 ((devid & 0x000f) == BDW_SPARE) ? 1 : \ 339 ((devid & 0x000f) == BDW_ULT) ? 1 : \ 340 ((devid & 0x000f) == BDW_IRIS) ? 1 : \ 341 ((devid & 0x000f) == BDW_SERVER) ? 1 : \ 342 ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \ 343 ((devid & 0x000f) == BDW_ULX) ? 1 : 0) 344 345 #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \ 346 (devid) == PCI_CHIP_CHERRYVIEW_1 || \ 347 (devid) == PCI_CHIP_CHERRYVIEW_2 || \ 348 (devid) == PCI_CHIP_CHERRYVIEW_3) 349 350 #define IS_GEN8(devid) (IS_BROADWELL(devid) || \ 351 IS_CHERRYVIEW(devid)) 352 353 #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \ 354 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \ 355 (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \ 356 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1) 357 358 #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \ 359 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \ 360 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \ 361 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \ 362 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \ 363 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \ 364 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \ 365 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \ 366 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \ 367 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2) 368 369 #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_GT3 || \ 370 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3) 371 372 #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \ 373 (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \ 374 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \ 375 (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \ 376 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4) 377 378 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \ 379 IS_SKL_GT2(devid) || \ 380 IS_SKL_GT3(devid) || \ 381 IS_SKL_GT4(devid)) 382 383 #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \ 384 (devid) == PCI_CHIP_BROXTON_1 || \ 385 (devid) == PCI_CHIP_BROXTON_2) 386 387 #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ 388 IS_BROXTON(devid)) 389 390 #define IS_9XX(dev) (IS_GEN3(dev) || \ 391 IS_GEN4(dev) || \ 392 IS_GEN5(dev) || \ 393 IS_GEN6(dev) || \ 394 IS_GEN7(dev) || \ 395 IS_GEN8(dev) || \ 396 IS_GEN9(dev)) 397 398 399 #endif /* _INTEL_CHIPSET_H */ 400