1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the SelectionDAG::Legalize method.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
38 using namespace llvm;
39 
40 #define DEBUG_TYPE "legalizedag"
41 
42 namespace {
43 
44 struct FloatSignAsInt;
45 
46 //===----------------------------------------------------------------------===//
47 /// This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it.  This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
52 ///
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing.  For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
57 ///
58 class SelectionDAGLegalize {
59   const TargetMachine &TM;
60   const TargetLowering &TLI;
61   SelectionDAG &DAG;
62 
63   /// \brief The set of nodes which have already been legalized. We hold a
64   /// reference to it in order to update as necessary on node deletion.
65   SmallPtrSetImpl<SDNode *> &LegalizedNodes;
66 
67   /// \brief A set of all the nodes updated during legalization.
68   SmallSetVector<SDNode *, 16> *UpdatedNodes;
69 
getSetCCResultType(EVT VT) const70   EVT getSetCCResultType(EVT VT) const {
71     return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
72   }
73 
74   // Libcall insertion helpers.
75 
76 public:
SelectionDAGLegalize(SelectionDAG & DAG,SmallPtrSetImpl<SDNode * > & LegalizedNodes,SmallSetVector<SDNode *,16> * UpdatedNodes=nullptr)77   SelectionDAGLegalize(SelectionDAG &DAG,
78                        SmallPtrSetImpl<SDNode *> &LegalizedNodes,
79                        SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
80       : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
81         LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
82 
83   /// \brief Legalizes the given operation.
84   void LegalizeOp(SDNode *Node);
85 
86 private:
87   SDValue OptimizeFloatStore(StoreSDNode *ST);
88 
89   void LegalizeLoadOps(SDNode *Node);
90   void LegalizeStoreOps(SDNode *Node);
91 
92   /// Some targets cannot handle a variable
93   /// insertion index for the INSERT_VECTOR_ELT instruction.  In this case, it
94   /// is necessary to spill the vector being inserted into to memory, perform
95   /// the insert there, and then read the result back.
96   SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
97                                          SDValue Idx, SDLoc dl);
98   SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
99                                   SDValue Idx, SDLoc dl);
100 
101   /// Return a vector shuffle operation which
102   /// performs the same shuffe in terms of order or result bytes, but on a type
103   /// whose vector element type is narrower than the original shuffle type.
104   /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
105   SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
106                                      SDValue N1, SDValue N2,
107                                      ArrayRef<int> Mask) const;
108 
109   bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
110                              bool &NeedInvert, SDLoc dl);
111 
112   SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
113   SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
114                         unsigned NumOps, bool isSigned, SDLoc dl);
115 
116   std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
117                                                  SDNode *Node, bool isSigned);
118   SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
119                           RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
120                           RTLIB::Libcall Call_F128,
121                           RTLIB::Libcall Call_PPCF128);
122   SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
123                            RTLIB::Libcall Call_I8,
124                            RTLIB::Libcall Call_I16,
125                            RTLIB::Libcall Call_I32,
126                            RTLIB::Libcall Call_I64,
127                            RTLIB::Libcall Call_I128);
128   void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
129   void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
130 
131   SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
132   SDValue ExpandBUILD_VECTOR(SDNode *Node);
133   SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
134   void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
135                                 SmallVectorImpl<SDValue> &Results);
136   void getSignAsIntValue(FloatSignAsInt &State, SDLoc DL, SDValue Value) const;
137   SDValue modifySignAsInt(const FloatSignAsInt &State, SDLoc DL,
138                           SDValue NewIntValue) const;
139   SDValue ExpandFCOPYSIGN(SDNode *Node) const;
140   SDValue ExpandFABS(SDNode *Node) const;
141   SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
142                                SDLoc dl);
143   SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
144                                 SDLoc dl);
145   SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
146                                 SDLoc dl);
147 
148   SDValue ExpandBITREVERSE(SDValue Op, SDLoc dl);
149   SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
150   SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
151 
152   SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
153   SDValue ExpandInsertToVectorThroughStack(SDValue Op);
154   SDValue ExpandVectorBuildThroughStack(SDNode* Node);
155 
156   SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
157   SDValue ExpandConstant(ConstantSDNode *CP);
158 
159   // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
160   bool ExpandNode(SDNode *Node);
161   void ConvertNodeToLibcall(SDNode *Node);
162   void PromoteNode(SDNode *Node);
163 
164 public:
165   // Node replacement helpers
ReplacedNode(SDNode * N)166   void ReplacedNode(SDNode *N) {
167     LegalizedNodes.erase(N);
168     if (UpdatedNodes)
169       UpdatedNodes->insert(N);
170   }
ReplaceNode(SDNode * Old,SDNode * New)171   void ReplaceNode(SDNode *Old, SDNode *New) {
172     DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
173           dbgs() << "     with:      "; New->dump(&DAG));
174 
175     assert(Old->getNumValues() == New->getNumValues() &&
176            "Replacing one node with another that produces a different number "
177            "of values!");
178     DAG.ReplaceAllUsesWith(Old, New);
179     for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
180       DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
181     if (UpdatedNodes)
182       UpdatedNodes->insert(New);
183     ReplacedNode(Old);
184   }
ReplaceNode(SDValue Old,SDValue New)185   void ReplaceNode(SDValue Old, SDValue New) {
186     DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
187           dbgs() << "     with:      "; New->dump(&DAG));
188 
189     DAG.ReplaceAllUsesWith(Old, New);
190     DAG.TransferDbgValues(Old, New);
191     if (UpdatedNodes)
192       UpdatedNodes->insert(New.getNode());
193     ReplacedNode(Old.getNode());
194   }
ReplaceNode(SDNode * Old,const SDValue * New)195   void ReplaceNode(SDNode *Old, const SDValue *New) {
196     DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
197 
198     DAG.ReplaceAllUsesWith(Old, New);
199     for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
200       DEBUG(dbgs() << (i == 0 ? "     with:      "
201                               : "      and:      ");
202             New[i]->dump(&DAG));
203       DAG.TransferDbgValues(SDValue(Old, i), New[i]);
204       if (UpdatedNodes)
205         UpdatedNodes->insert(New[i].getNode());
206     }
207     ReplacedNode(Old);
208   }
209 };
210 }
211 
212 /// Return a vector shuffle operation which
213 /// performs the same shuffe in terms of order or result bytes, but on a type
214 /// whose vector element type is narrower than the original shuffle type.
215 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
216 SDValue
ShuffleWithNarrowerEltType(EVT NVT,EVT VT,SDLoc dl,SDValue N1,SDValue N2,ArrayRef<int> Mask) const217 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT,  SDLoc dl,
218                                                  SDValue N1, SDValue N2,
219                                                  ArrayRef<int> Mask) const {
220   unsigned NumMaskElts = VT.getVectorNumElements();
221   unsigned NumDestElts = NVT.getVectorNumElements();
222   unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
223 
224   assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
225 
226   if (NumEltsGrowth == 1)
227     return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
228 
229   SmallVector<int, 8> NewMask;
230   for (unsigned i = 0; i != NumMaskElts; ++i) {
231     int Idx = Mask[i];
232     for (unsigned j = 0; j != NumEltsGrowth; ++j) {
233       if (Idx < 0)
234         NewMask.push_back(-1);
235       else
236         NewMask.push_back(Idx * NumEltsGrowth + j);
237     }
238   }
239   assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
240   assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
241   return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
242 }
243 
244 /// Expands the ConstantFP node to an integer constant or
245 /// a load from the constant pool.
246 SDValue
ExpandConstantFP(ConstantFPSDNode * CFP,bool UseCP)247 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
248   bool Extend = false;
249   SDLoc dl(CFP);
250 
251   // If a FP immediate is precise when represented as a float and if the
252   // target can do an extending load from float to double, we put it into
253   // the constant pool as a float, even if it's is statically typed as a
254   // double.  This shrinks FP constants and canonicalizes them for targets where
255   // an FP extending load is the same cost as a normal load (such as on the x87
256   // fp stack or PPC FP unit).
257   EVT VT = CFP->getValueType(0);
258   ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
259   if (!UseCP) {
260     assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
261     return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
262                            (VT == MVT::f64) ? MVT::i64 : MVT::i32);
263   }
264 
265   EVT OrigVT = VT;
266   EVT SVT = VT;
267   while (SVT != MVT::f32 && SVT != MVT::f16) {
268     SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
269     if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
270         // Only do this if the target has a native EXTLOAD instruction from
271         // smaller type.
272         TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
273         TLI.ShouldShrinkFPConstant(OrigVT)) {
274       Type *SType = SVT.getTypeForEVT(*DAG.getContext());
275       LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
276       VT = SVT;
277       Extend = true;
278     }
279   }
280 
281   SDValue CPIdx =
282       DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
283   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
284   if (Extend) {
285     SDValue Result = DAG.getExtLoad(
286         ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
287         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
288         false, false, false, Alignment);
289     return Result;
290   }
291   SDValue Result =
292       DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
293                   MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
294                   false, false, false, Alignment);
295   return Result;
296 }
297 
298 /// Expands the Constant node to a load from the constant pool.
ExpandConstant(ConstantSDNode * CP)299 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
300   SDLoc dl(CP);
301   EVT VT = CP->getValueType(0);
302   SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
303                                       TLI.getPointerTy(DAG.getDataLayout()));
304   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
305   SDValue Result =
306     DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
307                 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
308                 false, false, false, Alignment);
309   return Result;
310 }
311 
312 /// Expands an unaligned store to 2 half-size stores.
ExpandUnalignedStore(StoreSDNode * ST,SelectionDAG & DAG,const TargetLowering & TLI,SelectionDAGLegalize * DAGLegalize)313 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
314                                  const TargetLowering &TLI,
315                                  SelectionDAGLegalize *DAGLegalize) {
316   assert(ST->getAddressingMode() == ISD::UNINDEXED &&
317          "unaligned indexed stores not implemented!");
318   SDValue Chain = ST->getChain();
319   SDValue Ptr = ST->getBasePtr();
320   SDValue Val = ST->getValue();
321   EVT VT = Val.getValueType();
322   int Alignment = ST->getAlignment();
323   unsigned AS = ST->getAddressSpace();
324 
325   SDLoc dl(ST);
326   if (ST->getMemoryVT().isFloatingPoint() ||
327       ST->getMemoryVT().isVector()) {
328     EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
329     if (TLI.isTypeLegal(intVT)) {
330       // Expand to a bitconvert of the value to the integer type of the
331       // same size, then a (misaligned) int store.
332       // FIXME: Does not handle truncating floating point stores!
333       SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
334       Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
335                            ST->isVolatile(), ST->isNonTemporal(), Alignment);
336       DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
337       return;
338     }
339     // Do a (aligned) store to a stack slot, then copy from the stack slot
340     // to the final destination using (unaligned) integer loads and stores.
341     EVT StoredVT = ST->getMemoryVT();
342     MVT RegVT =
343       TLI.getRegisterType(*DAG.getContext(),
344                           EVT::getIntegerVT(*DAG.getContext(),
345                                             StoredVT.getSizeInBits()));
346     unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
347     unsigned RegBytes = RegVT.getSizeInBits() / 8;
348     unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
349 
350     // Make sure the stack slot is also aligned for the register type.
351     SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
352 
353     // Perform the original store, only redirected to the stack slot.
354     SDValue Store = DAG.getTruncStore(Chain, dl,
355                                       Val, StackPtr, MachinePointerInfo(),
356                                       StoredVT, false, false, 0);
357     SDValue Increment = DAG.getConstant(
358         RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
359     SmallVector<SDValue, 8> Stores;
360     unsigned Offset = 0;
361 
362     // Do all but one copies using the full register width.
363     for (unsigned i = 1; i < NumRegs; i++) {
364       // Load one integer register's worth from the stack slot.
365       SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
366                                  MachinePointerInfo(),
367                                  false, false, false, 0);
368       // Store it to the final location.  Remember the store.
369       Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
370                                   ST->getPointerInfo().getWithOffset(Offset),
371                                     ST->isVolatile(), ST->isNonTemporal(),
372                                     MinAlign(ST->getAlignment(), Offset)));
373       // Increment the pointers.
374       Offset += RegBytes;
375       StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
376                              Increment);
377       Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
378     }
379 
380     // The last store may be partial.  Do a truncating store.  On big-endian
381     // machines this requires an extending load from the stack slot to ensure
382     // that the bits are in the right place.
383     EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
384                                   8 * (StoredBytes - Offset));
385 
386     // Load from the stack slot.
387     SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
388                                   MachinePointerInfo(),
389                                   MemVT, false, false, false, 0);
390 
391     Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
392                                        ST->getPointerInfo()
393                                          .getWithOffset(Offset),
394                                        MemVT, ST->isVolatile(),
395                                        ST->isNonTemporal(),
396                                        MinAlign(ST->getAlignment(), Offset),
397                                        ST->getAAInfo()));
398     // The order of the stores doesn't matter - say it with a TokenFactor.
399     SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
400     DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
401     return;
402   }
403   assert(ST->getMemoryVT().isInteger() &&
404          !ST->getMemoryVT().isVector() &&
405          "Unaligned store of unknown type.");
406   // Get the half-size VT
407   EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
408   int NumBits = NewStoredVT.getSizeInBits();
409   int IncrementSize = NumBits / 8;
410 
411   // Divide the stored value in two parts.
412   SDValue ShiftAmount =
413       DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Val.getValueType(),
414                                                         DAG.getDataLayout()));
415   SDValue Lo = Val;
416   SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
417 
418   // Store the two parts
419   SDValue Store1, Store2;
420   Store1 = DAG.getTruncStore(Chain, dl,
421                              DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
422                              Ptr, ST->getPointerInfo(), NewStoredVT,
423                              ST->isVolatile(), ST->isNonTemporal(), Alignment);
424 
425   Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
426                     DAG.getConstant(IncrementSize, dl,
427                                     TLI.getPointerTy(DAG.getDataLayout(), AS)));
428   Alignment = MinAlign(Alignment, IncrementSize);
429   Store2 = DAG.getTruncStore(
430       Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
431       ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
432       ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
433 
434   SDValue Result =
435     DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
436   DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
437 }
438 
439 /// Expands an unaligned load to 2 half-size loads.
440 static void
ExpandUnalignedLoad(LoadSDNode * LD,SelectionDAG & DAG,const TargetLowering & TLI,SDValue & ValResult,SDValue & ChainResult)441 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
442                     const TargetLowering &TLI,
443                     SDValue &ValResult, SDValue &ChainResult) {
444   assert(LD->getAddressingMode() == ISD::UNINDEXED &&
445          "unaligned indexed loads not implemented!");
446   SDValue Chain = LD->getChain();
447   SDValue Ptr = LD->getBasePtr();
448   EVT VT = LD->getValueType(0);
449   EVT LoadedVT = LD->getMemoryVT();
450   SDLoc dl(LD);
451   if (VT.isFloatingPoint() || VT.isVector()) {
452     EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
453     if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
454       // Expand to a (misaligned) integer load of the same size,
455       // then bitconvert to floating point or vector.
456       SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
457                                     LD->getMemOperand());
458       SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
459       if (LoadedVT != VT)
460         Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
461                              ISD::ANY_EXTEND, dl, VT, Result);
462 
463       ValResult = Result;
464       ChainResult = newLoad.getValue(1);
465       return;
466     }
467 
468     // Copy the value to a (aligned) stack slot using (unaligned) integer
469     // loads and stores, then do a (aligned) load from the stack slot.
470     MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
471     unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
472     unsigned RegBytes = RegVT.getSizeInBits() / 8;
473     unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
474 
475     // Make sure the stack slot is also aligned for the register type.
476     SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
477 
478     SDValue Increment =
479         DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
480     SmallVector<SDValue, 8> Stores;
481     SDValue StackPtr = StackBase;
482     unsigned Offset = 0;
483 
484     // Do all but one copies using the full register width.
485     for (unsigned i = 1; i < NumRegs; i++) {
486       // Load one integer register's worth from the original location.
487       SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
488                                  LD->getPointerInfo().getWithOffset(Offset),
489                                  LD->isVolatile(), LD->isNonTemporal(),
490                                  LD->isInvariant(),
491                                  MinAlign(LD->getAlignment(), Offset),
492                                  LD->getAAInfo());
493       // Follow the load with a store to the stack slot.  Remember the store.
494       Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
495                                     MachinePointerInfo(), false, false, 0));
496       // Increment the pointers.
497       Offset += RegBytes;
498       Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
499       StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
500                              Increment);
501     }
502 
503     // The last copy may be partial.  Do an extending load.
504     EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
505                                   8 * (LoadedBytes - Offset));
506     SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
507                                   LD->getPointerInfo().getWithOffset(Offset),
508                                   MemVT, LD->isVolatile(),
509                                   LD->isNonTemporal(),
510                                   LD->isInvariant(),
511                                   MinAlign(LD->getAlignment(), Offset),
512                                   LD->getAAInfo());
513     // Follow the load with a store to the stack slot.  Remember the store.
514     // On big-endian machines this requires a truncating store to ensure
515     // that the bits end up in the right place.
516     Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
517                                        MachinePointerInfo(), MemVT,
518                                        false, false, 0));
519 
520     // The order of the stores doesn't matter - say it with a TokenFactor.
521     SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
522 
523     // Finally, perform the original load only redirected to the stack slot.
524     Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
525                           MachinePointerInfo(), LoadedVT, false,false, false,
526                           0);
527 
528     // Callers expect a MERGE_VALUES node.
529     ValResult = Load;
530     ChainResult = TF;
531     return;
532   }
533   assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
534          "Unaligned load of unsupported type.");
535 
536   // Compute the new VT that is half the size of the old one.  This is an
537   // integer MVT.
538   unsigned NumBits = LoadedVT.getSizeInBits();
539   EVT NewLoadedVT;
540   NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
541   NumBits >>= 1;
542 
543   unsigned Alignment = LD->getAlignment();
544   unsigned IncrementSize = NumBits / 8;
545   ISD::LoadExtType HiExtType = LD->getExtensionType();
546 
547   // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
548   if (HiExtType == ISD::NON_EXTLOAD)
549     HiExtType = ISD::ZEXTLOAD;
550 
551   // Load the value in two parts
552   SDValue Lo, Hi;
553   if (DAG.getDataLayout().isLittleEndian()) {
554     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
555                         NewLoadedVT, LD->isVolatile(),
556                         LD->isNonTemporal(), LD->isInvariant(), Alignment,
557                         LD->getAAInfo());
558     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
559                       DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
560     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
561                         LD->getPointerInfo().getWithOffset(IncrementSize),
562                         NewLoadedVT, LD->isVolatile(),
563                         LD->isNonTemporal(),LD->isInvariant(),
564                         MinAlign(Alignment, IncrementSize), LD->getAAInfo());
565   } else {
566     Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
567                         NewLoadedVT, LD->isVolatile(),
568                         LD->isNonTemporal(), LD->isInvariant(), Alignment,
569                         LD->getAAInfo());
570     Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
571                       DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
572     Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
573                         LD->getPointerInfo().getWithOffset(IncrementSize),
574                         NewLoadedVT, LD->isVolatile(),
575                         LD->isNonTemporal(), LD->isInvariant(),
576                         MinAlign(Alignment, IncrementSize), LD->getAAInfo());
577   }
578 
579   // aggregate the two parts
580   SDValue ShiftAmount =
581       DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
582                                                         DAG.getDataLayout()));
583   SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
584   Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
585 
586   SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
587                              Hi.getValue(1));
588 
589   ValResult = Result;
590   ChainResult = TF;
591 }
592 
593 /// Some target cannot handle a variable insertion index for the
594 /// INSERT_VECTOR_ELT instruction.  In this case, it
595 /// is necessary to spill the vector being inserted into to memory, perform
596 /// the insert there, and then read the result back.
597 SDValue SelectionDAGLegalize::
PerformInsertVectorEltInMemory(SDValue Vec,SDValue Val,SDValue Idx,SDLoc dl)598 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
599                                SDLoc dl) {
600   SDValue Tmp1 = Vec;
601   SDValue Tmp2 = Val;
602   SDValue Tmp3 = Idx;
603 
604   // If the target doesn't support this, we have to spill the input vector
605   // to a temporary stack slot, update the element, then reload it.  This is
606   // badness.  We could also load the value into a vector register (either
607   // with a "move to register" or "extload into register" instruction, then
608   // permute it into place, if the idx is a constant and if the idx is
609   // supported by the target.
610   EVT VT    = Tmp1.getValueType();
611   EVT EltVT = VT.getVectorElementType();
612   EVT IdxVT = Tmp3.getValueType();
613   EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
614   SDValue StackPtr = DAG.CreateStackTemporary(VT);
615 
616   int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
617 
618   // Store the vector.
619   SDValue Ch = DAG.getStore(
620       DAG.getEntryNode(), dl, Tmp1, StackPtr,
621       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
622       false, 0);
623 
624   // Truncate or zero extend offset to target pointer type.
625   Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
626   // Add the offset to the index.
627   unsigned EltSize = EltVT.getSizeInBits()/8;
628   Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
629                      DAG.getConstant(EltSize, dl, IdxVT));
630   SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
631   // Store the scalar value.
632   Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
633                          false, false, 0);
634   // Load the updated vector.
635   return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
636                                                DAG.getMachineFunction(), SPFI),
637                      false, false, false, 0);
638 }
639 
640 
641 SDValue SelectionDAGLegalize::
ExpandINSERT_VECTOR_ELT(SDValue Vec,SDValue Val,SDValue Idx,SDLoc dl)642 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
643   if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
644     // SCALAR_TO_VECTOR requires that the type of the value being inserted
645     // match the element type of the vector being created, except for
646     // integers in which case the inserted value can be over width.
647     EVT EltVT = Vec.getValueType().getVectorElementType();
648     if (Val.getValueType() == EltVT ||
649         (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
650       SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
651                                   Vec.getValueType(), Val);
652 
653       unsigned NumElts = Vec.getValueType().getVectorNumElements();
654       // We generate a shuffle of InVec and ScVec, so the shuffle mask
655       // should be 0,1,2,3,4,5... with the appropriate element replaced with
656       // elt 0 of the RHS.
657       SmallVector<int, 8> ShufOps;
658       for (unsigned i = 0; i != NumElts; ++i)
659         ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
660 
661       return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
662                                   &ShufOps[0]);
663     }
664   }
665   return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
666 }
667 
OptimizeFloatStore(StoreSDNode * ST)668 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
669   // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
670   // FIXME: We shouldn't do this for TargetConstantFP's.
671   // FIXME: move this to the DAG Combiner!  Note that we can't regress due
672   // to phase ordering between legalized code and the dag combiner.  This
673   // probably means that we need to integrate dag combiner and legalizer
674   // together.
675   // We generally can't do this one for long doubles.
676   SDValue Chain = ST->getChain();
677   SDValue Ptr = ST->getBasePtr();
678   unsigned Alignment = ST->getAlignment();
679   bool isVolatile = ST->isVolatile();
680   bool isNonTemporal = ST->isNonTemporal();
681   AAMDNodes AAInfo = ST->getAAInfo();
682   SDLoc dl(ST);
683   if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
684     if (CFP->getValueType(0) == MVT::f32 &&
685         TLI.isTypeLegal(MVT::i32)) {
686       SDValue Con = DAG.getConstant(CFP->getValueAPF().
687                                       bitcastToAPInt().zextOrTrunc(32),
688                                     SDLoc(CFP), MVT::i32);
689       return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
690                           isVolatile, isNonTemporal, Alignment, AAInfo);
691     }
692 
693     if (CFP->getValueType(0) == MVT::f64) {
694       // If this target supports 64-bit registers, do a single 64-bit store.
695       if (TLI.isTypeLegal(MVT::i64)) {
696         SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
697                                       zextOrTrunc(64), SDLoc(CFP), MVT::i64);
698         return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
699                             isVolatile, isNonTemporal, Alignment, AAInfo);
700       }
701 
702       if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
703         // Otherwise, if the target supports 32-bit registers, use 2 32-bit
704         // stores.  If the target supports neither 32- nor 64-bits, this
705         // xform is certainly not worth it.
706         const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
707         SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
708         SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
709         if (DAG.getDataLayout().isBigEndian())
710           std::swap(Lo, Hi);
711 
712         Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
713                           isNonTemporal, Alignment, AAInfo);
714         Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
715                           DAG.getConstant(4, dl, Ptr.getValueType()));
716         Hi = DAG.getStore(Chain, dl, Hi, Ptr,
717                           ST->getPointerInfo().getWithOffset(4),
718                           isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
719                           AAInfo);
720 
721         return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
722       }
723     }
724   }
725   return SDValue(nullptr, 0);
726 }
727 
LegalizeStoreOps(SDNode * Node)728 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
729     StoreSDNode *ST = cast<StoreSDNode>(Node);
730     SDValue Chain = ST->getChain();
731     SDValue Ptr = ST->getBasePtr();
732     SDLoc dl(Node);
733 
734     unsigned Alignment = ST->getAlignment();
735     bool isVolatile = ST->isVolatile();
736     bool isNonTemporal = ST->isNonTemporal();
737     AAMDNodes AAInfo = ST->getAAInfo();
738 
739     if (!ST->isTruncatingStore()) {
740       if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
741         ReplaceNode(ST, OptStore);
742         return;
743       }
744 
745       {
746         SDValue Value = ST->getValue();
747         MVT VT = Value.getSimpleValueType();
748         switch (TLI.getOperationAction(ISD::STORE, VT)) {
749         default: llvm_unreachable("This action is not supported yet!");
750         case TargetLowering::Legal: {
751           // If this is an unaligned store and the target doesn't support it,
752           // expand it.
753           EVT MemVT = ST->getMemoryVT();
754           unsigned AS = ST->getAddressSpace();
755           unsigned Align = ST->getAlignment();
756           const DataLayout &DL = DAG.getDataLayout();
757           if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
758             ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
759           break;
760         }
761         case TargetLowering::Custom: {
762           SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
763           if (Res && Res != SDValue(Node, 0))
764             ReplaceNode(SDValue(Node, 0), Res);
765           return;
766         }
767         case TargetLowering::Promote: {
768           MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
769           assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
770                  "Can only promote stores to same size type");
771           Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
772           SDValue Result =
773             DAG.getStore(Chain, dl, Value, Ptr,
774                          ST->getPointerInfo(), isVolatile,
775                          isNonTemporal, Alignment, AAInfo);
776           ReplaceNode(SDValue(Node, 0), Result);
777           break;
778         }
779         }
780         return;
781       }
782     } else {
783       SDValue Value = ST->getValue();
784 
785       EVT StVT = ST->getMemoryVT();
786       unsigned StWidth = StVT.getSizeInBits();
787       auto &DL = DAG.getDataLayout();
788 
789       if (StWidth != StVT.getStoreSizeInBits()) {
790         // Promote to a byte-sized store with upper bits zero if not
791         // storing an integral number of bytes.  For example, promote
792         // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
793         EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
794                                     StVT.getStoreSizeInBits());
795         Value = DAG.getZeroExtendInReg(Value, dl, StVT);
796         SDValue Result =
797           DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
798                             NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
799         ReplaceNode(SDValue(Node, 0), Result);
800       } else if (StWidth & (StWidth - 1)) {
801         // If not storing a power-of-2 number of bits, expand as two stores.
802         assert(!StVT.isVector() && "Unsupported truncstore!");
803         unsigned RoundWidth = 1 << Log2_32(StWidth);
804         assert(RoundWidth < StWidth);
805         unsigned ExtraWidth = StWidth - RoundWidth;
806         assert(ExtraWidth < RoundWidth);
807         assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
808                "Store size not an integral number of bytes!");
809         EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
810         EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
811         SDValue Lo, Hi;
812         unsigned IncrementSize;
813 
814         if (DL.isLittleEndian()) {
815           // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
816           // Store the bottom RoundWidth bits.
817           Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
818                                  RoundVT,
819                                  isVolatile, isNonTemporal, Alignment,
820                                  AAInfo);
821 
822           // Store the remaining ExtraWidth bits.
823           IncrementSize = RoundWidth / 8;
824           Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
825                             DAG.getConstant(IncrementSize, dl,
826                                             Ptr.getValueType()));
827           Hi = DAG.getNode(
828               ISD::SRL, dl, Value.getValueType(), Value,
829               DAG.getConstant(RoundWidth, dl,
830                               TLI.getShiftAmountTy(Value.getValueType(), DL)));
831           Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
832                              ST->getPointerInfo().getWithOffset(IncrementSize),
833                                  ExtraVT, isVolatile, isNonTemporal,
834                                  MinAlign(Alignment, IncrementSize), AAInfo);
835         } else {
836           // Big endian - avoid unaligned stores.
837           // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
838           // Store the top RoundWidth bits.
839           Hi = DAG.getNode(
840               ISD::SRL, dl, Value.getValueType(), Value,
841               DAG.getConstant(ExtraWidth, dl,
842                               TLI.getShiftAmountTy(Value.getValueType(), DL)));
843           Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
844                                  RoundVT, isVolatile, isNonTemporal, Alignment,
845                                  AAInfo);
846 
847           // Store the remaining ExtraWidth bits.
848           IncrementSize = RoundWidth / 8;
849           Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
850                             DAG.getConstant(IncrementSize, dl,
851                                             Ptr.getValueType()));
852           Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
853                               ST->getPointerInfo().getWithOffset(IncrementSize),
854                                  ExtraVT, isVolatile, isNonTemporal,
855                                  MinAlign(Alignment, IncrementSize), AAInfo);
856         }
857 
858         // The order of the stores doesn't matter.
859         SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
860         ReplaceNode(SDValue(Node, 0), Result);
861       } else {
862         switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
863         default: llvm_unreachable("This action is not supported yet!");
864         case TargetLowering::Legal: {
865           EVT MemVT = ST->getMemoryVT();
866           unsigned AS = ST->getAddressSpace();
867           unsigned Align = ST->getAlignment();
868           // If this is an unaligned store and the target doesn't support it,
869           // expand it.
870           if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
871             ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
872           break;
873         }
874         case TargetLowering::Custom: {
875           SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
876           if (Res && Res != SDValue(Node, 0))
877             ReplaceNode(SDValue(Node, 0), Res);
878           return;
879         }
880         case TargetLowering::Expand:
881           assert(!StVT.isVector() &&
882                  "Vector Stores are handled in LegalizeVectorOps");
883 
884           // TRUNCSTORE:i16 i32 -> STORE i16
885           assert(TLI.isTypeLegal(StVT) &&
886                  "Do not know how to expand this store!");
887           Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
888           SDValue Result =
889             DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
890                          isVolatile, isNonTemporal, Alignment, AAInfo);
891           ReplaceNode(SDValue(Node, 0), Result);
892           break;
893         }
894       }
895     }
896 }
897 
LegalizeLoadOps(SDNode * Node)898 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
899   LoadSDNode *LD = cast<LoadSDNode>(Node);
900   SDValue Chain = LD->getChain();  // The chain.
901   SDValue Ptr = LD->getBasePtr();  // The base pointer.
902   SDValue Value;                   // The value returned by the load op.
903   SDLoc dl(Node);
904 
905   ISD::LoadExtType ExtType = LD->getExtensionType();
906   if (ExtType == ISD::NON_EXTLOAD) {
907     MVT VT = Node->getSimpleValueType(0);
908     SDValue RVal = SDValue(Node, 0);
909     SDValue RChain = SDValue(Node, 1);
910 
911     switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
912     default: llvm_unreachable("This action is not supported yet!");
913     case TargetLowering::Legal: {
914       EVT MemVT = LD->getMemoryVT();
915       unsigned AS = LD->getAddressSpace();
916       unsigned Align = LD->getAlignment();
917       const DataLayout &DL = DAG.getDataLayout();
918       // If this is an unaligned load and the target doesn't support it,
919       // expand it.
920       if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
921         ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
922       break;
923     }
924     case TargetLowering::Custom: {
925       SDValue Res = TLI.LowerOperation(RVal, DAG);
926       if (Res.getNode()) {
927         RVal = Res;
928         RChain = Res.getValue(1);
929       }
930       break;
931     }
932     case TargetLowering::Promote: {
933       MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
934       assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
935              "Can only promote loads to same size type");
936 
937       SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
938       RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
939       RChain = Res.getValue(1);
940       break;
941     }
942     }
943     if (RChain.getNode() != Node) {
944       assert(RVal.getNode() != Node && "Load must be completely replaced");
945       DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
946       DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
947       if (UpdatedNodes) {
948         UpdatedNodes->insert(RVal.getNode());
949         UpdatedNodes->insert(RChain.getNode());
950       }
951       ReplacedNode(Node);
952     }
953     return;
954   }
955 
956   EVT SrcVT = LD->getMemoryVT();
957   unsigned SrcWidth = SrcVT.getSizeInBits();
958   unsigned Alignment = LD->getAlignment();
959   bool isVolatile = LD->isVolatile();
960   bool isNonTemporal = LD->isNonTemporal();
961   bool isInvariant = LD->isInvariant();
962   AAMDNodes AAInfo = LD->getAAInfo();
963 
964   if (SrcWidth != SrcVT.getStoreSizeInBits() &&
965       // Some targets pretend to have an i1 loading operation, and actually
966       // load an i8.  This trick is correct for ZEXTLOAD because the top 7
967       // bits are guaranteed to be zero; it helps the optimizers understand
968       // that these bits are zero.  It is also useful for EXTLOAD, since it
969       // tells the optimizers that those bits are undefined.  It would be
970       // nice to have an effective generic way of getting these benefits...
971       // Until such a way is found, don't insist on promoting i1 here.
972       (SrcVT != MVT::i1 ||
973        TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
974          TargetLowering::Promote)) {
975     // Promote to a byte-sized load if not loading an integral number of
976     // bytes.  For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
977     unsigned NewWidth = SrcVT.getStoreSizeInBits();
978     EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
979     SDValue Ch;
980 
981     // The extra bits are guaranteed to be zero, since we stored them that
982     // way.  A zext load from NVT thus automatically gives zext from SrcVT.
983 
984     ISD::LoadExtType NewExtType =
985       ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
986 
987     SDValue Result =
988       DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
989                      Chain, Ptr, LD->getPointerInfo(),
990                      NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
991                      AAInfo);
992 
993     Ch = Result.getValue(1); // The chain.
994 
995     if (ExtType == ISD::SEXTLOAD)
996       // Having the top bits zero doesn't help when sign extending.
997       Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
998                            Result.getValueType(),
999                            Result, DAG.getValueType(SrcVT));
1000     else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1001       // All the top bits are guaranteed to be zero - inform the optimizers.
1002       Result = DAG.getNode(ISD::AssertZext, dl,
1003                            Result.getValueType(), Result,
1004                            DAG.getValueType(SrcVT));
1005 
1006     Value = Result;
1007     Chain = Ch;
1008   } else if (SrcWidth & (SrcWidth - 1)) {
1009     // If not loading a power-of-2 number of bits, expand as two loads.
1010     assert(!SrcVT.isVector() && "Unsupported extload!");
1011     unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1012     assert(RoundWidth < SrcWidth);
1013     unsigned ExtraWidth = SrcWidth - RoundWidth;
1014     assert(ExtraWidth < RoundWidth);
1015     assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1016            "Load size not an integral number of bytes!");
1017     EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1018     EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1019     SDValue Lo, Hi, Ch;
1020     unsigned IncrementSize;
1021     auto &DL = DAG.getDataLayout();
1022 
1023     if (DL.isLittleEndian()) {
1024       // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1025       // Load the bottom RoundWidth bits.
1026       Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1027                           Chain, Ptr,
1028                           LD->getPointerInfo(), RoundVT, isVolatile,
1029                           isNonTemporal, isInvariant, Alignment, AAInfo);
1030 
1031       // Load the remaining ExtraWidth bits.
1032       IncrementSize = RoundWidth / 8;
1033       Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1034                          DAG.getConstant(IncrementSize, dl,
1035                                          Ptr.getValueType()));
1036       Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037                           LD->getPointerInfo().getWithOffset(IncrementSize),
1038                           ExtraVT, isVolatile, isNonTemporal, isInvariant,
1039                           MinAlign(Alignment, IncrementSize), AAInfo);
1040 
1041       // Build a factor node to remember that this load is independent of
1042       // the other one.
1043       Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1044                        Hi.getValue(1));
1045 
1046       // Move the top bits to the right place.
1047       Hi = DAG.getNode(
1048           ISD::SHL, dl, Hi.getValueType(), Hi,
1049           DAG.getConstant(RoundWidth, dl,
1050                           TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1051 
1052       // Join the hi and lo parts.
1053       Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1054     } else {
1055       // Big endian - avoid unaligned loads.
1056       // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1057       // Load the top RoundWidth bits.
1058       Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1059                           LD->getPointerInfo(), RoundVT, isVolatile,
1060                           isNonTemporal, isInvariant, Alignment, AAInfo);
1061 
1062       // Load the remaining ExtraWidth bits.
1063       IncrementSize = RoundWidth / 8;
1064       Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1065                          DAG.getConstant(IncrementSize, dl,
1066                                          Ptr.getValueType()));
1067       Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1068                           dl, Node->getValueType(0), Chain, Ptr,
1069                           LD->getPointerInfo().getWithOffset(IncrementSize),
1070                           ExtraVT, isVolatile, isNonTemporal, isInvariant,
1071                           MinAlign(Alignment, IncrementSize), AAInfo);
1072 
1073       // Build a factor node to remember that this load is independent of
1074       // the other one.
1075       Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1076                        Hi.getValue(1));
1077 
1078       // Move the top bits to the right place.
1079       Hi = DAG.getNode(
1080           ISD::SHL, dl, Hi.getValueType(), Hi,
1081           DAG.getConstant(ExtraWidth, dl,
1082                           TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1083 
1084       // Join the hi and lo parts.
1085       Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1086     }
1087 
1088     Chain = Ch;
1089   } else {
1090     bool isCustom = false;
1091     switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1092                                  SrcVT.getSimpleVT())) {
1093     default: llvm_unreachable("This action is not supported yet!");
1094     case TargetLowering::Custom:
1095       isCustom = true;
1096       // FALLTHROUGH
1097     case TargetLowering::Legal: {
1098       Value = SDValue(Node, 0);
1099       Chain = SDValue(Node, 1);
1100 
1101       if (isCustom) {
1102         SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1103         if (Res.getNode()) {
1104           Value = Res;
1105           Chain = Res.getValue(1);
1106         }
1107       } else {
1108         // If this is an unaligned load and the target doesn't support it,
1109         // expand it.
1110         EVT MemVT = LD->getMemoryVT();
1111         unsigned AS = LD->getAddressSpace();
1112         unsigned Align = LD->getAlignment();
1113         const DataLayout &DL = DAG.getDataLayout();
1114         if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
1115           ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1116       }
1117       break;
1118     }
1119     case TargetLowering::Expand:
1120       EVT DestVT = Node->getValueType(0);
1121       if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
1122         // If the source type is not legal, see if there is a legal extload to
1123         // an intermediate type that we can then extend further.
1124         EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1125         if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1126             TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1127           // If we are loading a legal type, this is a non-extload followed by a
1128           // full extend.
1129           ISD::LoadExtType MidExtType =
1130               (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1131 
1132           SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1133                                         SrcVT, LD->getMemOperand());
1134           unsigned ExtendOp =
1135               ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1136           Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1137           Chain = Load.getValue(1);
1138           break;
1139         }
1140 
1141         // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
1142         // normal undefined upper bits behavior to allow using an in-reg extend
1143         // with the illegal FP type, so load as an integer and do the
1144         // from-integer conversion.
1145         if (SrcVT.getScalarType() == MVT::f16) {
1146           EVT ISrcVT = SrcVT.changeTypeToInteger();
1147           EVT IDestVT = DestVT.changeTypeToInteger();
1148           EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
1149 
1150           SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
1151                                           Chain, Ptr, ISrcVT,
1152                                           LD->getMemOperand());
1153           Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1154           Chain = Result.getValue(1);
1155           break;
1156         }
1157       }
1158 
1159       assert(!SrcVT.isVector() &&
1160              "Vector Loads are handled in LegalizeVectorOps");
1161 
1162       // FIXME: This does not work for vectors on most targets.  Sign-
1163       // and zero-extend operations are currently folded into extending
1164       // loads, whether they are legal or not, and then we end up here
1165       // without any support for legalizing them.
1166       assert(ExtType != ISD::EXTLOAD &&
1167              "EXTLOAD should always be supported!");
1168       // Turn the unsupported load into an EXTLOAD followed by an
1169       // explicit zero/sign extend inreg.
1170       SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1171                                       Node->getValueType(0),
1172                                       Chain, Ptr, SrcVT,
1173                                       LD->getMemOperand());
1174       SDValue ValRes;
1175       if (ExtType == ISD::SEXTLOAD)
1176         ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1177                              Result.getValueType(),
1178                              Result, DAG.getValueType(SrcVT));
1179       else
1180         ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1181       Value = ValRes;
1182       Chain = Result.getValue(1);
1183       break;
1184     }
1185   }
1186 
1187   // Since loads produce two values, make sure to remember that we legalized
1188   // both of them.
1189   if (Chain.getNode() != Node) {
1190     assert(Value.getNode() != Node && "Load must be completely replaced");
1191     DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1192     DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1193     if (UpdatedNodes) {
1194       UpdatedNodes->insert(Value.getNode());
1195       UpdatedNodes->insert(Chain.getNode());
1196     }
1197     ReplacedNode(Node);
1198   }
1199 }
1200 
1201 /// Return a legal replacement for the given operation, with all legal operands.
LegalizeOp(SDNode * Node)1202 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1203   DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1204 
1205   if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1206     return;
1207 
1208 #ifndef NDEBUG
1209   for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1210     assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1211               TargetLowering::TypeLegal ||
1212             TLI.isTypeLegal(Node->getValueType(i))) &&
1213            "Unexpected illegal type!");
1214 
1215   for (const SDValue &Op : Node->op_values())
1216     assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
1217               TargetLowering::TypeLegal ||
1218             TLI.isTypeLegal(Op.getValueType()) ||
1219             Op.getOpcode() == ISD::TargetConstant) &&
1220             "Unexpected illegal type!");
1221 #endif
1222 
1223   // Figure out the correct action; the way to query this varies by opcode
1224   TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1225   bool SimpleFinishLegalizing = true;
1226   switch (Node->getOpcode()) {
1227   case ISD::INTRINSIC_W_CHAIN:
1228   case ISD::INTRINSIC_WO_CHAIN:
1229   case ISD::INTRINSIC_VOID:
1230   case ISD::STACKSAVE:
1231     Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1232     break;
1233   case ISD::GET_DYNAMIC_AREA_OFFSET:
1234     Action = TLI.getOperationAction(Node->getOpcode(),
1235                                     Node->getValueType(0));
1236     break;
1237   case ISD::VAARG:
1238     Action = TLI.getOperationAction(Node->getOpcode(),
1239                                     Node->getValueType(0));
1240     if (Action != TargetLowering::Promote)
1241       Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1242     break;
1243   case ISD::FP_TO_FP16:
1244   case ISD::SINT_TO_FP:
1245   case ISD::UINT_TO_FP:
1246   case ISD::EXTRACT_VECTOR_ELT:
1247     Action = TLI.getOperationAction(Node->getOpcode(),
1248                                     Node->getOperand(0).getValueType());
1249     break;
1250   case ISD::FP_ROUND_INREG:
1251   case ISD::SIGN_EXTEND_INREG: {
1252     EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1253     Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1254     break;
1255   }
1256   case ISD::ATOMIC_STORE: {
1257     Action = TLI.getOperationAction(Node->getOpcode(),
1258                                     Node->getOperand(2).getValueType());
1259     break;
1260   }
1261   case ISD::SELECT_CC:
1262   case ISD::SETCC:
1263   case ISD::BR_CC: {
1264     unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1265                          Node->getOpcode() == ISD::SETCC ? 2 :
1266                          Node->getOpcode() == ISD::SETCCE ? 3 : 1;
1267     unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1268     MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1269     ISD::CondCode CCCode =
1270         cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1271     Action = TLI.getCondCodeAction(CCCode, OpVT);
1272     if (Action == TargetLowering::Legal) {
1273       if (Node->getOpcode() == ISD::SELECT_CC)
1274         Action = TLI.getOperationAction(Node->getOpcode(),
1275                                         Node->getValueType(0));
1276       else
1277         Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1278     }
1279     break;
1280   }
1281   case ISD::LOAD:
1282   case ISD::STORE:
1283     // FIXME: Model these properly.  LOAD and STORE are complicated, and
1284     // STORE expects the unlegalized operand in some cases.
1285     SimpleFinishLegalizing = false;
1286     break;
1287   case ISD::CALLSEQ_START:
1288   case ISD::CALLSEQ_END:
1289     // FIXME: This shouldn't be necessary.  These nodes have special properties
1290     // dealing with the recursive nature of legalization.  Removing this
1291     // special case should be done as part of making LegalizeDAG non-recursive.
1292     SimpleFinishLegalizing = false;
1293     break;
1294   case ISD::EXTRACT_ELEMENT:
1295   case ISD::FLT_ROUNDS_:
1296   case ISD::FPOWI:
1297   case ISD::MERGE_VALUES:
1298   case ISD::EH_RETURN:
1299   case ISD::FRAME_TO_ARGS_OFFSET:
1300   case ISD::EH_SJLJ_SETJMP:
1301   case ISD::EH_SJLJ_LONGJMP:
1302   case ISD::EH_SJLJ_SETUP_DISPATCH:
1303     // These operations lie about being legal: when they claim to be legal,
1304     // they should actually be expanded.
1305     Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1306     if (Action == TargetLowering::Legal)
1307       Action = TargetLowering::Expand;
1308     break;
1309   case ISD::INIT_TRAMPOLINE:
1310   case ISD::ADJUST_TRAMPOLINE:
1311   case ISD::FRAMEADDR:
1312   case ISD::RETURNADDR:
1313     // These operations lie about being legal: when they claim to be legal,
1314     // they should actually be custom-lowered.
1315     Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1316     if (Action == TargetLowering::Legal)
1317       Action = TargetLowering::Custom;
1318     break;
1319   case ISD::READCYCLECOUNTER:
1320     // READCYCLECOUNTER returns an i64, even if type legalization might have
1321     // expanded that to several smaller types.
1322     Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1323     break;
1324   case ISD::READ_REGISTER:
1325   case ISD::WRITE_REGISTER:
1326     // Named register is legal in the DAG, but blocked by register name
1327     // selection if not implemented by target (to chose the correct register)
1328     // They'll be converted to Copy(To/From)Reg.
1329     Action = TargetLowering::Legal;
1330     break;
1331   case ISD::DEBUGTRAP:
1332     Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1333     if (Action == TargetLowering::Expand) {
1334       // replace ISD::DEBUGTRAP with ISD::TRAP
1335       SDValue NewVal;
1336       NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1337                            Node->getOperand(0));
1338       ReplaceNode(Node, NewVal.getNode());
1339       LegalizeOp(NewVal.getNode());
1340       return;
1341     }
1342     break;
1343 
1344   default:
1345     if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1346       Action = TargetLowering::Legal;
1347     } else {
1348       Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1349     }
1350     break;
1351   }
1352 
1353   if (SimpleFinishLegalizing) {
1354     SDNode *NewNode = Node;
1355     switch (Node->getOpcode()) {
1356     default: break;
1357     case ISD::SHL:
1358     case ISD::SRL:
1359     case ISD::SRA:
1360     case ISD::ROTL:
1361     case ISD::ROTR:
1362       // Legalizing shifts/rotates requires adjusting the shift amount
1363       // to the appropriate width.
1364       if (!Node->getOperand(1).getValueType().isVector()) {
1365         SDValue SAO =
1366           DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1367                                     Node->getOperand(1));
1368         HandleSDNode Handle(SAO);
1369         LegalizeOp(SAO.getNode());
1370         NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1371                                          Handle.getValue());
1372       }
1373       break;
1374     case ISD::SRL_PARTS:
1375     case ISD::SRA_PARTS:
1376     case ISD::SHL_PARTS:
1377       // Legalizing shifts/rotates requires adjusting the shift amount
1378       // to the appropriate width.
1379       if (!Node->getOperand(2).getValueType().isVector()) {
1380         SDValue SAO =
1381           DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1382                                     Node->getOperand(2));
1383         HandleSDNode Handle(SAO);
1384         LegalizeOp(SAO.getNode());
1385         NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1386                                          Node->getOperand(1),
1387                                          Handle.getValue());
1388       }
1389       break;
1390     }
1391 
1392     if (NewNode != Node) {
1393       ReplaceNode(Node, NewNode);
1394       Node = NewNode;
1395     }
1396     switch (Action) {
1397     case TargetLowering::Legal:
1398       return;
1399     case TargetLowering::Custom: {
1400       // FIXME: The handling for custom lowering with multiple results is
1401       // a complete mess.
1402       SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1403       if (Res.getNode()) {
1404         if (!(Res.getNode() != Node || Res.getResNo() != 0))
1405           return;
1406 
1407         if (Node->getNumValues() == 1) {
1408           // We can just directly replace this node with the lowered value.
1409           ReplaceNode(SDValue(Node, 0), Res);
1410           return;
1411         }
1412 
1413         SmallVector<SDValue, 8> ResultVals;
1414         for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1415           ResultVals.push_back(Res.getValue(i));
1416         ReplaceNode(Node, ResultVals.data());
1417         return;
1418       }
1419     }
1420       // FALL THROUGH
1421     case TargetLowering::Expand:
1422       if (ExpandNode(Node))
1423         return;
1424       // FALL THROUGH
1425     case TargetLowering::LibCall:
1426       ConvertNodeToLibcall(Node);
1427       return;
1428     case TargetLowering::Promote:
1429       PromoteNode(Node);
1430       return;
1431     }
1432   }
1433 
1434   switch (Node->getOpcode()) {
1435   default:
1436 #ifndef NDEBUG
1437     dbgs() << "NODE: ";
1438     Node->dump( &DAG);
1439     dbgs() << "\n";
1440 #endif
1441     llvm_unreachable("Do not know how to legalize this operator!");
1442 
1443   case ISD::CALLSEQ_START:
1444   case ISD::CALLSEQ_END:
1445     break;
1446   case ISD::LOAD: {
1447     return LegalizeLoadOps(Node);
1448   }
1449   case ISD::STORE: {
1450     return LegalizeStoreOps(Node);
1451   }
1452   }
1453 }
1454 
ExpandExtractFromVectorThroughStack(SDValue Op)1455 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1456   SDValue Vec = Op.getOperand(0);
1457   SDValue Idx = Op.getOperand(1);
1458   SDLoc dl(Op);
1459 
1460   // Before we generate a new store to a temporary stack slot, see if there is
1461   // already one that we can use. There often is because when we scalarize
1462   // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1463   // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1464   // the vector. If all are expanded here, we don't want one store per vector
1465   // element.
1466 
1467   // Caches for hasPredecessorHelper
1468   SmallPtrSet<const SDNode *, 32> Visited;
1469   SmallVector<const SDNode *, 16> Worklist;
1470 
1471   SDValue StackPtr, Ch;
1472   for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1473        UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1474     SDNode *User = *UI;
1475     if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1476       if (ST->isIndexed() || ST->isTruncatingStore() ||
1477           ST->getValue() != Vec)
1478         continue;
1479 
1480       // Make sure that nothing else could have stored into the destination of
1481       // this store.
1482       if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1483         continue;
1484 
1485       // If the index is dependent on the store we will introduce a cycle when
1486       // creating the load (the load uses the index, and by replacing the chain
1487       // we will make the index dependent on the load).
1488       if (Idx.getNode()->hasPredecessorHelper(ST, Visited, Worklist))
1489         continue;
1490 
1491       StackPtr = ST->getBasePtr();
1492       Ch = SDValue(ST, 0);
1493       break;
1494     }
1495   }
1496 
1497   if (!Ch.getNode()) {
1498     // Store the value to a temporary stack slot, then LOAD the returned part.
1499     StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1500     Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1501                       MachinePointerInfo(), false, false, 0);
1502   }
1503 
1504   // Add the offset to the index.
1505   unsigned EltSize =
1506       Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1507   Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1508                     DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1509 
1510   Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1511   StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1512 
1513   SDValue NewLoad;
1514 
1515   if (Op.getValueType().isVector())
1516     NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1517                           MachinePointerInfo(), false, false, false, 0);
1518   else
1519     NewLoad = DAG.getExtLoad(
1520         ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1521         Vec.getValueType().getVectorElementType(), false, false, false, 0);
1522 
1523   // Replace the chain going out of the store, by the one out of the load.
1524   DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1525 
1526   // We introduced a cycle though, so update the loads operands, making sure
1527   // to use the original store's chain as an incoming chain.
1528   SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1529                                           NewLoad->op_end());
1530   NewLoadOperands[0] = Ch;
1531   NewLoad =
1532       SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1533   return NewLoad;
1534 }
1535 
ExpandInsertToVectorThroughStack(SDValue Op)1536 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1537   assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1538 
1539   SDValue Vec  = Op.getOperand(0);
1540   SDValue Part = Op.getOperand(1);
1541   SDValue Idx  = Op.getOperand(2);
1542   SDLoc dl(Op);
1543 
1544   // Store the value to a temporary stack slot, then LOAD the returned part.
1545 
1546   SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1547   int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1548   MachinePointerInfo PtrInfo =
1549       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1550 
1551   // First store the whole vector.
1552   SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1553                             false, false, 0);
1554 
1555   // Then store the inserted part.
1556 
1557   // Add the offset to the index.
1558   unsigned EltSize =
1559       Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1560 
1561   Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1562                     DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1563   Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1564 
1565   SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1566                                     StackPtr);
1567 
1568   // Store the subvector.
1569   Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1570                     MachinePointerInfo(), false, false, 0);
1571 
1572   // Finally, load the updated vector.
1573   return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1574                      false, false, false, 0);
1575 }
1576 
ExpandVectorBuildThroughStack(SDNode * Node)1577 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1578   // We can't handle this case efficiently.  Allocate a sufficiently
1579   // aligned object on the stack, store each element into it, then load
1580   // the result as a vector.
1581   // Create the stack frame object.
1582   EVT VT = Node->getValueType(0);
1583   EVT EltVT = VT.getVectorElementType();
1584   SDLoc dl(Node);
1585   SDValue FIPtr = DAG.CreateStackTemporary(VT);
1586   int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1587   MachinePointerInfo PtrInfo =
1588       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1589 
1590   // Emit a store of each element to the stack slot.
1591   SmallVector<SDValue, 8> Stores;
1592   unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1593   // Store (in the right endianness) the elements to memory.
1594   for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1595     // Ignore undef elements.
1596     if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1597 
1598     unsigned Offset = TypeByteSize*i;
1599 
1600     SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1601     Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1602 
1603     // If the destination vector element type is narrower than the source
1604     // element type, only store the bits necessary.
1605     if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1606       Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1607                                          Node->getOperand(i), Idx,
1608                                          PtrInfo.getWithOffset(Offset),
1609                                          EltVT, false, false, 0));
1610     } else
1611       Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1612                                     Node->getOperand(i), Idx,
1613                                     PtrInfo.getWithOffset(Offset),
1614                                     false, false, 0));
1615   }
1616 
1617   SDValue StoreChain;
1618   if (!Stores.empty())    // Not all undef elements?
1619     StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1620   else
1621     StoreChain = DAG.getEntryNode();
1622 
1623   // Result is a load from the stack slot.
1624   return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1625                      false, false, false, 0);
1626 }
1627 
1628 namespace {
1629 /// Keeps track of state when getting the sign of a floating-point value as an
1630 /// integer.
1631 struct FloatSignAsInt {
1632   EVT FloatVT;
1633   SDValue Chain;
1634   SDValue FloatPtr;
1635   SDValue IntPtr;
1636   MachinePointerInfo IntPointerInfo;
1637   MachinePointerInfo FloatPointerInfo;
1638   SDValue IntValue;
1639   APInt SignMask;
1640 };
1641 }
1642 
1643 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1644 /// containing the sign bit if the target has no integer value capable of
1645 /// holding all bits of the floating-point value.
getSignAsIntValue(FloatSignAsInt & State,SDLoc DL,SDValue Value) const1646 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1647                                              SDLoc DL, SDValue Value) const {
1648   EVT FloatVT = Value.getValueType();
1649   unsigned NumBits = FloatVT.getSizeInBits();
1650   State.FloatVT = FloatVT;
1651   EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1652   // Convert to an integer of the same size.
1653   if (TLI.isTypeLegal(IVT)) {
1654     State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1655     State.SignMask = APInt::getSignBit(NumBits);
1656     return;
1657   }
1658 
1659   auto &DataLayout = DAG.getDataLayout();
1660   // Store the float to memory, then load the sign part out as an integer.
1661   MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1662   // First create a temporary that is aligned for both the load and store.
1663   SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1664   int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1665   // Then store the float to it.
1666   State.FloatPtr = StackPtr;
1667   MachineFunction &MF = DAG.getMachineFunction();
1668   State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1669   State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1670                              State.FloatPointerInfo, false, false, 0);
1671 
1672   SDValue IntPtr;
1673   if (DataLayout.isBigEndian()) {
1674     assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1675     // Load out a legal integer with the same sign bit as the float.
1676     IntPtr = StackPtr;
1677     State.IntPointerInfo = State.FloatPointerInfo;
1678   } else {
1679     // Advance the pointer so that the loaded byte will contain the sign bit.
1680     unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1681     IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1682                       DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1683     State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1684                                                              ByteOffset);
1685   }
1686 
1687   State.IntPtr = IntPtr;
1688   State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain,
1689                                   IntPtr, State.IntPointerInfo, MVT::i8,
1690                                   false, false, false, 0);
1691   State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1692 }
1693 
1694 /// Replace the integer value produced by getSignAsIntValue() with a new value
1695 /// and cast the result back to a floating-point type.
modifySignAsInt(const FloatSignAsInt & State,SDLoc DL,SDValue NewIntValue) const1696 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1697                                           SDLoc DL, SDValue NewIntValue) const {
1698   if (!State.Chain)
1699     return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1700 
1701   // Override the part containing the sign bit in the value stored on the stack.
1702   SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1703                                     State.IntPointerInfo, MVT::i8, false, false,
1704                                     0);
1705   return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1706                      State.FloatPointerInfo, false, false, false, 0);
1707 }
1708 
ExpandFCOPYSIGN(SDNode * Node) const1709 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1710   SDLoc DL(Node);
1711   SDValue Mag = Node->getOperand(0);
1712   SDValue Sign = Node->getOperand(1);
1713 
1714   // Get sign bit into an integer value.
1715   FloatSignAsInt SignAsInt;
1716   getSignAsIntValue(SignAsInt, DL, Sign);
1717 
1718   EVT IntVT = SignAsInt.IntValue.getValueType();
1719   SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1720   SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1721                                 SignMask);
1722 
1723   // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1724   EVT FloatVT = Mag.getValueType();
1725   if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1726       TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1727     SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1728     SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1729     SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1730                                 DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1731     return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1732   }
1733 
1734   // Transform values to integer, copy the sign bit and transform back.
1735   FloatSignAsInt MagAsInt;
1736   getSignAsIntValue(MagAsInt, DL, Mag);
1737   assert(SignAsInt.SignMask == MagAsInt.SignMask);
1738   SDValue ClearSignMask = DAG.getConstant(~SignAsInt.SignMask, DL, IntVT);
1739   SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, MagAsInt.IntValue,
1740                                     ClearSignMask);
1741   SDValue CopiedSign = DAG.getNode(ISD::OR, DL, IntVT, ClearedSign, SignBit);
1742 
1743   return modifySignAsInt(MagAsInt, DL, CopiedSign);
1744 }
1745 
ExpandFABS(SDNode * Node) const1746 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1747   SDLoc DL(Node);
1748   SDValue Value = Node->getOperand(0);
1749 
1750   // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1751   EVT FloatVT = Value.getValueType();
1752   if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1753     SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1754     return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1755   }
1756 
1757   // Transform value to integer, clear the sign bit and transform back.
1758   FloatSignAsInt ValueAsInt;
1759   getSignAsIntValue(ValueAsInt, DL, Value);
1760   EVT IntVT = ValueAsInt.IntValue.getValueType();
1761   SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1762   SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1763                                     ClearSignMask);
1764   return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1765 }
1766 
ExpandDYNAMIC_STACKALLOC(SDNode * Node,SmallVectorImpl<SDValue> & Results)1767 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1768                                            SmallVectorImpl<SDValue> &Results) {
1769   unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1770   assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1771           " not tell us which reg is the stack pointer!");
1772   SDLoc dl(Node);
1773   EVT VT = Node->getValueType(0);
1774   SDValue Tmp1 = SDValue(Node, 0);
1775   SDValue Tmp2 = SDValue(Node, 1);
1776   SDValue Tmp3 = Node->getOperand(2);
1777   SDValue Chain = Tmp1.getOperand(0);
1778 
1779   // Chain the dynamic stack allocation so that it doesn't modify the stack
1780   // pointer when other instructions are using the stack.
1781   Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1782 
1783   SDValue Size  = Tmp2.getOperand(1);
1784   SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1785   Chain = SP.getValue(1);
1786   unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1787   unsigned StackAlign =
1788       DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1789   Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size);       // Value
1790   if (Align > StackAlign)
1791     Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1792                        DAG.getConstant(-(uint64_t)Align, dl, VT));
1793   Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1);     // Output chain
1794 
1795   Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1796                             DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1797 
1798   Results.push_back(Tmp1);
1799   Results.push_back(Tmp2);
1800 }
1801 
1802 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1803 /// target.
1804 ///
1805 /// If the SETCC has been legalized using AND / OR, then the legalized node
1806 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1807 /// will be set to false.
1808 ///
1809 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1810 /// then the values of LHS and RHS will be swapped, CC will be set to the
1811 /// new condition, and NeedInvert will be set to false.
1812 ///
1813 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1814 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1815 /// will be set to true. The caller must invert the result of the SETCC with
1816 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1817 /// of a true/false result.
1818 ///
1819 /// \returns true if the SetCC has been legalized, false if it hasn't.
LegalizeSetCCCondCode(EVT VT,SDValue & LHS,SDValue & RHS,SDValue & CC,bool & NeedInvert,SDLoc dl)1820 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1821                                                  SDValue &LHS, SDValue &RHS,
1822                                                  SDValue &CC,
1823                                                  bool &NeedInvert,
1824                                                  SDLoc dl) {
1825   MVT OpVT = LHS.getSimpleValueType();
1826   ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1827   NeedInvert = false;
1828   switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1829   default: llvm_unreachable("Unknown condition code action!");
1830   case TargetLowering::Legal:
1831     // Nothing to do.
1832     break;
1833   case TargetLowering::Expand: {
1834     ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1835     if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1836       std::swap(LHS, RHS);
1837       CC = DAG.getCondCode(InvCC);
1838       return true;
1839     }
1840     ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1841     unsigned Opc = 0;
1842     switch (CCCode) {
1843     default: llvm_unreachable("Don't know how to expand this condition!");
1844     case ISD::SETO:
1845         assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1846             == TargetLowering::Legal
1847             && "If SETO is expanded, SETOEQ must be legal!");
1848         CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1849     case ISD::SETUO:
1850         assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1851             == TargetLowering::Legal
1852             && "If SETUO is expanded, SETUNE must be legal!");
1853         CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR;  break;
1854     case ISD::SETOEQ:
1855     case ISD::SETOGT:
1856     case ISD::SETOGE:
1857     case ISD::SETOLT:
1858     case ISD::SETOLE:
1859     case ISD::SETONE:
1860     case ISD::SETUEQ:
1861     case ISD::SETUNE:
1862     case ISD::SETUGT:
1863     case ISD::SETUGE:
1864     case ISD::SETULT:
1865     case ISD::SETULE:
1866         // If we are floating point, assign and break, otherwise fall through.
1867         if (!OpVT.isInteger()) {
1868           // We can use the 4th bit to tell if we are the unordered
1869           // or ordered version of the opcode.
1870           CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1871           Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1872           CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1873           break;
1874         }
1875         // Fallthrough if we are unsigned integer.
1876     case ISD::SETLE:
1877     case ISD::SETGT:
1878     case ISD::SETGE:
1879     case ISD::SETLT:
1880       // We only support using the inverted operation, which is computed above
1881       // and not a different manner of supporting expanding these cases.
1882       llvm_unreachable("Don't know how to expand this condition!");
1883     case ISD::SETNE:
1884     case ISD::SETEQ:
1885       // Try inverting the result of the inverse condition.
1886       InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1887       if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1888         CC = DAG.getCondCode(InvCC);
1889         NeedInvert = true;
1890         return true;
1891       }
1892       // If inverting the condition didn't work then we have no means to expand
1893       // the condition.
1894       llvm_unreachable("Don't know how to expand this condition!");
1895     }
1896 
1897     SDValue SetCC1, SetCC2;
1898     if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1899       // If we aren't the ordered or unorder operation,
1900       // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1901       SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1902       SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1903     } else {
1904       // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1905       SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1906       SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1907     }
1908     LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1909     RHS = SDValue();
1910     CC  = SDValue();
1911     return true;
1912   }
1913   }
1914   return false;
1915 }
1916 
1917 /// Emit a store/load combination to the stack.  This stores
1918 /// SrcOp to a stack slot of type SlotVT, truncating it if needed.  It then does
1919 /// a load from the stack slot to DestVT, extending it if needed.
1920 /// The resultant code need not be legal.
EmitStackConvert(SDValue SrcOp,EVT SlotVT,EVT DestVT,SDLoc dl)1921 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1922                                                EVT SlotVT,
1923                                                EVT DestVT,
1924                                                SDLoc dl) {
1925   // Create the stack frame object.
1926   unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1927       SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1928   SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1929 
1930   FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1931   int SPFI = StackPtrFI->getIndex();
1932   MachinePointerInfo PtrInfo =
1933       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1934 
1935   unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1936   unsigned SlotSize = SlotVT.getSizeInBits();
1937   unsigned DestSize = DestVT.getSizeInBits();
1938   Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1939   unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1940 
1941   // Emit a store to the stack slot.  Use a truncstore if the input value is
1942   // later than DestVT.
1943   SDValue Store;
1944 
1945   if (SrcSize > SlotSize)
1946     Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1947                               PtrInfo, SlotVT, false, false, SrcAlign);
1948   else {
1949     assert(SrcSize == SlotSize && "Invalid store");
1950     Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1951                          PtrInfo, false, false, SrcAlign);
1952   }
1953 
1954   // Result is a load from the stack slot.
1955   if (SlotSize == DestSize)
1956     return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1957                        false, false, false, DestAlign);
1958 
1959   assert(SlotSize < DestSize && "Unknown extension!");
1960   return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1961                         PtrInfo, SlotVT, false, false, false, DestAlign);
1962 }
1963 
ExpandSCALAR_TO_VECTOR(SDNode * Node)1964 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1965   SDLoc dl(Node);
1966   // Create a vector sized/aligned stack slot, store the value to element #0,
1967   // then load the whole vector back out.
1968   SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1969 
1970   FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1971   int SPFI = StackPtrFI->getIndex();
1972 
1973   SDValue Ch = DAG.getTruncStore(
1974       DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
1975       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
1976       Node->getValueType(0).getVectorElementType(), false, false, 0);
1977   return DAG.getLoad(
1978       Node->getValueType(0), dl, Ch, StackPtr,
1979       MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
1980       false, false, 0);
1981 }
1982 
1983 static bool
ExpandBVWithShuffles(SDNode * Node,SelectionDAG & DAG,const TargetLowering & TLI,SDValue & Res)1984 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1985                      const TargetLowering &TLI, SDValue &Res) {
1986   unsigned NumElems = Node->getNumOperands();
1987   SDLoc dl(Node);
1988   EVT VT = Node->getValueType(0);
1989 
1990   // Try to group the scalars into pairs, shuffle the pairs together, then
1991   // shuffle the pairs of pairs together, etc. until the vector has
1992   // been built. This will work only if all of the necessary shuffle masks
1993   // are legal.
1994 
1995   // We do this in two phases; first to check the legality of the shuffles,
1996   // and next, assuming that all shuffles are legal, to create the new nodes.
1997   for (int Phase = 0; Phase < 2; ++Phase) {
1998     SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1999                                                                NewIntermedVals;
2000     for (unsigned i = 0; i < NumElems; ++i) {
2001       SDValue V = Node->getOperand(i);
2002       if (V.getOpcode() == ISD::UNDEF)
2003         continue;
2004 
2005       SDValue Vec;
2006       if (Phase)
2007         Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
2008       IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
2009     }
2010 
2011     while (IntermedVals.size() > 2) {
2012       NewIntermedVals.clear();
2013       for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
2014         // This vector and the next vector are shuffled together (simply to
2015         // append the one to the other).
2016         SmallVector<int, 16> ShuffleVec(NumElems, -1);
2017 
2018         SmallVector<int, 16> FinalIndices;
2019         FinalIndices.reserve(IntermedVals[i].second.size() +
2020                              IntermedVals[i+1].second.size());
2021 
2022         int k = 0;
2023         for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
2024              ++j, ++k) {
2025           ShuffleVec[k] = j;
2026           FinalIndices.push_back(IntermedVals[i].second[j]);
2027         }
2028         for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
2029              ++j, ++k) {
2030           ShuffleVec[k] = NumElems + j;
2031           FinalIndices.push_back(IntermedVals[i+1].second[j]);
2032         }
2033 
2034         SDValue Shuffle;
2035         if (Phase)
2036           Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
2037                                          IntermedVals[i+1].first,
2038                                          ShuffleVec.data());
2039         else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2040           return false;
2041         NewIntermedVals.push_back(
2042             std::make_pair(Shuffle, std::move(FinalIndices)));
2043       }
2044 
2045       // If we had an odd number of defined values, then append the last
2046       // element to the array of new vectors.
2047       if ((IntermedVals.size() & 1) != 0)
2048         NewIntermedVals.push_back(IntermedVals.back());
2049 
2050       IntermedVals.swap(NewIntermedVals);
2051     }
2052 
2053     assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
2054            "Invalid number of intermediate vectors");
2055     SDValue Vec1 = IntermedVals[0].first;
2056     SDValue Vec2;
2057     if (IntermedVals.size() > 1)
2058       Vec2 = IntermedVals[1].first;
2059     else if (Phase)
2060       Vec2 = DAG.getUNDEF(VT);
2061 
2062     SmallVector<int, 16> ShuffleVec(NumElems, -1);
2063     for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
2064       ShuffleVec[IntermedVals[0].second[i]] = i;
2065     for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
2066       ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
2067 
2068     if (Phase)
2069       Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2070     else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2071       return false;
2072   }
2073 
2074   return true;
2075 }
2076 
2077 /// Expand a BUILD_VECTOR node on targets that don't
2078 /// support the operation, but do support the resultant vector type.
ExpandBUILD_VECTOR(SDNode * Node)2079 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2080   unsigned NumElems = Node->getNumOperands();
2081   SDValue Value1, Value2;
2082   SDLoc dl(Node);
2083   EVT VT = Node->getValueType(0);
2084   EVT OpVT = Node->getOperand(0).getValueType();
2085   EVT EltVT = VT.getVectorElementType();
2086 
2087   // If the only non-undef value is the low element, turn this into a
2088   // SCALAR_TO_VECTOR node.  If this is { X, X, X, X }, determine X.
2089   bool isOnlyLowElement = true;
2090   bool MoreThanTwoValues = false;
2091   bool isConstant = true;
2092   for (unsigned i = 0; i < NumElems; ++i) {
2093     SDValue V = Node->getOperand(i);
2094     if (V.getOpcode() == ISD::UNDEF)
2095       continue;
2096     if (i > 0)
2097       isOnlyLowElement = false;
2098     if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2099       isConstant = false;
2100 
2101     if (!Value1.getNode()) {
2102       Value1 = V;
2103     } else if (!Value2.getNode()) {
2104       if (V != Value1)
2105         Value2 = V;
2106     } else if (V != Value1 && V != Value2) {
2107       MoreThanTwoValues = true;
2108     }
2109   }
2110 
2111   if (!Value1.getNode())
2112     return DAG.getUNDEF(VT);
2113 
2114   if (isOnlyLowElement)
2115     return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2116 
2117   // If all elements are constants, create a load from the constant pool.
2118   if (isConstant) {
2119     SmallVector<Constant*, 16> CV;
2120     for (unsigned i = 0, e = NumElems; i != e; ++i) {
2121       if (ConstantFPSDNode *V =
2122           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2123         CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2124       } else if (ConstantSDNode *V =
2125                  dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2126         if (OpVT==EltVT)
2127           CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2128         else {
2129           // If OpVT and EltVT don't match, EltVT is not legal and the
2130           // element values have been promoted/truncated earlier.  Undo this;
2131           // we don't want a v16i8 to become a v16i32 for example.
2132           const ConstantInt *CI = V->getConstantIntValue();
2133           CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2134                                         CI->getZExtValue()));
2135         }
2136       } else {
2137         assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2138         Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2139         CV.push_back(UndefValue::get(OpNTy));
2140       }
2141     }
2142     Constant *CP = ConstantVector::get(CV);
2143     SDValue CPIdx =
2144         DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
2145     unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2146     return DAG.getLoad(
2147         VT, dl, DAG.getEntryNode(), CPIdx,
2148         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2149         false, false, Alignment);
2150   }
2151 
2152   SmallSet<SDValue, 16> DefinedValues;
2153   for (unsigned i = 0; i < NumElems; ++i) {
2154     if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2155       continue;
2156     DefinedValues.insert(Node->getOperand(i));
2157   }
2158 
2159   if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2160     if (!MoreThanTwoValues) {
2161       SmallVector<int, 8> ShuffleVec(NumElems, -1);
2162       for (unsigned i = 0; i < NumElems; ++i) {
2163         SDValue V = Node->getOperand(i);
2164         if (V.getOpcode() == ISD::UNDEF)
2165           continue;
2166         ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2167       }
2168       if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2169         // Get the splatted value into the low element of a vector register.
2170         SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2171         SDValue Vec2;
2172         if (Value2.getNode())
2173           Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2174         else
2175           Vec2 = DAG.getUNDEF(VT);
2176 
2177         // Return shuffle(LowValVec, undef, <0,0,0,0>)
2178         return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2179       }
2180     } else {
2181       SDValue Res;
2182       if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2183         return Res;
2184     }
2185   }
2186 
2187   // Otherwise, we can't handle this case efficiently.
2188   return ExpandVectorBuildThroughStack(Node);
2189 }
2190 
2191 // Expand a node into a call to a libcall.  If the result value
2192 // does not fit into a register, return the lo part and set the hi part to the
2193 // by-reg argument.  If it does fit into a single register, return the result
2194 // and leave the Hi part unset.
ExpandLibCall(RTLIB::Libcall LC,SDNode * Node,bool isSigned)2195 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2196                                             bool isSigned) {
2197   TargetLowering::ArgListTy Args;
2198   TargetLowering::ArgListEntry Entry;
2199   for (const SDValue &Op : Node->op_values()) {
2200     EVT ArgVT = Op.getValueType();
2201     Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2202     Entry.Node = Op;
2203     Entry.Ty = ArgTy;
2204     Entry.isSExt = isSigned;
2205     Entry.isZExt = !isSigned;
2206     Args.push_back(Entry);
2207   }
2208   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2209                                          TLI.getPointerTy(DAG.getDataLayout()));
2210 
2211   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2212 
2213   // By default, the input chain to this libcall is the entry node of the
2214   // function. If the libcall is going to be emitted as a tail call then
2215   // TLI.isUsedByReturnOnly will change it to the right chain if the return
2216   // node which is being folded has a non-entry input chain.
2217   SDValue InChain = DAG.getEntryNode();
2218 
2219   // isTailCall may be true since the callee does not reference caller stack
2220   // frame. Check if it's in the right position.
2221   SDValue TCChain = InChain;
2222   bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2223   if (isTailCall)
2224     InChain = TCChain;
2225 
2226   TargetLowering::CallLoweringInfo CLI(DAG);
2227   CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2228     .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2229     .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2230 
2231   std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2232 
2233   if (!CallInfo.second.getNode())
2234     // It's a tailcall, return the chain (which is the DAG root).
2235     return DAG.getRoot();
2236 
2237   return CallInfo.first;
2238 }
2239 
2240 /// Generate a libcall taking the given operands as arguments
2241 /// and returning a result of type RetVT.
ExpandLibCall(RTLIB::Libcall LC,EVT RetVT,const SDValue * Ops,unsigned NumOps,bool isSigned,SDLoc dl)2242 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2243                                             const SDValue *Ops, unsigned NumOps,
2244                                             bool isSigned, SDLoc dl) {
2245   TargetLowering::ArgListTy Args;
2246   Args.reserve(NumOps);
2247 
2248   TargetLowering::ArgListEntry Entry;
2249   for (unsigned i = 0; i != NumOps; ++i) {
2250     Entry.Node = Ops[i];
2251     Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2252     Entry.isSExt = isSigned;
2253     Entry.isZExt = !isSigned;
2254     Args.push_back(Entry);
2255   }
2256   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2257                                          TLI.getPointerTy(DAG.getDataLayout()));
2258 
2259   Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2260 
2261   TargetLowering::CallLoweringInfo CLI(DAG);
2262   CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2263     .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2264     .setSExtResult(isSigned).setZExtResult(!isSigned);
2265 
2266   std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2267 
2268   return CallInfo.first;
2269 }
2270 
2271 // Expand a node into a call to a libcall. Similar to
2272 // ExpandLibCall except that the first operand is the in-chain.
2273 std::pair<SDValue, SDValue>
ExpandChainLibCall(RTLIB::Libcall LC,SDNode * Node,bool isSigned)2274 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2275                                          SDNode *Node,
2276                                          bool isSigned) {
2277   SDValue InChain = Node->getOperand(0);
2278 
2279   TargetLowering::ArgListTy Args;
2280   TargetLowering::ArgListEntry Entry;
2281   for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2282     EVT ArgVT = Node->getOperand(i).getValueType();
2283     Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2284     Entry.Node = Node->getOperand(i);
2285     Entry.Ty = ArgTy;
2286     Entry.isSExt = isSigned;
2287     Entry.isZExt = !isSigned;
2288     Args.push_back(Entry);
2289   }
2290   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2291                                          TLI.getPointerTy(DAG.getDataLayout()));
2292 
2293   Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2294 
2295   TargetLowering::CallLoweringInfo CLI(DAG);
2296   CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2297     .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2298     .setSExtResult(isSigned).setZExtResult(!isSigned);
2299 
2300   std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2301 
2302   return CallInfo;
2303 }
2304 
ExpandFPLibCall(SDNode * Node,RTLIB::Libcall Call_F32,RTLIB::Libcall Call_F64,RTLIB::Libcall Call_F80,RTLIB::Libcall Call_F128,RTLIB::Libcall Call_PPCF128)2305 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2306                                               RTLIB::Libcall Call_F32,
2307                                               RTLIB::Libcall Call_F64,
2308                                               RTLIB::Libcall Call_F80,
2309                                               RTLIB::Libcall Call_F128,
2310                                               RTLIB::Libcall Call_PPCF128) {
2311   RTLIB::Libcall LC;
2312   switch (Node->getSimpleValueType(0).SimpleTy) {
2313   default: llvm_unreachable("Unexpected request for libcall!");
2314   case MVT::f32: LC = Call_F32; break;
2315   case MVT::f64: LC = Call_F64; break;
2316   case MVT::f80: LC = Call_F80; break;
2317   case MVT::f128: LC = Call_F128; break;
2318   case MVT::ppcf128: LC = Call_PPCF128; break;
2319   }
2320   return ExpandLibCall(LC, Node, false);
2321 }
2322 
ExpandIntLibCall(SDNode * Node,bool isSigned,RTLIB::Libcall Call_I8,RTLIB::Libcall Call_I16,RTLIB::Libcall Call_I32,RTLIB::Libcall Call_I64,RTLIB::Libcall Call_I128)2323 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2324                                                RTLIB::Libcall Call_I8,
2325                                                RTLIB::Libcall Call_I16,
2326                                                RTLIB::Libcall Call_I32,
2327                                                RTLIB::Libcall Call_I64,
2328                                                RTLIB::Libcall Call_I128) {
2329   RTLIB::Libcall LC;
2330   switch (Node->getSimpleValueType(0).SimpleTy) {
2331   default: llvm_unreachable("Unexpected request for libcall!");
2332   case MVT::i8:   LC = Call_I8; break;
2333   case MVT::i16:  LC = Call_I16; break;
2334   case MVT::i32:  LC = Call_I32; break;
2335   case MVT::i64:  LC = Call_I64; break;
2336   case MVT::i128: LC = Call_I128; break;
2337   }
2338   return ExpandLibCall(LC, Node, isSigned);
2339 }
2340 
2341 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2342 void
ExpandDivRemLibCall(SDNode * Node,SmallVectorImpl<SDValue> & Results)2343 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2344                                           SmallVectorImpl<SDValue> &Results) {
2345   unsigned Opcode = Node->getOpcode();
2346   bool isSigned = Opcode == ISD::SDIVREM;
2347 
2348   RTLIB::Libcall LC;
2349   switch (Node->getSimpleValueType(0).SimpleTy) {
2350   default: llvm_unreachable("Unexpected request for libcall!");
2351   case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
2352   case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2353   case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2354   case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2355   case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2356   }
2357 
2358   // The input chain to this libcall is the entry node of the function.
2359   // Legalizing the call will automatically add the previous call to the
2360   // dependence.
2361   SDValue InChain = DAG.getEntryNode();
2362 
2363   EVT RetVT = Node->getValueType(0);
2364   Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2365 
2366   TargetLowering::ArgListTy Args;
2367   TargetLowering::ArgListEntry Entry;
2368   for (const SDValue &Op : Node->op_values()) {
2369     EVT ArgVT = Op.getValueType();
2370     Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2371     Entry.Node = Op;
2372     Entry.Ty = ArgTy;
2373     Entry.isSExt = isSigned;
2374     Entry.isZExt = !isSigned;
2375     Args.push_back(Entry);
2376   }
2377 
2378   // Also pass the return address of the remainder.
2379   SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2380   Entry.Node = FIPtr;
2381   Entry.Ty = RetTy->getPointerTo();
2382   Entry.isSExt = isSigned;
2383   Entry.isZExt = !isSigned;
2384   Args.push_back(Entry);
2385 
2386   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2387                                          TLI.getPointerTy(DAG.getDataLayout()));
2388 
2389   SDLoc dl(Node);
2390   TargetLowering::CallLoweringInfo CLI(DAG);
2391   CLI.setDebugLoc(dl).setChain(InChain)
2392     .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2393     .setSExtResult(isSigned).setZExtResult(!isSigned);
2394 
2395   std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2396 
2397   // Remainder is loaded back from the stack frame.
2398   SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2399                             MachinePointerInfo(), false, false, false, 0);
2400   Results.push_back(CallInfo.first);
2401   Results.push_back(Rem);
2402 }
2403 
2404 /// Return true if sincos libcall is available.
isSinCosLibcallAvailable(SDNode * Node,const TargetLowering & TLI)2405 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2406   RTLIB::Libcall LC;
2407   switch (Node->getSimpleValueType(0).SimpleTy) {
2408   default: llvm_unreachable("Unexpected request for libcall!");
2409   case MVT::f32:     LC = RTLIB::SINCOS_F32; break;
2410   case MVT::f64:     LC = RTLIB::SINCOS_F64; break;
2411   case MVT::f80:     LC = RTLIB::SINCOS_F80; break;
2412   case MVT::f128:    LC = RTLIB::SINCOS_F128; break;
2413   case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2414   }
2415   return TLI.getLibcallName(LC) != nullptr;
2416 }
2417 
2418 /// Return true if sincos libcall is available and can be used to combine sin
2419 /// and cos.
canCombineSinCosLibcall(SDNode * Node,const TargetLowering & TLI,const TargetMachine & TM)2420 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2421                                     const TargetMachine &TM) {
2422   if (!isSinCosLibcallAvailable(Node, TLI))
2423     return false;
2424   // GNU sin/cos functions set errno while sincos does not. Therefore
2425   // combining sin and cos is only safe if unsafe-fpmath is enabled.
2426   bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2427   if (isGNU && !TM.Options.UnsafeFPMath)
2428     return false;
2429   return true;
2430 }
2431 
2432 /// Only issue sincos libcall if both sin and cos are needed.
useSinCos(SDNode * Node)2433 static bool useSinCos(SDNode *Node) {
2434   unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2435     ? ISD::FCOS : ISD::FSIN;
2436 
2437   SDValue Op0 = Node->getOperand(0);
2438   for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2439        UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2440     SDNode *User = *UI;
2441     if (User == Node)
2442       continue;
2443     // The other user might have been turned into sincos already.
2444     if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2445       return true;
2446   }
2447   return false;
2448 }
2449 
2450 /// Issue libcalls to sincos to compute sin / cos pairs.
2451 void
ExpandSinCosLibCall(SDNode * Node,SmallVectorImpl<SDValue> & Results)2452 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2453                                           SmallVectorImpl<SDValue> &Results) {
2454   RTLIB::Libcall LC;
2455   switch (Node->getSimpleValueType(0).SimpleTy) {
2456   default: llvm_unreachable("Unexpected request for libcall!");
2457   case MVT::f32:     LC = RTLIB::SINCOS_F32; break;
2458   case MVT::f64:     LC = RTLIB::SINCOS_F64; break;
2459   case MVT::f80:     LC = RTLIB::SINCOS_F80; break;
2460   case MVT::f128:    LC = RTLIB::SINCOS_F128; break;
2461   case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2462   }
2463 
2464   // The input chain to this libcall is the entry node of the function.
2465   // Legalizing the call will automatically add the previous call to the
2466   // dependence.
2467   SDValue InChain = DAG.getEntryNode();
2468 
2469   EVT RetVT = Node->getValueType(0);
2470   Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2471 
2472   TargetLowering::ArgListTy Args;
2473   TargetLowering::ArgListEntry Entry;
2474 
2475   // Pass the argument.
2476   Entry.Node = Node->getOperand(0);
2477   Entry.Ty = RetTy;
2478   Entry.isSExt = false;
2479   Entry.isZExt = false;
2480   Args.push_back(Entry);
2481 
2482   // Pass the return address of sin.
2483   SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2484   Entry.Node = SinPtr;
2485   Entry.Ty = RetTy->getPointerTo();
2486   Entry.isSExt = false;
2487   Entry.isZExt = false;
2488   Args.push_back(Entry);
2489 
2490   // Also pass the return address of the cos.
2491   SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2492   Entry.Node = CosPtr;
2493   Entry.Ty = RetTy->getPointerTo();
2494   Entry.isSExt = false;
2495   Entry.isZExt = false;
2496   Args.push_back(Entry);
2497 
2498   SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2499                                          TLI.getPointerTy(DAG.getDataLayout()));
2500 
2501   SDLoc dl(Node);
2502   TargetLowering::CallLoweringInfo CLI(DAG);
2503   CLI.setDebugLoc(dl).setChain(InChain)
2504     .setCallee(TLI.getLibcallCallingConv(LC),
2505                Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2506 
2507   std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2508 
2509   Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2510                                 MachinePointerInfo(), false, false, false, 0));
2511   Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2512                                 MachinePointerInfo(), false, false, false, 0));
2513 }
2514 
2515 /// This function is responsible for legalizing a
2516 /// INT_TO_FP operation of the specified operand when the target requests that
2517 /// we expand it.  At this point, we know that the result and operand types are
2518 /// legal for the target.
ExpandLegalINT_TO_FP(bool isSigned,SDValue Op0,EVT DestVT,SDLoc dl)2519 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2520                                                    SDValue Op0,
2521                                                    EVT DestVT,
2522                                                    SDLoc dl) {
2523   // TODO: Should any fast-math-flags be set for the created nodes?
2524 
2525   if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2526     // simple 32-bit [signed|unsigned] integer to float/double expansion
2527 
2528     // Get the stack frame index of a 8 byte buffer.
2529     SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2530 
2531     // word offset constant for Hi/Lo address computation
2532     SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2533                                       StackSlot.getValueType());
2534     // set up Hi and Lo (into buffer) address based on endian
2535     SDValue Hi = StackSlot;
2536     SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2537                              StackSlot, WordOff);
2538     if (DAG.getDataLayout().isLittleEndian())
2539       std::swap(Hi, Lo);
2540 
2541     // if signed map to unsigned space
2542     SDValue Op0Mapped;
2543     if (isSigned) {
2544       // constant used to invert sign bit (signed to unsigned mapping)
2545       SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2546       Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2547     } else {
2548       Op0Mapped = Op0;
2549     }
2550     // store the lo of the constructed double - based on integer input
2551     SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2552                                   Op0Mapped, Lo, MachinePointerInfo(),
2553                                   false, false, 0);
2554     // initial hi portion of constructed double
2555     SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2556     // store the hi of the constructed double - biased exponent
2557     SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2558                                   MachinePointerInfo(),
2559                                   false, false, 0);
2560     // load the constructed double
2561     SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2562                                MachinePointerInfo(), false, false, false, 0);
2563     // FP constant to bias correct the final result
2564     SDValue Bias = DAG.getConstantFP(isSigned ?
2565                                      BitsToDouble(0x4330000080000000ULL) :
2566                                      BitsToDouble(0x4330000000000000ULL),
2567                                      dl, MVT::f64);
2568     // subtract the bias
2569     SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2570     // final result
2571     SDValue Result;
2572     // handle final rounding
2573     if (DestVT == MVT::f64) {
2574       // do nothing
2575       Result = Sub;
2576     } else if (DestVT.bitsLT(MVT::f64)) {
2577       Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2578                            DAG.getIntPtrConstant(0, dl));
2579     } else if (DestVT.bitsGT(MVT::f64)) {
2580       Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2581     }
2582     return Result;
2583   }
2584   assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2585   // Code below here assumes !isSigned without checking again.
2586 
2587   // Implementation of unsigned i64 to f64 following the algorithm in
2588   // __floatundidf in compiler_rt. This implementation has the advantage
2589   // of performing rounding correctly, both in the default rounding mode
2590   // and in all alternate rounding modes.
2591   // TODO: Generalize this for use with other types.
2592   if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2593     SDValue TwoP52 =
2594       DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2595     SDValue TwoP84PlusTwoP52 =
2596       DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2597                         MVT::f64);
2598     SDValue TwoP84 =
2599       DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2600 
2601     SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2602     SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2603                              DAG.getConstant(32, dl, MVT::i64));
2604     SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2605     SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2606     SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2607     SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2608     SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2609                                 TwoP84PlusTwoP52);
2610     return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2611   }
2612 
2613   // Implementation of unsigned i64 to f32.
2614   // TODO: Generalize this for use with other types.
2615   if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2616     // For unsigned conversions, convert them to signed conversions using the
2617     // algorithm from the x86_64 __floatundidf in compiler_rt.
2618     if (!isSigned) {
2619       SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2620 
2621       SDValue ShiftConst = DAG.getConstant(
2622           1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2623       SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2624       SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2625       SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2626       SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2627 
2628       SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2629       SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2630 
2631       // TODO: This really should be implemented using a branch rather than a
2632       // select.  We happen to get lucky and machinesink does the right
2633       // thing most of the time.  This would be a good candidate for a
2634       //pseudo-op, or, even better, for whole-function isel.
2635       SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2636         Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2637       return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2638     }
2639 
2640     // Otherwise, implement the fully general conversion.
2641 
2642     SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2643          DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2644     SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2645          DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2646     SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2647          DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2648     SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2649                               DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2650                               ISD::SETNE);
2651     SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2652     SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2653                               DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2654                                               MVT::i64),
2655                               ISD::SETUGE);
2656     SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2657     EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2658 
2659     SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2660                              DAG.getConstant(32, dl, SHVT));
2661     SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2662     SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2663     SDValue TwoP32 =
2664       DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2665                         MVT::f64);
2666     SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2667     SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2668     SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2669     SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2670     return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2671                        DAG.getIntPtrConstant(0, dl));
2672   }
2673 
2674   SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2675 
2676   SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2677                                  Op0,
2678                                  DAG.getConstant(0, dl, Op0.getValueType()),
2679                                  ISD::SETLT);
2680   SDValue Zero = DAG.getIntPtrConstant(0, dl),
2681           Four = DAG.getIntPtrConstant(4, dl);
2682   SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2683                                     SignSet, Four, Zero);
2684 
2685   // If the sign bit of the integer is set, the large number will be treated
2686   // as a negative number.  To counteract this, the dynamic code adds an
2687   // offset depending on the data type.
2688   uint64_t FF;
2689   switch (Op0.getSimpleValueType().SimpleTy) {
2690   default: llvm_unreachable("Unsupported integer type!");
2691   case MVT::i8 : FF = 0x43800000ULL; break;  // 2^8  (as a float)
2692   case MVT::i16: FF = 0x47800000ULL; break;  // 2^16 (as a float)
2693   case MVT::i32: FF = 0x4F800000ULL; break;  // 2^32 (as a float)
2694   case MVT::i64: FF = 0x5F800000ULL; break;  // 2^64 (as a float)
2695   }
2696   if (DAG.getDataLayout().isLittleEndian())
2697     FF <<= 32;
2698   Constant *FudgeFactor = ConstantInt::get(
2699                                        Type::getInt64Ty(*DAG.getContext()), FF);
2700 
2701   SDValue CPIdx =
2702       DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2703   unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2704   CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2705   Alignment = std::min(Alignment, 4u);
2706   SDValue FudgeInReg;
2707   if (DestVT == MVT::f32)
2708     FudgeInReg = DAG.getLoad(
2709         MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2710         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2711         false, false, Alignment);
2712   else {
2713     SDValue Load = DAG.getExtLoad(
2714         ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2715         MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2716         false, false, false, Alignment);
2717     HandleSDNode Handle(Load);
2718     LegalizeOp(Load.getNode());
2719     FudgeInReg = Handle.getValue();
2720   }
2721 
2722   return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2723 }
2724 
2725 /// This function is responsible for legalizing a
2726 /// *INT_TO_FP operation of the specified operand when the target requests that
2727 /// we promote it.  At this point, we know that the result and operand types are
2728 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2729 /// operation that takes a larger input.
PromoteLegalINT_TO_FP(SDValue LegalOp,EVT DestVT,bool isSigned,SDLoc dl)2730 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2731                                                     EVT DestVT,
2732                                                     bool isSigned,
2733                                                     SDLoc dl) {
2734   // First step, figure out the appropriate *INT_TO_FP operation to use.
2735   EVT NewInTy = LegalOp.getValueType();
2736 
2737   unsigned OpToUse = 0;
2738 
2739   // Scan for the appropriate larger type to use.
2740   while (1) {
2741     NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2742     assert(NewInTy.isInteger() && "Ran out of possibilities!");
2743 
2744     // If the target supports SINT_TO_FP of this type, use it.
2745     if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2746       OpToUse = ISD::SINT_TO_FP;
2747       break;
2748     }
2749     if (isSigned) continue;
2750 
2751     // If the target supports UINT_TO_FP of this type, use it.
2752     if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2753       OpToUse = ISD::UINT_TO_FP;
2754       break;
2755     }
2756 
2757     // Otherwise, try a larger type.
2758   }
2759 
2760   // Okay, we found the operation and type to use.  Zero extend our input to the
2761   // desired type then run the operation on it.
2762   return DAG.getNode(OpToUse, dl, DestVT,
2763                      DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2764                                  dl, NewInTy, LegalOp));
2765 }
2766 
2767 /// This function is responsible for legalizing a
2768 /// FP_TO_*INT operation of the specified operand when the target requests that
2769 /// we promote it.  At this point, we know that the result and operand types are
2770 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2771 /// operation that returns a larger result.
PromoteLegalFP_TO_INT(SDValue LegalOp,EVT DestVT,bool isSigned,SDLoc dl)2772 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2773                                                     EVT DestVT,
2774                                                     bool isSigned,
2775                                                     SDLoc dl) {
2776   // First step, figure out the appropriate FP_TO*INT operation to use.
2777   EVT NewOutTy = DestVT;
2778 
2779   unsigned OpToUse = 0;
2780 
2781   // Scan for the appropriate larger type to use.
2782   while (1) {
2783     NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2784     assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2785 
2786     // A larger signed type can hold all unsigned values of the requested type,
2787     // so using FP_TO_SINT is valid
2788     if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2789       OpToUse = ISD::FP_TO_SINT;
2790       break;
2791     }
2792 
2793     // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2794     if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2795       OpToUse = ISD::FP_TO_UINT;
2796       break;
2797     }
2798 
2799     // Otherwise, try a larger type.
2800   }
2801 
2802 
2803   // Okay, we found the operation and type to use.
2804   SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2805 
2806   // Truncate the result of the extended FP_TO_*INT operation to the desired
2807   // size.
2808   return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2809 }
2810 
2811 /// Open code the operations for BITREVERSE.
ExpandBITREVERSE(SDValue Op,SDLoc dl)2812 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, SDLoc dl) {
2813   EVT VT = Op.getValueType();
2814   EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2815   unsigned Sz = VT.getScalarSizeInBits();
2816 
2817   SDValue Tmp, Tmp2;
2818   Tmp = DAG.getConstant(0, dl, VT);
2819   for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2820     if (I < J)
2821       Tmp2 =
2822           DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2823     else
2824       Tmp2 =
2825           DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2826 
2827     APInt Shift(Sz, 1);
2828     Shift = Shift.shl(J);
2829     Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2830     Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2831   }
2832 
2833   return Tmp;
2834 }
2835 
2836 /// Open code the operations for BSWAP of the specified operation.
ExpandBSWAP(SDValue Op,SDLoc dl)2837 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2838   EVT VT = Op.getValueType();
2839   EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2840   SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2841   switch (VT.getSimpleVT().SimpleTy) {
2842   default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2843   case MVT::i16:
2844     Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2845     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2846     return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2847   case MVT::i32:
2848     Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2849     Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2850     Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2851     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2852     Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2853                        DAG.getConstant(0xFF0000, dl, VT));
2854     Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2855     Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2856     Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2857     return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2858   case MVT::i64:
2859     Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2860     Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2861     Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2862     Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2863     Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2864     Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2865     Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2866     Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2867     Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2868                        DAG.getConstant(255ULL<<48, dl, VT));
2869     Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2870                        DAG.getConstant(255ULL<<40, dl, VT));
2871     Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2872                        DAG.getConstant(255ULL<<32, dl, VT));
2873     Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2874                        DAG.getConstant(255ULL<<24, dl, VT));
2875     Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2876                        DAG.getConstant(255ULL<<16, dl, VT));
2877     Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2878                        DAG.getConstant(255ULL<<8 , dl, VT));
2879     Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2880     Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2881     Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2882     Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2883     Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2884     Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2885     return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2886   }
2887 }
2888 
2889 /// Expand the specified bitcount instruction into operations.
ExpandBitCount(unsigned Opc,SDValue Op,SDLoc dl)2890 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2891                                              SDLoc dl) {
2892   switch (Opc) {
2893   default: llvm_unreachable("Cannot expand this yet!");
2894   case ISD::CTPOP: {
2895     EVT VT = Op.getValueType();
2896     EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2897     unsigned Len = VT.getSizeInBits();
2898 
2899     assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2900            "CTPOP not implemented for this type.");
2901 
2902     // This is the "best" algorithm from
2903     // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2904 
2905     SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2906                                      dl, VT);
2907     SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2908                                      dl, VT);
2909     SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2910                                      dl, VT);
2911     SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2912                                      dl, VT);
2913 
2914     // v = v - ((v >> 1) & 0x55555555...)
2915     Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2916                      DAG.getNode(ISD::AND, dl, VT,
2917                                  DAG.getNode(ISD::SRL, dl, VT, Op,
2918                                              DAG.getConstant(1, dl, ShVT)),
2919                                  Mask55));
2920     // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2921     Op = DAG.getNode(ISD::ADD, dl, VT,
2922                      DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2923                      DAG.getNode(ISD::AND, dl, VT,
2924                                  DAG.getNode(ISD::SRL, dl, VT, Op,
2925                                              DAG.getConstant(2, dl, ShVT)),
2926                                  Mask33));
2927     // v = (v + (v >> 4)) & 0x0F0F0F0F...
2928     Op = DAG.getNode(ISD::AND, dl, VT,
2929                      DAG.getNode(ISD::ADD, dl, VT, Op,
2930                                  DAG.getNode(ISD::SRL, dl, VT, Op,
2931                                              DAG.getConstant(4, dl, ShVT))),
2932                      Mask0F);
2933     // v = (v * 0x01010101...) >> (Len - 8)
2934     Op = DAG.getNode(ISD::SRL, dl, VT,
2935                      DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2936                      DAG.getConstant(Len - 8, dl, ShVT));
2937 
2938     return Op;
2939   }
2940   case ISD::CTLZ_ZERO_UNDEF:
2941     // This trivially expands to CTLZ.
2942     return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2943   case ISD::CTLZ: {
2944     // for now, we do this:
2945     // x = x | (x >> 1);
2946     // x = x | (x >> 2);
2947     // ...
2948     // x = x | (x >>16);
2949     // x = x | (x >>32); // for 64-bit input
2950     // return popcount(~x);
2951     //
2952     // Ref: "Hacker's Delight" by Henry Warren
2953     EVT VT = Op.getValueType();
2954     EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2955     unsigned len = VT.getSizeInBits();
2956     for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2957       SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2958       Op = DAG.getNode(ISD::OR, dl, VT, Op,
2959                        DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2960     }
2961     Op = DAG.getNOT(dl, Op, VT);
2962     return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2963   }
2964   case ISD::CTTZ_ZERO_UNDEF:
2965     // This trivially expands to CTTZ.
2966     return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2967   case ISD::CTTZ: {
2968     // for now, we use: { return popcount(~x & (x - 1)); }
2969     // unless the target has ctlz but not ctpop, in which case we use:
2970     // { return 32 - nlz(~x & (x-1)); }
2971     // Ref: "Hacker's Delight" by Henry Warren
2972     EVT VT = Op.getValueType();
2973     SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2974                                DAG.getNOT(dl, Op, VT),
2975                                DAG.getNode(ISD::SUB, dl, VT, Op,
2976                                            DAG.getConstant(1, dl, VT)));
2977     // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2978     if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2979         TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2980       return DAG.getNode(ISD::SUB, dl, VT,
2981                          DAG.getConstant(VT.getSizeInBits(), dl, VT),
2982                          DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2983     return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2984   }
2985   }
2986 }
2987 
ExpandNode(SDNode * Node)2988 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2989   SmallVector<SDValue, 8> Results;
2990   SDLoc dl(Node);
2991   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2992   bool NeedInvert;
2993   switch (Node->getOpcode()) {
2994   case ISD::CTPOP:
2995   case ISD::CTLZ:
2996   case ISD::CTLZ_ZERO_UNDEF:
2997   case ISD::CTTZ:
2998   case ISD::CTTZ_ZERO_UNDEF:
2999     Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
3000     Results.push_back(Tmp1);
3001     break;
3002   case ISD::BITREVERSE:
3003     Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
3004     break;
3005   case ISD::BSWAP:
3006     Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
3007     break;
3008   case ISD::FRAMEADDR:
3009   case ISD::RETURNADDR:
3010   case ISD::FRAME_TO_ARGS_OFFSET:
3011     Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3012     break;
3013   case ISD::FLT_ROUNDS_:
3014     Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
3015     break;
3016   case ISD::EH_RETURN:
3017   case ISD::EH_LABEL:
3018   case ISD::PREFETCH:
3019   case ISD::VAEND:
3020   case ISD::EH_SJLJ_LONGJMP:
3021     // If the target didn't expand these, there's nothing to do, so just
3022     // preserve the chain and be done.
3023     Results.push_back(Node->getOperand(0));
3024     break;
3025   case ISD::READCYCLECOUNTER:
3026     // If the target didn't expand this, just return 'zero' and preserve the
3027     // chain.
3028     Results.append(Node->getNumValues() - 1,
3029                    DAG.getConstant(0, dl, Node->getValueType(0)));
3030     Results.push_back(Node->getOperand(0));
3031     break;
3032   case ISD::EH_SJLJ_SETJMP:
3033     // If the target didn't expand this, just return 'zero' and preserve the
3034     // chain.
3035     Results.push_back(DAG.getConstant(0, dl, MVT::i32));
3036     Results.push_back(Node->getOperand(0));
3037     break;
3038   case ISD::ATOMIC_LOAD: {
3039     // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3040     SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
3041     SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3042     SDValue Swap = DAG.getAtomicCmpSwap(
3043         ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3044         Node->getOperand(0), Node->getOperand(1), Zero, Zero,
3045         cast<AtomicSDNode>(Node)->getMemOperand(),
3046         cast<AtomicSDNode>(Node)->getOrdering(),
3047         cast<AtomicSDNode>(Node)->getOrdering(),
3048         cast<AtomicSDNode>(Node)->getSynchScope());
3049     Results.push_back(Swap.getValue(0));
3050     Results.push_back(Swap.getValue(1));
3051     break;
3052   }
3053   case ISD::ATOMIC_STORE: {
3054     // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3055     SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3056                                  cast<AtomicSDNode>(Node)->getMemoryVT(),
3057                                  Node->getOperand(0),
3058                                  Node->getOperand(1), Node->getOperand(2),
3059                                  cast<AtomicSDNode>(Node)->getMemOperand(),
3060                                  cast<AtomicSDNode>(Node)->getOrdering(),
3061                                  cast<AtomicSDNode>(Node)->getSynchScope());
3062     Results.push_back(Swap.getValue(1));
3063     break;
3064   }
3065   case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3066     // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3067     // splits out the success value as a comparison. Expanding the resulting
3068     // ATOMIC_CMP_SWAP will produce a libcall.
3069     SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3070     SDValue Res = DAG.getAtomicCmpSwap(
3071         ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3072         Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3073         Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3074         cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3075         cast<AtomicSDNode>(Node)->getFailureOrdering(),
3076         cast<AtomicSDNode>(Node)->getSynchScope());
3077 
3078     SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3079                                    Res, Node->getOperand(2), ISD::SETEQ);
3080 
3081     Results.push_back(Res.getValue(0));
3082     Results.push_back(Success);
3083     Results.push_back(Res.getValue(1));
3084     break;
3085   }
3086   case ISD::DYNAMIC_STACKALLOC:
3087     ExpandDYNAMIC_STACKALLOC(Node, Results);
3088     break;
3089   case ISD::MERGE_VALUES:
3090     for (unsigned i = 0; i < Node->getNumValues(); i++)
3091       Results.push_back(Node->getOperand(i));
3092     break;
3093   case ISD::UNDEF: {
3094     EVT VT = Node->getValueType(0);
3095     if (VT.isInteger())
3096       Results.push_back(DAG.getConstant(0, dl, VT));
3097     else {
3098       assert(VT.isFloatingPoint() && "Unknown value type!");
3099       Results.push_back(DAG.getConstantFP(0, dl, VT));
3100     }
3101     break;
3102   }
3103   case ISD::FP_ROUND:
3104   case ISD::BITCAST:
3105     Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3106                             Node->getValueType(0), dl);
3107     Results.push_back(Tmp1);
3108     break;
3109   case ISD::FP_EXTEND:
3110     Tmp1 = EmitStackConvert(Node->getOperand(0),
3111                             Node->getOperand(0).getValueType(),
3112                             Node->getValueType(0), dl);
3113     Results.push_back(Tmp1);
3114     break;
3115   case ISD::SIGN_EXTEND_INREG: {
3116     // NOTE: we could fall back on load/store here too for targets without
3117     // SAR.  However, it is doubtful that any exist.
3118     EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3119     EVT VT = Node->getValueType(0);
3120     EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3121     if (VT.isVector())
3122       ShiftAmountTy = VT;
3123     unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3124                         ExtraVT.getScalarType().getSizeInBits();
3125     SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3126     Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3127                        Node->getOperand(0), ShiftCst);
3128     Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3129     Results.push_back(Tmp1);
3130     break;
3131   }
3132   case ISD::FP_ROUND_INREG: {
3133     // The only way we can lower this is to turn it into a TRUNCSTORE,
3134     // EXTLOAD pair, targeting a temporary location (a stack slot).
3135 
3136     // NOTE: there is a choice here between constantly creating new stack
3137     // slots and always reusing the same one.  We currently always create
3138     // new ones, as reuse may inhibit scheduling.
3139     EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3140     Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3141                             Node->getValueType(0), dl);
3142     Results.push_back(Tmp1);
3143     break;
3144   }
3145   case ISD::SINT_TO_FP:
3146   case ISD::UINT_TO_FP:
3147     Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3148                                 Node->getOperand(0), Node->getValueType(0), dl);
3149     Results.push_back(Tmp1);
3150     break;
3151   case ISD::FP_TO_SINT:
3152     if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3153       Results.push_back(Tmp1);
3154     break;
3155   case ISD::FP_TO_UINT: {
3156     SDValue True, False;
3157     EVT VT =  Node->getOperand(0).getValueType();
3158     EVT NVT = Node->getValueType(0);
3159     APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3160                 APInt::getNullValue(VT.getSizeInBits()));
3161     APInt x = APInt::getSignBit(NVT.getSizeInBits());
3162     (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3163     Tmp1 = DAG.getConstantFP(apf, dl, VT);
3164     Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3165                         Node->getOperand(0),
3166                         Tmp1, ISD::SETLT);
3167     True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3168     // TODO: Should any fast-math-flags be set for the FSUB?
3169     False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3170                         DAG.getNode(ISD::FSUB, dl, VT,
3171                                     Node->getOperand(0), Tmp1));
3172     False = DAG.getNode(ISD::XOR, dl, NVT, False,
3173                         DAG.getConstant(x, dl, NVT));
3174     Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3175     Results.push_back(Tmp1);
3176     break;
3177   }
3178   case ISD::VAARG:
3179     Results.push_back(DAG.expandVAArg(Node));
3180     Results.push_back(Results[0].getValue(1));
3181     break;
3182   case ISD::VACOPY:
3183     Results.push_back(DAG.expandVACopy(Node));
3184     break;
3185   case ISD::EXTRACT_VECTOR_ELT:
3186     if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3187       // This must be an access of the only element.  Return it.
3188       Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3189                          Node->getOperand(0));
3190     else
3191       Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3192     Results.push_back(Tmp1);
3193     break;
3194   case ISD::EXTRACT_SUBVECTOR:
3195     Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3196     break;
3197   case ISD::INSERT_SUBVECTOR:
3198     Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3199     break;
3200   case ISD::CONCAT_VECTORS: {
3201     Results.push_back(ExpandVectorBuildThroughStack(Node));
3202     break;
3203   }
3204   case ISD::SCALAR_TO_VECTOR:
3205     Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3206     break;
3207   case ISD::INSERT_VECTOR_ELT:
3208     Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3209                                               Node->getOperand(1),
3210                                               Node->getOperand(2), dl));
3211     break;
3212   case ISD::VECTOR_SHUFFLE: {
3213     SmallVector<int, 32> NewMask;
3214     ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3215 
3216     EVT VT = Node->getValueType(0);
3217     EVT EltVT = VT.getVectorElementType();
3218     SDValue Op0 = Node->getOperand(0);
3219     SDValue Op1 = Node->getOperand(1);
3220     if (!TLI.isTypeLegal(EltVT)) {
3221 
3222       EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3223 
3224       // BUILD_VECTOR operands are allowed to be wider than the element type.
3225       // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3226       // it.
3227       if (NewEltVT.bitsLT(EltVT)) {
3228 
3229         // Convert shuffle node.
3230         // If original node was v4i64 and the new EltVT is i32,
3231         // cast operands to v8i32 and re-build the mask.
3232 
3233         // Calculate new VT, the size of the new VT should be equal to original.
3234         EVT NewVT =
3235             EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3236                              VT.getSizeInBits() / NewEltVT.getSizeInBits());
3237         assert(NewVT.bitsEq(VT));
3238 
3239         // cast operands to new VT
3240         Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3241         Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3242 
3243         // Convert the shuffle mask
3244         unsigned int factor =
3245                          NewVT.getVectorNumElements()/VT.getVectorNumElements();
3246 
3247         // EltVT gets smaller
3248         assert(factor > 0);
3249 
3250         for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3251           if (Mask[i] < 0) {
3252             for (unsigned fi = 0; fi < factor; ++fi)
3253               NewMask.push_back(Mask[i]);
3254           }
3255           else {
3256             for (unsigned fi = 0; fi < factor; ++fi)
3257               NewMask.push_back(Mask[i]*factor+fi);
3258           }
3259         }
3260         Mask = NewMask;
3261         VT = NewVT;
3262       }
3263       EltVT = NewEltVT;
3264     }
3265     unsigned NumElems = VT.getVectorNumElements();
3266     SmallVector<SDValue, 16> Ops;
3267     for (unsigned i = 0; i != NumElems; ++i) {
3268       if (Mask[i] < 0) {
3269         Ops.push_back(DAG.getUNDEF(EltVT));
3270         continue;
3271       }
3272       unsigned Idx = Mask[i];
3273       if (Idx < NumElems)
3274         Ops.push_back(DAG.getNode(
3275             ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3276             DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3277       else
3278         Ops.push_back(DAG.getNode(
3279             ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3280             DAG.getConstant(Idx - NumElems, dl,
3281                             TLI.getVectorIdxTy(DAG.getDataLayout()))));
3282     }
3283 
3284     Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3285     // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3286     Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3287     Results.push_back(Tmp1);
3288     break;
3289   }
3290   case ISD::EXTRACT_ELEMENT: {
3291     EVT OpTy = Node->getOperand(0).getValueType();
3292     if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3293       // 1 -> Hi
3294       Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3295                          DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3296                                          TLI.getShiftAmountTy(
3297                                              Node->getOperand(0).getValueType(),
3298                                              DAG.getDataLayout())));
3299       Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3300     } else {
3301       // 0 -> Lo
3302       Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3303                          Node->getOperand(0));
3304     }
3305     Results.push_back(Tmp1);
3306     break;
3307   }
3308   case ISD::STACKSAVE:
3309     // Expand to CopyFromReg if the target set
3310     // StackPointerRegisterToSaveRestore.
3311     if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3312       Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3313                                            Node->getValueType(0)));
3314       Results.push_back(Results[0].getValue(1));
3315     } else {
3316       Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3317       Results.push_back(Node->getOperand(0));
3318     }
3319     break;
3320   case ISD::STACKRESTORE:
3321     // Expand to CopyToReg if the target set
3322     // StackPointerRegisterToSaveRestore.
3323     if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3324       Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3325                                          Node->getOperand(1)));
3326     } else {
3327       Results.push_back(Node->getOperand(0));
3328     }
3329     break;
3330   case ISD::GET_DYNAMIC_AREA_OFFSET:
3331     Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3332     Results.push_back(Results[0].getValue(0));
3333     break;
3334   case ISD::FCOPYSIGN:
3335     Results.push_back(ExpandFCOPYSIGN(Node));
3336     break;
3337   case ISD::FNEG:
3338     // Expand Y = FNEG(X) ->  Y = SUB -0.0, X
3339     Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3340     // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3341     Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3342                        Node->getOperand(0));
3343     Results.push_back(Tmp1);
3344     break;
3345   case ISD::FABS:
3346     Results.push_back(ExpandFABS(Node));
3347     break;
3348   case ISD::SMIN:
3349   case ISD::SMAX:
3350   case ISD::UMIN:
3351   case ISD::UMAX: {
3352     // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3353     ISD::CondCode Pred;
3354     switch (Node->getOpcode()) {
3355     default: llvm_unreachable("How did we get here?");
3356     case ISD::SMAX: Pred = ISD::SETGT; break;
3357     case ISD::SMIN: Pred = ISD::SETLT; break;
3358     case ISD::UMAX: Pred = ISD::SETUGT; break;
3359     case ISD::UMIN: Pred = ISD::SETULT; break;
3360     }
3361     Tmp1 = Node->getOperand(0);
3362     Tmp2 = Node->getOperand(1);
3363     Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3364     Results.push_back(Tmp1);
3365     break;
3366   }
3367 
3368   case ISD::FSIN:
3369   case ISD::FCOS: {
3370     EVT VT = Node->getValueType(0);
3371     // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3372     // fcos which share the same operand and both are used.
3373     if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3374          canCombineSinCosLibcall(Node, TLI, TM))
3375         && useSinCos(Node)) {
3376       SDVTList VTs = DAG.getVTList(VT, VT);
3377       Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3378       if (Node->getOpcode() == ISD::FCOS)
3379         Tmp1 = Tmp1.getValue(1);
3380       Results.push_back(Tmp1);
3381     }
3382     break;
3383   }
3384   case ISD::FMAD:
3385     llvm_unreachable("Illegal fmad should never be formed");
3386 
3387   case ISD::FP16_TO_FP:
3388     if (Node->getValueType(0) != MVT::f32) {
3389       // We can extend to types bigger than f32 in two steps without changing
3390       // the result. Since "f16 -> f32" is much more commonly available, give
3391       // CodeGen the option of emitting that before resorting to a libcall.
3392       SDValue Res =
3393           DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3394       Results.push_back(
3395           DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3396     }
3397     break;
3398   case ISD::FP_TO_FP16:
3399     if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3400       SDValue Op = Node->getOperand(0);
3401       MVT SVT = Op.getSimpleValueType();
3402       if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3403           TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3404         // Under fastmath, we can expand this node into a fround followed by
3405         // a float-half conversion.
3406         SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3407                                        DAG.getIntPtrConstant(0, dl));
3408         Results.push_back(
3409             DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3410       }
3411     }
3412     break;
3413   case ISD::ConstantFP: {
3414     ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3415     // Check to see if this FP immediate is already legal.
3416     // If this is a legal constant, turn it into a TargetConstantFP node.
3417     if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3418       Results.push_back(ExpandConstantFP(CFP, true));
3419     break;
3420   }
3421   case ISD::Constant: {
3422     ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3423     Results.push_back(ExpandConstant(CP));
3424     break;
3425   }
3426   case ISD::FSUB: {
3427     EVT VT = Node->getValueType(0);
3428     if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3429         TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3430       const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(Node)->Flags;
3431       Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3432       Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3433       Results.push_back(Tmp1);
3434     }
3435     break;
3436   }
3437   case ISD::SUB: {
3438     EVT VT = Node->getValueType(0);
3439     assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3440            TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3441            "Don't know how to expand this subtraction!");
3442     Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3443                DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3444                                VT));
3445     Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3446     Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3447     break;
3448   }
3449   case ISD::UREM:
3450   case ISD::SREM: {
3451     EVT VT = Node->getValueType(0);
3452     bool isSigned = Node->getOpcode() == ISD::SREM;
3453     unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3454     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3455     Tmp2 = Node->getOperand(0);
3456     Tmp3 = Node->getOperand(1);
3457     if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3458       SDVTList VTs = DAG.getVTList(VT, VT);
3459       Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3460       Results.push_back(Tmp1);
3461     } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3462       // X % Y -> X-X/Y*Y
3463       Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3464       Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3465       Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3466       Results.push_back(Tmp1);
3467     }
3468     break;
3469   }
3470   case ISD::UDIV:
3471   case ISD::SDIV: {
3472     bool isSigned = Node->getOpcode() == ISD::SDIV;
3473     unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3474     EVT VT = Node->getValueType(0);
3475     if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3476       SDVTList VTs = DAG.getVTList(VT, VT);
3477       Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3478                          Node->getOperand(1));
3479       Results.push_back(Tmp1);
3480     }
3481     break;
3482   }
3483   case ISD::MULHU:
3484   case ISD::MULHS: {
3485     unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3486                                                               ISD::SMUL_LOHI;
3487     EVT VT = Node->getValueType(0);
3488     SDVTList VTs = DAG.getVTList(VT, VT);
3489     assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3490            "If this wasn't legal, it shouldn't have been created!");
3491     Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3492                        Node->getOperand(1));
3493     Results.push_back(Tmp1.getValue(1));
3494     break;
3495   }
3496   case ISD::MUL: {
3497     EVT VT = Node->getValueType(0);
3498     SDVTList VTs = DAG.getVTList(VT, VT);
3499     // See if multiply or divide can be lowered using two-result operations.
3500     // We just need the low half of the multiply; try both the signed
3501     // and unsigned forms. If the target supports both SMUL_LOHI and
3502     // UMUL_LOHI, form a preference by checking which forms of plain
3503     // MULH it supports.
3504     bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3505     bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3506     bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3507     bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3508     unsigned OpToUse = 0;
3509     if (HasSMUL_LOHI && !HasMULHS) {
3510       OpToUse = ISD::SMUL_LOHI;
3511     } else if (HasUMUL_LOHI && !HasMULHU) {
3512       OpToUse = ISD::UMUL_LOHI;
3513     } else if (HasSMUL_LOHI) {
3514       OpToUse = ISD::SMUL_LOHI;
3515     } else if (HasUMUL_LOHI) {
3516       OpToUse = ISD::UMUL_LOHI;
3517     }
3518     if (OpToUse) {
3519       Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3520                                     Node->getOperand(1)));
3521       break;
3522     }
3523 
3524     SDValue Lo, Hi;
3525     EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3526     if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3527         TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3528         TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3529         TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3530         TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3531       Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3532       Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3533       SDValue Shift =
3534           DAG.getConstant(HalfType.getSizeInBits(), dl,
3535                           TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3536       Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3537       Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3538     }
3539     break;
3540   }
3541   case ISD::SADDO:
3542   case ISD::SSUBO: {
3543     SDValue LHS = Node->getOperand(0);
3544     SDValue RHS = Node->getOperand(1);
3545     SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3546                               ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3547                               LHS, RHS);
3548     Results.push_back(Sum);
3549     EVT ResultType = Node->getValueType(1);
3550     EVT OType = getSetCCResultType(Node->getValueType(0));
3551 
3552     SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3553 
3554     //   LHSSign -> LHS >= 0
3555     //   RHSSign -> RHS >= 0
3556     //   SumSign -> Sum >= 0
3557     //
3558     //   Add:
3559     //   Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3560     //   Sub:
3561     //   Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3562     //
3563     SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3564     SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3565     SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3566                                       Node->getOpcode() == ISD::SADDO ?
3567                                       ISD::SETEQ : ISD::SETNE);
3568 
3569     SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3570     SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3571 
3572     SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3573     Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3574     break;
3575   }
3576   case ISD::UADDO:
3577   case ISD::USUBO: {
3578     SDValue LHS = Node->getOperand(0);
3579     SDValue RHS = Node->getOperand(1);
3580     SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3581                               ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3582                               LHS, RHS);
3583     Results.push_back(Sum);
3584 
3585     EVT ResultType = Node->getValueType(1);
3586     EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3587     ISD::CondCode CC
3588       = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3589     SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3590 
3591     Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3592     break;
3593   }
3594   case ISD::UMULO:
3595   case ISD::SMULO: {
3596     EVT VT = Node->getValueType(0);
3597     EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3598     SDValue LHS = Node->getOperand(0);
3599     SDValue RHS = Node->getOperand(1);
3600     SDValue BottomHalf;
3601     SDValue TopHalf;
3602     static const unsigned Ops[2][3] =
3603         { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3604           { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3605     bool isSigned = Node->getOpcode() == ISD::SMULO;
3606     if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3607       BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3608       TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3609     } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3610       BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3611                                RHS);
3612       TopHalf = BottomHalf.getValue(1);
3613     } else if (TLI.isTypeLegal(WideVT)) {
3614       LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3615       RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3616       Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3617       BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3618                                DAG.getIntPtrConstant(0, dl));
3619       TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3620                             DAG.getIntPtrConstant(1, dl));
3621     } else {
3622       // We can fall back to a libcall with an illegal type for the MUL if we
3623       // have a libcall big enough.
3624       // Also, we can fall back to a division in some cases, but that's a big
3625       // performance hit in the general case.
3626       RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3627       if (WideVT == MVT::i16)
3628         LC = RTLIB::MUL_I16;
3629       else if (WideVT == MVT::i32)
3630         LC = RTLIB::MUL_I32;
3631       else if (WideVT == MVT::i64)
3632         LC = RTLIB::MUL_I64;
3633       else if (WideVT == MVT::i128)
3634         LC = RTLIB::MUL_I128;
3635       assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3636 
3637       // The high part is obtained by SRA'ing all but one of the bits of low
3638       // part.
3639       unsigned LoSize = VT.getSizeInBits();
3640       SDValue HiLHS =
3641           DAG.getNode(ISD::SRA, dl, VT, RHS,
3642                       DAG.getConstant(LoSize - 1, dl,
3643                                       TLI.getPointerTy(DAG.getDataLayout())));
3644       SDValue HiRHS =
3645           DAG.getNode(ISD::SRA, dl, VT, LHS,
3646                       DAG.getConstant(LoSize - 1, dl,
3647                                       TLI.getPointerTy(DAG.getDataLayout())));
3648 
3649       // Here we're passing the 2 arguments explicitly as 4 arguments that are
3650       // pre-lowered to the correct types. This all depends upon WideVT not
3651       // being a legal type for the architecture and thus has to be split to
3652       // two arguments.
3653       SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3654       SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3655       BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3656                                DAG.getIntPtrConstant(0, dl));
3657       TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3658                             DAG.getIntPtrConstant(1, dl));
3659       // Ret is a node with an illegal type. Because such things are not
3660       // generally permitted during this phase of legalization, make sure the
3661       // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3662       // folded.
3663       assert(Ret->use_empty() &&
3664              "Unexpected uses of illegally type from expanded lib call.");
3665     }
3666 
3667     if (isSigned) {
3668       Tmp1 = DAG.getConstant(
3669           VT.getSizeInBits() - 1, dl,
3670           TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3671       Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3672       TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3673                              ISD::SETNE);
3674     } else {
3675       TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3676                              DAG.getConstant(0, dl, VT), ISD::SETNE);
3677     }
3678     Results.push_back(BottomHalf);
3679     Results.push_back(TopHalf);
3680     break;
3681   }
3682   case ISD::BUILD_PAIR: {
3683     EVT PairTy = Node->getValueType(0);
3684     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3685     Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3686     Tmp2 = DAG.getNode(
3687         ISD::SHL, dl, PairTy, Tmp2,
3688         DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3689                         TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3690     Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3691     break;
3692   }
3693   case ISD::SELECT:
3694     Tmp1 = Node->getOperand(0);
3695     Tmp2 = Node->getOperand(1);
3696     Tmp3 = Node->getOperand(2);
3697     if (Tmp1.getOpcode() == ISD::SETCC) {
3698       Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3699                              Tmp2, Tmp3,
3700                              cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3701     } else {
3702       Tmp1 = DAG.getSelectCC(dl, Tmp1,
3703                              DAG.getConstant(0, dl, Tmp1.getValueType()),
3704                              Tmp2, Tmp3, ISD::SETNE);
3705     }
3706     Results.push_back(Tmp1);
3707     break;
3708   case ISD::BR_JT: {
3709     SDValue Chain = Node->getOperand(0);
3710     SDValue Table = Node->getOperand(1);
3711     SDValue Index = Node->getOperand(2);
3712 
3713     EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
3714 
3715     const DataLayout &TD = DAG.getDataLayout();
3716     unsigned EntrySize =
3717       DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3718 
3719     Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3720                         DAG.getConstant(EntrySize, dl, Index.getValueType()));
3721     SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3722                                Index, Table);
3723 
3724     EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3725     SDValue LD = DAG.getExtLoad(
3726         ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3727         MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT,
3728         false, false, false, 0);
3729     Addr = LD;
3730     if (TM.getRelocationModel() == Reloc::PIC_) {
3731       // For PIC, the sequence is:
3732       // BRIND(load(Jumptable + index) + RelocBase)
3733       // RelocBase can be JumpTable, GOT or some sort of global base.
3734       Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3735                           TLI.getPICJumpTableRelocBase(Table, DAG));
3736     }
3737     Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3738     Results.push_back(Tmp1);
3739     break;
3740   }
3741   case ISD::BRCOND:
3742     // Expand brcond's setcc into its constituent parts and create a BR_CC
3743     // Node.
3744     Tmp1 = Node->getOperand(0);
3745     Tmp2 = Node->getOperand(1);
3746     if (Tmp2.getOpcode() == ISD::SETCC) {
3747       Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3748                          Tmp1, Tmp2.getOperand(2),
3749                          Tmp2.getOperand(0), Tmp2.getOperand(1),
3750                          Node->getOperand(2));
3751     } else {
3752       // We test only the i1 bit.  Skip the AND if UNDEF.
3753       Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3754         DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3755                     DAG.getConstant(1, dl, Tmp2.getValueType()));
3756       Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3757                          DAG.getCondCode(ISD::SETNE), Tmp3,
3758                          DAG.getConstant(0, dl, Tmp3.getValueType()),
3759                          Node->getOperand(2));
3760     }
3761     Results.push_back(Tmp1);
3762     break;
3763   case ISD::SETCC: {
3764     Tmp1 = Node->getOperand(0);
3765     Tmp2 = Node->getOperand(1);
3766     Tmp3 = Node->getOperand(2);
3767     bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3768                                            Tmp3, NeedInvert, dl);
3769 
3770     if (Legalized) {
3771       // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3772       // condition code, create a new SETCC node.
3773       if (Tmp3.getNode())
3774         Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3775                            Tmp1, Tmp2, Tmp3);
3776 
3777       // If we expanded the SETCC by inverting the condition code, then wrap
3778       // the existing SETCC in a NOT to restore the intended condition.
3779       if (NeedInvert)
3780         Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3781 
3782       Results.push_back(Tmp1);
3783       break;
3784     }
3785 
3786     // Otherwise, SETCC for the given comparison type must be completely
3787     // illegal; expand it into a SELECT_CC.
3788     EVT VT = Node->getValueType(0);
3789     int TrueValue;
3790     switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3791     case TargetLowering::ZeroOrOneBooleanContent:
3792     case TargetLowering::UndefinedBooleanContent:
3793       TrueValue = 1;
3794       break;
3795     case TargetLowering::ZeroOrNegativeOneBooleanContent:
3796       TrueValue = -1;
3797       break;
3798     }
3799     Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3800                        DAG.getConstant(TrueValue, dl, VT),
3801                        DAG.getConstant(0, dl, VT),
3802                        Tmp3);
3803     Results.push_back(Tmp1);
3804     break;
3805   }
3806   case ISD::SELECT_CC: {
3807     Tmp1 = Node->getOperand(0);   // LHS
3808     Tmp2 = Node->getOperand(1);   // RHS
3809     Tmp3 = Node->getOperand(2);   // True
3810     Tmp4 = Node->getOperand(3);   // False
3811     EVT VT = Node->getValueType(0);
3812     SDValue CC = Node->getOperand(4);
3813     ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3814 
3815     if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3816       // If the condition code is legal, then we need to expand this
3817       // node using SETCC and SELECT.
3818       EVT CmpVT = Tmp1.getValueType();
3819       assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3820              "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3821              "expanded.");
3822       EVT CCVT =
3823           TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3824       SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3825       Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3826       break;
3827     }
3828 
3829     // SELECT_CC is legal, so the condition code must not be.
3830     bool Legalized = false;
3831     // Try to legalize by inverting the condition.  This is for targets that
3832     // might support an ordered version of a condition, but not the unordered
3833     // version (or vice versa).
3834     ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3835                                                Tmp1.getValueType().isInteger());
3836     if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3837       // Use the new condition code and swap true and false
3838       Legalized = true;
3839       Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3840     } else {
3841       // If The inverse is not legal, then try to swap the arguments using
3842       // the inverse condition code.
3843       ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3844       if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3845         // The swapped inverse condition is legal, so swap true and false,
3846         // lhs and rhs.
3847         Legalized = true;
3848         Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3849       }
3850     }
3851 
3852     if (!Legalized) {
3853       Legalized = LegalizeSetCCCondCode(
3854           getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3855           dl);
3856 
3857       assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3858 
3859       // If we expanded the SETCC by inverting the condition code, then swap
3860       // the True/False operands to match.
3861       if (NeedInvert)
3862         std::swap(Tmp3, Tmp4);
3863 
3864       // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3865       // condition code, create a new SELECT_CC node.
3866       if (CC.getNode()) {
3867         Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3868                            Tmp1, Tmp2, Tmp3, Tmp4, CC);
3869       } else {
3870         Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3871         CC = DAG.getCondCode(ISD::SETNE);
3872         Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3873                            Tmp2, Tmp3, Tmp4, CC);
3874       }
3875     }
3876     Results.push_back(Tmp1);
3877     break;
3878   }
3879   case ISD::BR_CC: {
3880     Tmp1 = Node->getOperand(0);              // Chain
3881     Tmp2 = Node->getOperand(2);              // LHS
3882     Tmp3 = Node->getOperand(3);              // RHS
3883     Tmp4 = Node->getOperand(1);              // CC
3884 
3885     bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3886         Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3887     (void)Legalized;
3888     assert(Legalized && "Can't legalize BR_CC with legal condition!");
3889 
3890     // If we expanded the SETCC by inverting the condition code, then wrap
3891     // the existing SETCC in a NOT to restore the intended condition.
3892     if (NeedInvert)
3893       Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3894 
3895     // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3896     // node.
3897     if (Tmp4.getNode()) {
3898       Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3899                          Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3900     } else {
3901       Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3902       Tmp4 = DAG.getCondCode(ISD::SETNE);
3903       Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3904                          Tmp2, Tmp3, Node->getOperand(4));
3905     }
3906     Results.push_back(Tmp1);
3907     break;
3908   }
3909   case ISD::BUILD_VECTOR:
3910     Results.push_back(ExpandBUILD_VECTOR(Node));
3911     break;
3912   case ISD::SRA:
3913   case ISD::SRL:
3914   case ISD::SHL: {
3915     // Scalarize vector SRA/SRL/SHL.
3916     EVT VT = Node->getValueType(0);
3917     assert(VT.isVector() && "Unable to legalize non-vector shift");
3918     assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3919     unsigned NumElem = VT.getVectorNumElements();
3920 
3921     SmallVector<SDValue, 8> Scalars;
3922     for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3923       SDValue Ex = DAG.getNode(
3924           ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3925           DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3926       SDValue Sh = DAG.getNode(
3927           ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3928           DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3929       Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3930                                     VT.getScalarType(), Ex, Sh));
3931     }
3932     SDValue Result =
3933       DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
3934     ReplaceNode(SDValue(Node, 0), Result);
3935     break;
3936   }
3937   case ISD::GLOBAL_OFFSET_TABLE:
3938   case ISD::GlobalAddress:
3939   case ISD::GlobalTLSAddress:
3940   case ISD::ExternalSymbol:
3941   case ISD::ConstantPool:
3942   case ISD::JumpTable:
3943   case ISD::INTRINSIC_W_CHAIN:
3944   case ISD::INTRINSIC_WO_CHAIN:
3945   case ISD::INTRINSIC_VOID:
3946     // FIXME: Custom lowering for these operations shouldn't return null!
3947     break;
3948   }
3949 
3950   // Replace the original node with the legalized result.
3951   if (Results.empty())
3952     return false;
3953 
3954   ReplaceNode(Node, Results.data());
3955   return true;
3956 }
3957 
ConvertNodeToLibcall(SDNode * Node)3958 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3959   SmallVector<SDValue, 8> Results;
3960   SDLoc dl(Node);
3961   SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3962   unsigned Opc = Node->getOpcode();
3963   switch (Opc) {
3964   case ISD::ATOMIC_FENCE: {
3965     // If the target didn't lower this, lower it to '__sync_synchronize()' call
3966     // FIXME: handle "fence singlethread" more efficiently.
3967     TargetLowering::ArgListTy Args;
3968 
3969     TargetLowering::CallLoweringInfo CLI(DAG);
3970     CLI.setDebugLoc(dl)
3971         .setChain(Node->getOperand(0))
3972         .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3973                    DAG.getExternalSymbol("__sync_synchronize",
3974                                          TLI.getPointerTy(DAG.getDataLayout())),
3975                    std::move(Args), 0);
3976 
3977     std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3978 
3979     Results.push_back(CallResult.second);
3980     break;
3981   }
3982   // By default, atomic intrinsics are marked Legal and lowered. Targets
3983   // which don't support them directly, however, may want libcalls, in which
3984   // case they mark them Expand, and we get here.
3985   case ISD::ATOMIC_SWAP:
3986   case ISD::ATOMIC_LOAD_ADD:
3987   case ISD::ATOMIC_LOAD_SUB:
3988   case ISD::ATOMIC_LOAD_AND:
3989   case ISD::ATOMIC_LOAD_OR:
3990   case ISD::ATOMIC_LOAD_XOR:
3991   case ISD::ATOMIC_LOAD_NAND:
3992   case ISD::ATOMIC_LOAD_MIN:
3993   case ISD::ATOMIC_LOAD_MAX:
3994   case ISD::ATOMIC_LOAD_UMIN:
3995   case ISD::ATOMIC_LOAD_UMAX:
3996   case ISD::ATOMIC_CMP_SWAP: {
3997     MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
3998     RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
3999     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
4000 
4001     std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
4002     Results.push_back(Tmp.first);
4003     Results.push_back(Tmp.second);
4004     break;
4005   }
4006   case ISD::TRAP: {
4007     // If this operation is not supported, lower it to 'abort()' call
4008     TargetLowering::ArgListTy Args;
4009     TargetLowering::CallLoweringInfo CLI(DAG);
4010     CLI.setDebugLoc(dl)
4011         .setChain(Node->getOperand(0))
4012         .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
4013                    DAG.getExternalSymbol("abort",
4014                                          TLI.getPointerTy(DAG.getDataLayout())),
4015                    std::move(Args), 0);
4016     std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4017 
4018     Results.push_back(CallResult.second);
4019     break;
4020   }
4021   case ISD::FMINNUM:
4022     Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
4023                                       RTLIB::FMIN_F80, RTLIB::FMIN_F128,
4024                                       RTLIB::FMIN_PPCF128));
4025     break;
4026   case ISD::FMAXNUM:
4027     Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
4028                                       RTLIB::FMAX_F80, RTLIB::FMAX_F128,
4029                                       RTLIB::FMAX_PPCF128));
4030     break;
4031   case ISD::FSQRT:
4032     Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
4033                                       RTLIB::SQRT_F80, RTLIB::SQRT_F128,
4034                                       RTLIB::SQRT_PPCF128));
4035     break;
4036   case ISD::FSIN:
4037     Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
4038                                       RTLIB::SIN_F80, RTLIB::SIN_F128,
4039                                       RTLIB::SIN_PPCF128));
4040     break;
4041   case ISD::FCOS:
4042     Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
4043                                       RTLIB::COS_F80, RTLIB::COS_F128,
4044                                       RTLIB::COS_PPCF128));
4045     break;
4046   case ISD::FSINCOS:
4047     // Expand into sincos libcall.
4048     ExpandSinCosLibCall(Node, Results);
4049     break;
4050   case ISD::FLOG:
4051     Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
4052                                       RTLIB::LOG_F80, RTLIB::LOG_F128,
4053                                       RTLIB::LOG_PPCF128));
4054     break;
4055   case ISD::FLOG2:
4056     Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
4057                                       RTLIB::LOG2_F80, RTLIB::LOG2_F128,
4058                                       RTLIB::LOG2_PPCF128));
4059     break;
4060   case ISD::FLOG10:
4061     Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
4062                                       RTLIB::LOG10_F80, RTLIB::LOG10_F128,
4063                                       RTLIB::LOG10_PPCF128));
4064     break;
4065   case ISD::FEXP:
4066     Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
4067                                       RTLIB::EXP_F80, RTLIB::EXP_F128,
4068                                       RTLIB::EXP_PPCF128));
4069     break;
4070   case ISD::FEXP2:
4071     Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
4072                                       RTLIB::EXP2_F80, RTLIB::EXP2_F128,
4073                                       RTLIB::EXP2_PPCF128));
4074     break;
4075   case ISD::FTRUNC:
4076     Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
4077                                       RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
4078                                       RTLIB::TRUNC_PPCF128));
4079     break;
4080   case ISD::FFLOOR:
4081     Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
4082                                       RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
4083                                       RTLIB::FLOOR_PPCF128));
4084     break;
4085   case ISD::FCEIL:
4086     Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
4087                                       RTLIB::CEIL_F80, RTLIB::CEIL_F128,
4088                                       RTLIB::CEIL_PPCF128));
4089     break;
4090   case ISD::FRINT:
4091     Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
4092                                       RTLIB::RINT_F80, RTLIB::RINT_F128,
4093                                       RTLIB::RINT_PPCF128));
4094     break;
4095   case ISD::FNEARBYINT:
4096     Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
4097                                       RTLIB::NEARBYINT_F64,
4098                                       RTLIB::NEARBYINT_F80,
4099                                       RTLIB::NEARBYINT_F128,
4100                                       RTLIB::NEARBYINT_PPCF128));
4101     break;
4102   case ISD::FROUND:
4103     Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
4104                                       RTLIB::ROUND_F64,
4105                                       RTLIB::ROUND_F80,
4106                                       RTLIB::ROUND_F128,
4107                                       RTLIB::ROUND_PPCF128));
4108     break;
4109   case ISD::FPOWI:
4110     Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
4111                                       RTLIB::POWI_F80, RTLIB::POWI_F128,
4112                                       RTLIB::POWI_PPCF128));
4113     break;
4114   case ISD::FPOW:
4115     Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
4116                                       RTLIB::POW_F80, RTLIB::POW_F128,
4117                                       RTLIB::POW_PPCF128));
4118     break;
4119   case ISD::FDIV:
4120     Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4121                                       RTLIB::DIV_F80, RTLIB::DIV_F128,
4122                                       RTLIB::DIV_PPCF128));
4123     break;
4124   case ISD::FREM:
4125     Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4126                                       RTLIB::REM_F80, RTLIB::REM_F128,
4127                                       RTLIB::REM_PPCF128));
4128     break;
4129   case ISD::FMA:
4130     Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4131                                       RTLIB::FMA_F80, RTLIB::FMA_F128,
4132                                       RTLIB::FMA_PPCF128));
4133     break;
4134   case ISD::FADD:
4135     Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4136                                       RTLIB::ADD_F80, RTLIB::ADD_F128,
4137                                       RTLIB::ADD_PPCF128));
4138     break;
4139   case ISD::FMUL:
4140     Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4141                                       RTLIB::MUL_F80, RTLIB::MUL_F128,
4142                                       RTLIB::MUL_PPCF128));
4143     break;
4144   case ISD::FP16_TO_FP:
4145     if (Node->getValueType(0) == MVT::f32) {
4146       Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4147     }
4148     break;
4149   case ISD::FP_TO_FP16: {
4150     RTLIB::Libcall LC =
4151         RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4152     assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4153     Results.push_back(ExpandLibCall(LC, Node, false));
4154     break;
4155   }
4156   case ISD::FSUB:
4157     Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4158                                       RTLIB::SUB_F80, RTLIB::SUB_F128,
4159                                       RTLIB::SUB_PPCF128));
4160     break;
4161   case ISD::SREM:
4162     Results.push_back(ExpandIntLibCall(Node, true,
4163                                        RTLIB::SREM_I8,
4164                                        RTLIB::SREM_I16, RTLIB::SREM_I32,
4165                                        RTLIB::SREM_I64, RTLIB::SREM_I128));
4166     break;
4167   case ISD::UREM:
4168     Results.push_back(ExpandIntLibCall(Node, false,
4169                                        RTLIB::UREM_I8,
4170                                        RTLIB::UREM_I16, RTLIB::UREM_I32,
4171                                        RTLIB::UREM_I64, RTLIB::UREM_I128));
4172     break;
4173   case ISD::SDIV:
4174     Results.push_back(ExpandIntLibCall(Node, true,
4175                                        RTLIB::SDIV_I8,
4176                                        RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4177                                        RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4178     break;
4179   case ISD::UDIV:
4180     Results.push_back(ExpandIntLibCall(Node, false,
4181                                        RTLIB::UDIV_I8,
4182                                        RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4183                                        RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4184     break;
4185   case ISD::SDIVREM:
4186   case ISD::UDIVREM:
4187     // Expand into divrem libcall
4188     ExpandDivRemLibCall(Node, Results);
4189     break;
4190   case ISD::MUL:
4191     Results.push_back(ExpandIntLibCall(Node, false,
4192                                        RTLIB::MUL_I8,
4193                                        RTLIB::MUL_I16, RTLIB::MUL_I32,
4194                                        RTLIB::MUL_I64, RTLIB::MUL_I128));
4195     break;
4196   }
4197 
4198   // Replace the original node with the legalized result.
4199   if (!Results.empty())
4200     ReplaceNode(Node, Results.data());
4201 }
4202 
4203 // Determine the vector type to use in place of an original scalar element when
4204 // promoting equally sized vectors.
getPromotedVectorElementType(const TargetLowering & TLI,MVT EltVT,MVT NewEltVT)4205 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4206                                         MVT EltVT, MVT NewEltVT) {
4207   unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4208   MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4209   assert(TLI.isTypeLegal(MidVT) && "unexpected");
4210   return MidVT;
4211 }
4212 
PromoteNode(SDNode * Node)4213 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4214   SmallVector<SDValue, 8> Results;
4215   MVT OVT = Node->getSimpleValueType(0);
4216   if (Node->getOpcode() == ISD::UINT_TO_FP ||
4217       Node->getOpcode() == ISD::SINT_TO_FP ||
4218       Node->getOpcode() == ISD::SETCC ||
4219       Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4220       Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4221     OVT = Node->getOperand(0).getSimpleValueType();
4222   }
4223   if (Node->getOpcode() == ISD::BR_CC)
4224     OVT = Node->getOperand(2).getSimpleValueType();
4225   MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4226   SDLoc dl(Node);
4227   SDValue Tmp1, Tmp2, Tmp3;
4228   switch (Node->getOpcode()) {
4229   case ISD::CTTZ:
4230   case ISD::CTTZ_ZERO_UNDEF:
4231   case ISD::CTLZ:
4232   case ISD::CTLZ_ZERO_UNDEF:
4233   case ISD::CTPOP:
4234     // Zero extend the argument.
4235     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4236     // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4237     // already the correct result.
4238     Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4239     if (Node->getOpcode() == ISD::CTTZ) {
4240       // FIXME: This should set a bit in the zero extended value instead.
4241       Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4242                           Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4243                           ISD::SETEQ);
4244       Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4245                            DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4246     } else if (Node->getOpcode() == ISD::CTLZ ||
4247                Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4248       // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4249       Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4250                           DAG.getConstant(NVT.getSizeInBits() -
4251                                           OVT.getSizeInBits(), dl, NVT));
4252     }
4253     Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4254     break;
4255   case ISD::BSWAP: {
4256     unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4257     Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4258     Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4259     Tmp1 = DAG.getNode(
4260         ISD::SRL, dl, NVT, Tmp1,
4261         DAG.getConstant(DiffBits, dl,
4262                         TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4263     Results.push_back(Tmp1);
4264     break;
4265   }
4266   case ISD::FP_TO_UINT:
4267   case ISD::FP_TO_SINT:
4268     Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4269                                  Node->getOpcode() == ISD::FP_TO_SINT, dl);
4270     Results.push_back(Tmp1);
4271     break;
4272   case ISD::UINT_TO_FP:
4273   case ISD::SINT_TO_FP:
4274     Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4275                                  Node->getOpcode() == ISD::SINT_TO_FP, dl);
4276     Results.push_back(Tmp1);
4277     break;
4278   case ISD::VAARG: {
4279     SDValue Chain = Node->getOperand(0); // Get the chain.
4280     SDValue Ptr = Node->getOperand(1); // Get the pointer.
4281 
4282     unsigned TruncOp;
4283     if (OVT.isVector()) {
4284       TruncOp = ISD::BITCAST;
4285     } else {
4286       assert(OVT.isInteger()
4287         && "VAARG promotion is supported only for vectors or integer types");
4288       TruncOp = ISD::TRUNCATE;
4289     }
4290 
4291     // Perform the larger operation, then convert back
4292     Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4293              Node->getConstantOperandVal(3));
4294     Chain = Tmp1.getValue(1);
4295 
4296     Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4297 
4298     // Modified the chain result - switch anything that used the old chain to
4299     // use the new one.
4300     DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4301     DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4302     if (UpdatedNodes) {
4303       UpdatedNodes->insert(Tmp2.getNode());
4304       UpdatedNodes->insert(Chain.getNode());
4305     }
4306     ReplacedNode(Node);
4307     break;
4308   }
4309   case ISD::AND:
4310   case ISD::OR:
4311   case ISD::XOR: {
4312     unsigned ExtOp, TruncOp;
4313     if (OVT.isVector()) {
4314       ExtOp   = ISD::BITCAST;
4315       TruncOp = ISD::BITCAST;
4316     } else {
4317       assert(OVT.isInteger() && "Cannot promote logic operation");
4318       ExtOp   = ISD::ANY_EXTEND;
4319       TruncOp = ISD::TRUNCATE;
4320     }
4321     // Promote each of the values to the new type.
4322     Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4323     Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4324     // Perform the larger operation, then convert back
4325     Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4326     Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4327     break;
4328   }
4329   case ISD::SELECT: {
4330     unsigned ExtOp, TruncOp;
4331     if (Node->getValueType(0).isVector() ||
4332         Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4333       ExtOp   = ISD::BITCAST;
4334       TruncOp = ISD::BITCAST;
4335     } else if (Node->getValueType(0).isInteger()) {
4336       ExtOp   = ISD::ANY_EXTEND;
4337       TruncOp = ISD::TRUNCATE;
4338     } else {
4339       ExtOp   = ISD::FP_EXTEND;
4340       TruncOp = ISD::FP_ROUND;
4341     }
4342     Tmp1 = Node->getOperand(0);
4343     // Promote each of the values to the new type.
4344     Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4345     Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4346     // Perform the larger operation, then round down.
4347     Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4348     if (TruncOp != ISD::FP_ROUND)
4349       Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4350     else
4351       Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4352                          DAG.getIntPtrConstant(0, dl));
4353     Results.push_back(Tmp1);
4354     break;
4355   }
4356   case ISD::VECTOR_SHUFFLE: {
4357     ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4358 
4359     // Cast the two input vectors.
4360     Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4361     Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4362 
4363     // Convert the shuffle mask to the right # elements.
4364     Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4365     Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4366     Results.push_back(Tmp1);
4367     break;
4368   }
4369   case ISD::SETCC: {
4370     unsigned ExtOp = ISD::FP_EXTEND;
4371     if (NVT.isInteger()) {
4372       ISD::CondCode CCCode =
4373         cast<CondCodeSDNode>(Node->getOperand(2))->get();
4374       ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4375     }
4376     Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4377     Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4378     Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4379                                   Tmp1, Tmp2, Node->getOperand(2)));
4380     break;
4381   }
4382   case ISD::BR_CC: {
4383     unsigned ExtOp = ISD::FP_EXTEND;
4384     if (NVT.isInteger()) {
4385       ISD::CondCode CCCode =
4386         cast<CondCodeSDNode>(Node->getOperand(1))->get();
4387       ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4388     }
4389     Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4390     Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4391     Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4392                                   Node->getOperand(0), Node->getOperand(1),
4393                                   Tmp1, Tmp2, Node->getOperand(4)));
4394     break;
4395   }
4396   case ISD::FADD:
4397   case ISD::FSUB:
4398   case ISD::FMUL:
4399   case ISD::FDIV:
4400   case ISD::FREM:
4401   case ISD::FMINNUM:
4402   case ISD::FMAXNUM:
4403   case ISD::FPOW: {
4404     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4405     Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4406     Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4407                        Node->getFlags());
4408     Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4409                                   Tmp3, DAG.getIntPtrConstant(0, dl)));
4410     break;
4411   }
4412   case ISD::FMA: {
4413     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4414     Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4415     Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4416     Results.push_back(
4417         DAG.getNode(ISD::FP_ROUND, dl, OVT,
4418                     DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4419                     DAG.getIntPtrConstant(0, dl)));
4420     break;
4421   }
4422   case ISD::FCOPYSIGN:
4423   case ISD::FPOWI: {
4424     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4425     Tmp2 = Node->getOperand(1);
4426     Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4427 
4428     // fcopysign doesn't change anything but the sign bit, so
4429     //   (fp_round (fcopysign (fpext a), b))
4430     // is as precise as
4431     //   (fp_round (fpext a))
4432     // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4433     const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4434     Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4435                                   Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4436     break;
4437   }
4438   case ISD::FFLOOR:
4439   case ISD::FCEIL:
4440   case ISD::FRINT:
4441   case ISD::FNEARBYINT:
4442   case ISD::FROUND:
4443   case ISD::FTRUNC:
4444   case ISD::FNEG:
4445   case ISD::FSQRT:
4446   case ISD::FSIN:
4447   case ISD::FCOS:
4448   case ISD::FLOG:
4449   case ISD::FLOG2:
4450   case ISD::FLOG10:
4451   case ISD::FABS:
4452   case ISD::FEXP:
4453   case ISD::FEXP2: {
4454     Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4455     Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4456     Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4457                                   Tmp2, DAG.getIntPtrConstant(0, dl)));
4458     break;
4459   }
4460   case ISD::BUILD_VECTOR: {
4461     MVT EltVT = OVT.getVectorElementType();
4462     MVT NewEltVT = NVT.getVectorElementType();
4463 
4464     // Handle bitcasts to a different vector type with the same total bit size
4465     //
4466     // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4467     //  =>
4468     //  v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4469 
4470     assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4471            "Invalid promote type for build_vector");
4472     assert(NewEltVT.bitsLT(EltVT) && "not handled");
4473 
4474     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4475 
4476     SmallVector<SDValue, 8> NewOps;
4477     for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4478       SDValue Op = Node->getOperand(I);
4479       NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4480     }
4481 
4482     SDLoc SL(Node);
4483     SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4484     SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4485     Results.push_back(CvtVec);
4486     break;
4487   }
4488   case ISD::EXTRACT_VECTOR_ELT: {
4489     MVT EltVT = OVT.getVectorElementType();
4490     MVT NewEltVT = NVT.getVectorElementType();
4491 
4492     // Handle bitcasts to a different vector type with the same total bit size.
4493     //
4494     // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4495     //  =>
4496     //  v4i32:castx = bitcast x:v2i64
4497     //
4498     // i64 = bitcast
4499     //   (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4500     //                       (i32 (extract_vector_elt castx, (2 * y + 1)))
4501     //
4502 
4503     assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4504            "Invalid promote type for extract_vector_elt");
4505     assert(NewEltVT.bitsLT(EltVT) && "not handled");
4506 
4507     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4508     unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4509 
4510     SDValue Idx = Node->getOperand(1);
4511     EVT IdxVT = Idx.getValueType();
4512     SDLoc SL(Node);
4513     SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4514     SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4515 
4516     SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4517 
4518     SmallVector<SDValue, 8> NewOps;
4519     for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4520       SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4521       SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4522 
4523       SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4524                                 CastVec, TmpIdx);
4525       NewOps.push_back(Elt);
4526     }
4527 
4528     SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps);
4529 
4530     Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4531     break;
4532   }
4533   case ISD::INSERT_VECTOR_ELT: {
4534     MVT EltVT = OVT.getVectorElementType();
4535     MVT NewEltVT = NVT.getVectorElementType();
4536 
4537     // Handle bitcasts to a different vector type with the same total bit size
4538     //
4539     // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4540     //  =>
4541     //  v4i32:castx = bitcast x:v2i64
4542     //  v2i32:casty = bitcast y:i64
4543     //
4544     // v2i64 = bitcast
4545     //   (v4i32 insert_vector_elt
4546     //       (v4i32 insert_vector_elt v4i32:castx,
4547     //                                (extract_vector_elt casty, 0), 2 * z),
4548     //        (extract_vector_elt casty, 1), (2 * z + 1))
4549 
4550     assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4551            "Invalid promote type for insert_vector_elt");
4552     assert(NewEltVT.bitsLT(EltVT) && "not handled");
4553 
4554     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4555     unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4556 
4557     SDValue Val = Node->getOperand(1);
4558     SDValue Idx = Node->getOperand(2);
4559     EVT IdxVT = Idx.getValueType();
4560     SDLoc SL(Node);
4561 
4562     SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4563     SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4564 
4565     SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4566     SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4567 
4568     SDValue NewVec = CastVec;
4569     for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4570       SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4571       SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4572 
4573       SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4574                                 CastVal, IdxOffset);
4575 
4576       NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4577                            NewVec, Elt, InEltIdx);
4578     }
4579 
4580     Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4581     break;
4582   }
4583   case ISD::SCALAR_TO_VECTOR: {
4584     MVT EltVT = OVT.getVectorElementType();
4585     MVT NewEltVT = NVT.getVectorElementType();
4586 
4587     // Handle bitcasts to different vector type with the smae total bit size.
4588     //
4589     // e.g. v2i64 = scalar_to_vector x:i64
4590     //   =>
4591     //  concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4592     //
4593 
4594     MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4595     SDValue Val = Node->getOperand(0);
4596     SDLoc SL(Node);
4597 
4598     SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4599     SDValue Undef = DAG.getUNDEF(MidVT);
4600 
4601     SmallVector<SDValue, 8> NewElts;
4602     NewElts.push_back(CastVal);
4603     for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4604       NewElts.push_back(Undef);
4605 
4606     SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4607     SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4608     Results.push_back(CvtVec);
4609     break;
4610   }
4611   }
4612 
4613   // Replace the original node with the legalized result.
4614   if (!Results.empty())
4615     ReplaceNode(Node, Results.data());
4616 }
4617 
4618 /// This is the entry point for the file.
Legalize()4619 void SelectionDAG::Legalize() {
4620   AssignTopologicalOrder();
4621 
4622   SmallPtrSet<SDNode *, 16> LegalizedNodes;
4623   SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4624 
4625   // Visit all the nodes. We start in topological order, so that we see
4626   // nodes with their original operands intact. Legalization can produce
4627   // new nodes which may themselves need to be legalized. Iterate until all
4628   // nodes have been legalized.
4629   for (;;) {
4630     bool AnyLegalized = false;
4631     for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4632       --NI;
4633 
4634       SDNode *N = &*NI;
4635       if (N->use_empty() && N != getRoot().getNode()) {
4636         ++NI;
4637         DeleteNode(N);
4638         continue;
4639       }
4640 
4641       if (LegalizedNodes.insert(N).second) {
4642         AnyLegalized = true;
4643         Legalizer.LegalizeOp(N);
4644 
4645         if (N->use_empty() && N != getRoot().getNode()) {
4646           ++NI;
4647           DeleteNode(N);
4648         }
4649       }
4650     }
4651     if (!AnyLegalized)
4652       break;
4653 
4654   }
4655 
4656   // Remove dead nodes now.
4657   RemoveDeadNodes();
4658 }
4659 
LegalizeOp(SDNode * N,SmallSetVector<SDNode *,16> & UpdatedNodes)4660 bool SelectionDAG::LegalizeOp(SDNode *N,
4661                               SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4662   SmallPtrSet<SDNode *, 16> LegalizedNodes;
4663   SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4664 
4665   // Directly insert the node in question, and legalize it. This will recurse
4666   // as needed through operands.
4667   LegalizedNodes.insert(N);
4668   Legalizer.LegalizeOp(N);
4669 
4670   return LegalizedNodes.count(N);
4671 }
4672