1 // Copyright 2006-2013 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 // This module contains the architecture-specific code. This make the rest of
6 // the code less dependent on differences between different processor
7 // architecture.
8 // The classes have the same definition for all architectures. The
9 // implementation for a particular architecture is put in cpu_<arch>.cc.
10 // The build system then uses the implementation for the target architecture.
11 //
12 
13 #ifndef V8_BASE_CPU_H_
14 #define V8_BASE_CPU_H_
15 
16 #include "src/base/macros.h"
17 
18 namespace v8 {
19 namespace base {
20 
21 // ----------------------------------------------------------------------------
22 // CPU
23 //
24 // Query information about the processor.
25 //
26 // This class also has static methods for the architecture specific functions.
27 // Add methods here to cope with differences between the supported
28 // architectures. For each architecture the file cpu_<arch>.cc contains the
29 // implementation of these static functions.
30 
31 class CPU final {
32  public:
33   CPU();
34 
35   // x86 CPUID information
vendor()36   const char* vendor() const { return vendor_; }
stepping()37   int stepping() const { return stepping_; }
model()38   int model() const { return model_; }
ext_model()39   int ext_model() const { return ext_model_; }
family()40   int family() const { return family_; }
ext_family()41   int ext_family() const { return ext_family_; }
type()42   int type() const { return type_; }
43 
44   // arm implementer/part information
implementer()45   int implementer() const { return implementer_; }
46   static const int ARM = 0x41;
47   static const int NVIDIA = 0x4e;
48   static const int QUALCOMM = 0x51;
architecture()49   int architecture() const { return architecture_; }
variant()50   int variant() const { return variant_; }
51   static const int NVIDIA_DENVER = 0x0;
part()52   int part() const { return part_; }
53 
54   // ARM-specific part codes
55   static const int ARM_CORTEX_A5 = 0xc05;
56   static const int ARM_CORTEX_A7 = 0xc07;
57   static const int ARM_CORTEX_A8 = 0xc08;
58   static const int ARM_CORTEX_A9 = 0xc09;
59   static const int ARM_CORTEX_A12 = 0xc0c;
60   static const int ARM_CORTEX_A15 = 0xc0f;
61 
62   // Denver-specific part code
63   static const int NVIDIA_DENVER_V10 = 0x002;
64 
65   // PPC-specific part codes
66   enum {
67     PPC_POWER5,
68     PPC_POWER6,
69     PPC_POWER7,
70     PPC_POWER8,
71     PPC_G4,
72     PPC_G5,
73     PPC_PA6T
74   };
75 
76   // General features
has_fpu()77   bool has_fpu() const { return has_fpu_; }
78 
79   // x86 features
has_cmov()80   bool has_cmov() const { return has_cmov_; }
has_sahf()81   bool has_sahf() const { return has_sahf_; }
has_mmx()82   bool has_mmx() const { return has_mmx_; }
has_sse()83   bool has_sse() const { return has_sse_; }
has_sse2()84   bool has_sse2() const { return has_sse2_; }
has_sse3()85   bool has_sse3() const { return has_sse3_; }
has_ssse3()86   bool has_ssse3() const { return has_ssse3_; }
has_sse41()87   bool has_sse41() const { return has_sse41_; }
has_sse42()88   bool has_sse42() const { return has_sse42_; }
has_osxsave()89   bool has_osxsave() const { return has_osxsave_; }
has_avx()90   bool has_avx() const { return has_avx_; }
has_fma3()91   bool has_fma3() const { return has_fma3_; }
has_bmi1()92   bool has_bmi1() const { return has_bmi1_; }
has_bmi2()93   bool has_bmi2() const { return has_bmi2_; }
has_lzcnt()94   bool has_lzcnt() const { return has_lzcnt_; }
has_popcnt()95   bool has_popcnt() const { return has_popcnt_; }
is_atom()96   bool is_atom() const { return is_atom_; }
97 
98   // arm features
has_idiva()99   bool has_idiva() const { return has_idiva_; }
has_neon()100   bool has_neon() const { return has_neon_; }
has_thumb2()101   bool has_thumb2() const { return has_thumb2_; }
has_vfp()102   bool has_vfp() const { return has_vfp_; }
has_vfp3()103   bool has_vfp3() const { return has_vfp3_; }
has_vfp3_d32()104   bool has_vfp3_d32() const { return has_vfp3_d32_; }
105 
106   // mips features
is_fp64_mode()107   bool is_fp64_mode() const { return is_fp64_mode_; }
108 
109  private:
110   char vendor_[13];
111   int stepping_;
112   int model_;
113   int ext_model_;
114   int family_;
115   int ext_family_;
116   int type_;
117   int implementer_;
118   int architecture_;
119   int variant_;
120   int part_;
121   bool has_fpu_;
122   bool has_cmov_;
123   bool has_sahf_;
124   bool has_mmx_;
125   bool has_sse_;
126   bool has_sse2_;
127   bool has_sse3_;
128   bool has_ssse3_;
129   bool has_sse41_;
130   bool has_sse42_;
131   bool is_atom_;
132   bool has_osxsave_;
133   bool has_avx_;
134   bool has_fma3_;
135   bool has_bmi1_;
136   bool has_bmi2_;
137   bool has_lzcnt_;
138   bool has_popcnt_;
139   bool has_idiva_;
140   bool has_neon_;
141   bool has_thumb2_;
142   bool has_vfp_;
143   bool has_vfp3_;
144   bool has_vfp3_d32_;
145   bool is_fp64_mode_;
146 };
147 
148 }  // namespace base
149 }  // namespace v8
150 
151 #endif  // V8_BASE_CPU_H_
152