Home
last modified time | relevance | path

Searched defs:NumVecs (Results 1 – 5 of 5) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1018 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, in SelectTable()
1134 SDNode *AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, in SelectLoad()
1155 SDNode *AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs, in SelectPostLoad()
1187 SDNode *AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs, in SelectStore()
1203 SDNode *AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs, in SelectPostStore()
1259 SDNode *AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs, in SelectLoadLane()
1299 SDNode *AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs, in SelectPostLoadLane()
1355 SDNode *AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs, in SelectStoreLane()
1385 SDNode *AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs, in SelectPostStoreLane()
DAArch64ISelLowering.cpp9078 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp1684 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign()
1804 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD()
1937 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVST()
2085 bool isUpdating, unsigned NumVecs, in SelectVLDSTLane()
2204 unsigned NumVecs, in SelectVLDDup()
2286 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, in SelectVTBL()
DARMISelLowering.cpp9514 unsigned NumVecs = 0; in CombineBaseUpdate() local
9714 unsigned NumVecs = 0; in CombineVLDDUP() local
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp27079 unsigned NumVecs = VT.getSizeInBits() / 128; in PerformSExtCombine() local