1 /*
2 * Copyright (C) 2009 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #ifndef RADEON_OPCODES_H
29 #define RADEON_OPCODES_H
30
31 #include <assert.h>
32
33 /**
34 * Opcodes understood by the Radeon compiler.
35 */
36 typedef enum {
37 RC_OPCODE_NOP = 0,
38 RC_OPCODE_ILLEGAL_OPCODE,
39
40 /** vec4 instruction: dst.c = abs(src0.c); */
41 RC_OPCODE_ABS,
42
43 /** vec4 instruction: dst.c = src0.c + src1.c; */
44 RC_OPCODE_ADD,
45
46 /** special instruction: load address register
47 * dst.x = floor(src.x), where dst must be an address register */
48 RC_OPCODE_ARL,
49
50 /** vec4 instruction: dst.c = ceil(src0.c) */
51 RC_OPCODE_CEIL,
52
53 /** vec4 instruction: dst.c = clamp(src0.c, src1.c, src2.c) */
54 RC_OPCODE_CLAMP,
55
56 /** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
57 RC_OPCODE_CMP,
58
59 /** vec4 instruction: dst.c = src2.c > 0.5 ? src0.c : src1.c */
60 RC_OPCODE_CND,
61
62 /** scalar instruction: dst = cos(src0.x) */
63 RC_OPCODE_COS,
64
65 /** special instruction: take vec4 partial derivative in X direction
66 * dst.c = d src0.c / dx */
67 RC_OPCODE_DDX,
68
69 /** special instruction: take vec4 partial derivative in Y direction
70 * dst.c = d src0.c / dy */
71 RC_OPCODE_DDY,
72
73 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y */
74 RC_OPCODE_DP2,
75
76 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z */
77 RC_OPCODE_DP3,
78
79 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src0.w*src1.w */
80 RC_OPCODE_DP4,
81
82 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src1.w */
83 RC_OPCODE_DPH,
84
85 /** special instruction, see ARB_fragment_program */
86 RC_OPCODE_DST,
87
88 /** scalar instruction: dst = 2**src0.x */
89 RC_OPCODE_EX2,
90
91 /** special instruction, see ARB_vertex_program */
92 RC_OPCODE_EXP,
93
94 /** vec4 instruction: dst.c = floor(src0.c) */
95 RC_OPCODE_FLR,
96
97 /** vec4 instruction: dst.c = src0.c - floor(src0.c) */
98 RC_OPCODE_FRC,
99
100 /** special instruction: stop execution if any component of src0 is negative */
101 RC_OPCODE_KIL,
102
103 /** scalar instruction: dst = log_2(src0.x) */
104 RC_OPCODE_LG2,
105
106 /** special instruction, see ARB_vertex_program */
107 RC_OPCODE_LIT,
108
109 /** special instruction, see ARB_vertex_program */
110 RC_OPCODE_LOG,
111
112 /** vec4 instruction: dst.c = src0.c*src1.c + (1 - src0.c)*src2.c */
113 RC_OPCODE_LRP,
114
115 /** vec4 instruction: dst.c = src0.c*src1.c + src2.c */
116 RC_OPCODE_MAD,
117
118 /** vec4 instruction: dst.c = max(src0.c, src1.c) */
119 RC_OPCODE_MAX,
120
121 /** vec4 instruction: dst.c = min(src0.c, src1.c) */
122 RC_OPCODE_MIN,
123
124 /** vec4 instruction: dst.c = src0.c */
125 RC_OPCODE_MOV,
126
127 /** vec4 instruction: dst.c = src0.c*src1.c */
128 RC_OPCODE_MUL,
129
130 /** scalar instruction: dst = src0.x ** src1.x */
131 RC_OPCODE_POW,
132
133 /** scalar instruction: dst = 1 / src0.x */
134 RC_OPCODE_RCP,
135
136 /** vec4 instruction: dst.c = floor(src0.c + 0.5) */
137 RC_OPCODE_ROUND,
138
139 /** scalar instruction: dst = 1 / sqrt(src0.x) */
140 RC_OPCODE_RSQ,
141
142 /** special instruction, see ARB_fragment_program */
143 RC_OPCODE_SCS,
144
145 /** vec4 instruction: dst.c = (src0.c == src1.c) ? 1.0 : 0.0 */
146 RC_OPCODE_SEQ,
147
148 /** vec4 instruction: dst.c = 0.0 */
149 RC_OPCODE_SFL,
150
151 /** vec4 instruction: dst.c = (src0.c >= src1.c) ? 1.0 : 0.0 */
152 RC_OPCODE_SGE,
153
154 /** vec4 instruction: dst.c = (src0.c > src1.c) ? 1.0 : 0.0 */
155 RC_OPCODE_SGT,
156
157 /** scalar instruction: dst = sin(src0.x) */
158 RC_OPCODE_SIN,
159
160 /** vec4 instruction: dst.c = (src0.c <= src1.c) ? 1.0 : 0.0 */
161 RC_OPCODE_SLE,
162
163 /** vec4 instruction: dst.c = (src0.c < src1.c) ? 1.0 : 0.0 */
164 RC_OPCODE_SLT,
165
166 /** vec4 instruction: dst.c = (src0.c != src1.c) ? 1.0 : 0.0 */
167 RC_OPCODE_SNE,
168
169 /** vec4 instruction: dst.c = (src0.c < 0 ?) -1 : ((src0.c > 0) : 1 : 0) */
170 RC_OPCODE_SSG,
171
172 /** vec4 instruction: dst.c = src0.c - src1.c */
173 RC_OPCODE_SUB,
174
175 /** vec4 instruction: dst.c = src0.c */
176 RC_OPCODE_SWZ,
177
178 /** vec4 instruction: dst.c = (abs(src0.c) - fract(abs(src0.c))) * sgn(src0.c) */
179 RC_OPCODE_TRUNC,
180
181 /** special instruction, see ARB_fragment_program */
182 RC_OPCODE_XPD,
183
184 RC_OPCODE_TEX,
185 RC_OPCODE_TXB,
186 RC_OPCODE_TXD,
187 RC_OPCODE_TXL,
188 RC_OPCODE_TXP,
189
190 /** branch instruction:
191 * If src0.x != 0.0, continue with the next instruction;
192 * otherwise, jump to matching RC_OPCODE_ELSE or RC_OPCODE_ENDIF.
193 */
194 RC_OPCODE_IF,
195
196 /** branch instruction: jump to matching RC_OPCODE_ENDIF */
197 RC_OPCODE_ELSE,
198
199 /** branch instruction: has no effect */
200 RC_OPCODE_ENDIF,
201
202 RC_OPCODE_BGNLOOP,
203
204 RC_OPCODE_BRK,
205
206 RC_OPCODE_ENDLOOP,
207
208 RC_OPCODE_CONT,
209
210 /** special instruction, used in R300-R500 fragment program pair instructions
211 * indicates that the result of the alpha operation shall be replicated
212 * across all other channels */
213 RC_OPCODE_REPL_ALPHA,
214
215 /** special instruction, used in R300-R500 fragment programs
216 * to indicate the start of a block of texture instructions that
217 * can run simultaneously. */
218 RC_OPCODE_BEGIN_TEX,
219
220 /** Stop execution of the shader (GLSL discard) */
221 RC_OPCODE_KILP,
222
223 /* Vertex shader CF Instructions */
224 RC_ME_PRED_SEQ,
225 RC_ME_PRED_SGT,
226 RC_ME_PRED_SGE,
227 RC_ME_PRED_SNEQ,
228 RC_ME_PRED_SET_CLR,
229 RC_ME_PRED_SET_INV,
230 RC_ME_PRED_SET_POP,
231 RC_ME_PRED_SET_RESTORE,
232
233 RC_VE_PRED_SEQ_PUSH,
234 RC_VE_PRED_SGT_PUSH,
235 RC_VE_PRED_SGE_PUSH,
236 RC_VE_PRED_SNEQ_PUSH,
237
238 MAX_RC_OPCODE
239 } rc_opcode;
240
241
242 struct rc_opcode_info {
243 rc_opcode Opcode;
244 const char * Name;
245
246 /** true if the instruction reads from a texture.
247 *
248 * \note This is false for the KIL instruction, even though KIL is
249 * a texture instruction from a hardware point of view. */
250 unsigned int HasTexture:1;
251
252 unsigned int NumSrcRegs:2;
253 unsigned int HasDstReg:1;
254
255 /** true if this instruction affects control flow */
256 unsigned int IsFlowControl:1;
257
258 /** true if this is a vector instruction that operates on components in parallel
259 * without any cross-component interaction */
260 unsigned int IsComponentwise:1;
261
262 /** true if this instruction sources only its operands X components
263 * to compute one result which is smeared across all output channels */
264 unsigned int IsStandardScalar:1;
265 };
266
267 extern struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE];
268
rc_get_opcode_info(rc_opcode opcode)269 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
270 {
271 assert((unsigned int)opcode < MAX_RC_OPCODE);
272 assert(rc_opcodes[opcode].Opcode == opcode);
273
274 return &rc_opcodes[opcode];
275 }
276
277 struct rc_instruction;
278
279 void rc_compute_sources_for_writemask(
280 const struct rc_instruction *inst,
281 unsigned int writemask,
282 unsigned int *srcmasks);
283
284 #endif /* RADEON_OPCODES_H */
285