1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines wrappers for the Target class and related global
11 // functionality.  This makes it easier to access the data and provides a single
12 // place that needs to check it for validity.  All of these classes abort
13 // on error conditions.
14 //
15 //===----------------------------------------------------------------------===//
16 
17 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
18 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
19 
20 #include "CodeGenInstruction.h"
21 #include "CodeGenRegisters.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/TableGen/Record.h"
24 #include <algorithm>
25 
26 namespace llvm {
27 
28 struct CodeGenRegister;
29 class CodeGenSchedModels;
30 class CodeGenTarget;
31 
32 // SelectionDAG node properties.
33 //  SDNPMemOperand: indicates that a node touches memory and therefore must
34 //                  have an associated memory operand that describes the access.
35 enum SDNP {
36   SDNPCommutative,
37   SDNPAssociative,
38   SDNPHasChain,
39   SDNPOutGlue,
40   SDNPInGlue,
41   SDNPOptInGlue,
42   SDNPMayLoad,
43   SDNPMayStore,
44   SDNPSideEffect,
45   SDNPMemOperand,
46   SDNPVariadic,
47   SDNPWantRoot,
48   SDNPWantParent
49 };
50 
51 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
52 /// record corresponds to.
53 MVT::SimpleValueType getValueType(Record *Rec);
54 
55 std::string getName(MVT::SimpleValueType T);
56 std::string getEnumName(MVT::SimpleValueType T);
57 
58 /// getQualifiedName - Return the name of the specified record, with a
59 /// namespace qualifier if the record contains one.
60 std::string getQualifiedName(const Record *R);
61 
62 /// CodeGenTarget - This class corresponds to the Target class in the .td files.
63 ///
64 class CodeGenTarget {
65   RecordKeeper &Records;
66   Record *TargetRec;
67 
68   mutable DenseMap<const Record*,
69                    std::unique_ptr<CodeGenInstruction>> Instructions;
70   mutable std::unique_ptr<CodeGenRegBank> RegBank;
71   mutable std::vector<Record*> RegAltNameIndices;
72   mutable SmallVector<MVT::SimpleValueType, 8> LegalValueTypes;
73   void ReadRegAltNameIndices() const;
74   void ReadInstructions() const;
75   void ReadLegalValueTypes() const;
76 
77   mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
78 
79   mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
80 public:
81   CodeGenTarget(RecordKeeper &Records);
82   ~CodeGenTarget();
83 
getTargetRecord()84   Record *getTargetRecord() const { return TargetRec; }
85   const std::string &getName() const;
86 
87   /// getInstNamespace - Return the target-specific instruction namespace.
88   ///
89   std::string getInstNamespace() const;
90 
91   /// getInstructionSet - Return the InstructionSet object.
92   ///
93   Record *getInstructionSet() const;
94 
95   /// getAsmParser - Return the AssemblyParser definition for this target.
96   ///
97   Record *getAsmParser() const;
98 
99   /// getAsmParserVariant - Return the AssmblyParserVariant definition for
100   /// this target.
101   ///
102   Record *getAsmParserVariant(unsigned i) const;
103 
104   /// getAsmParserVariantCount - Return the AssmblyParserVariant definition
105   /// available for this target.
106   ///
107   unsigned getAsmParserVariantCount() const;
108 
109   /// getAsmWriter - Return the AssemblyWriter definition for this target.
110   ///
111   Record *getAsmWriter() const;
112 
113   /// getRegBank - Return the register bank description.
114   CodeGenRegBank &getRegBank() const;
115 
116   /// getRegisterByName - If there is a register with the specific AsmName,
117   /// return it.
118   const CodeGenRegister *getRegisterByName(StringRef Name) const;
119 
getRegAltNameIndices()120   const std::vector<Record*> &getRegAltNameIndices() const {
121     if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
122     return RegAltNameIndices;
123   }
124 
getRegisterClass(Record * R)125   const CodeGenRegisterClass &getRegisterClass(Record *R) const {
126     return *getRegBank().getRegClass(R);
127   }
128 
129   /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
130   /// specified physical register.
131   std::vector<MVT::SimpleValueType> getRegisterVTs(Record *R) const;
132 
getLegalValueTypes()133   ArrayRef<MVT::SimpleValueType> getLegalValueTypes() const {
134     if (LegalValueTypes.empty()) ReadLegalValueTypes();
135     return LegalValueTypes;
136   }
137 
138   /// isLegalValueType - Return true if the specified value type is natively
139   /// supported by the target (i.e. there are registers that directly hold it).
isLegalValueType(MVT::SimpleValueType VT)140   bool isLegalValueType(MVT::SimpleValueType VT) const {
141     ArrayRef<MVT::SimpleValueType> LegalVTs = getLegalValueTypes();
142     for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i)
143       if (LegalVTs[i] == VT) return true;
144     return false;
145   }
146 
147   CodeGenSchedModels &getSchedModels() const;
148 
149 private:
150   DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
getInstructions()151   getInstructions() const {
152     if (Instructions.empty()) ReadInstructions();
153     return Instructions;
154   }
155 public:
156 
getInstruction(const Record * InstRec)157   CodeGenInstruction &getInstruction(const Record *InstRec) const {
158     if (Instructions.empty()) ReadInstructions();
159     auto I = Instructions.find(InstRec);
160     assert(I != Instructions.end() && "Not an instruction");
161     return *I->second;
162   }
163 
164   /// getInstructionsByEnumValue - Return all of the instructions defined by the
165   /// target, ordered by their enum value.
166   const std::vector<const CodeGenInstruction*> &
getInstructionsByEnumValue()167   getInstructionsByEnumValue() const {
168     if (InstrsByEnum.empty()) ComputeInstrsByEnum();
169     return InstrsByEnum;
170   }
171 
172   typedef std::vector<const CodeGenInstruction*>::const_iterator inst_iterator;
inst_begin()173   inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
inst_end()174   inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
instructions()175   iterator_range<inst_iterator> instructions() const {
176     return make_range(inst_begin(), inst_end());
177   }
178 
179 
180   /// isLittleEndianEncoding - are instruction bit patterns defined as  [0..n]?
181   ///
182   bool isLittleEndianEncoding() const;
183 
184   /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
185   /// encodings, reverse the bit order of all instructions.
186   void reverseBitsForLittleEndianEncoding();
187 
188   /// guessInstructionProperties - should we just guess unset instruction
189   /// properties?
190   bool guessInstructionProperties() const;
191 
192 private:
193   void ComputeInstrsByEnum() const;
194 };
195 
196 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
197 /// tablegen class in TargetSelectionDAG.td
198 class ComplexPattern {
199   MVT::SimpleValueType Ty;
200   unsigned NumOperands;
201   std::string SelectFunc;
202   std::vector<Record*> RootNodes;
203   unsigned Properties; // Node properties
204 public:
ComplexPattern()205   ComplexPattern() : NumOperands(0) {}
206   ComplexPattern(Record *R);
207 
getValueType()208   MVT::SimpleValueType getValueType() const { return Ty; }
getNumOperands()209   unsigned getNumOperands() const { return NumOperands; }
getSelectFunc()210   const std::string &getSelectFunc() const { return SelectFunc; }
getRootNodes()211   const std::vector<Record*> &getRootNodes() const {
212     return RootNodes;
213   }
hasProperty(enum SDNP Prop)214   bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
215 };
216 
217 } // End llvm namespace
218 
219 #endif
220