1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic. 76 /// Materializes the offset from the local object pointer of another 77 /// function to a particular local object passed to llvm.localescape. The 78 /// operand is the MCSymbol label used to represent this offset, since 79 /// typically the offset is not known until after code generation of the 80 /// parent. 81 LOCAL_RECOVER, 82 83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 84 /// the DAG, which implements the named register global variables extension. 85 READ_REGISTER, 86 WRITE_REGISTER, 87 88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 89 /// first (possible) on-stack argument. This is needed for correct stack 90 /// adjustment during unwind. 91 FRAME_TO_ARGS_OFFSET, 92 93 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 94 /// 'eh_return' gcc dwarf builtin, which is used to return from 95 /// exception. The general meaning is: adjust stack by OFFSET and pass 96 /// execution to HANDLER. Many platform-related details also :) 97 EH_RETURN, 98 99 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 100 /// This corresponds to the eh.sjlj.setjmp intrinsic. 101 /// It takes an input chain and a pointer to the jump buffer as inputs 102 /// and returns an outchain. 103 EH_SJLJ_SETJMP, 104 105 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 106 /// This corresponds to the eh.sjlj.longjmp intrinsic. 107 /// It takes an input chain and a pointer to the jump buffer as inputs 108 /// and returns an outchain. 109 EH_SJLJ_LONGJMP, 110 111 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) 112 /// The target initializes the dispatch table here. 113 EH_SJLJ_SETUP_DISPATCH, 114 115 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 116 /// simplification, or lowering of the constant. They are used for constants 117 /// which are known to fit in the immediate fields of their users, or for 118 /// carrying magic numbers which are not values which need to be 119 /// materialized in registers. 120 TargetConstant, 121 TargetConstantFP, 122 123 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 124 /// anything else with this node, and this is valid in the target-specific 125 /// dag, turning into a GlobalAddress operand. 126 TargetGlobalAddress, 127 TargetGlobalTLSAddress, 128 TargetFrameIndex, 129 TargetJumpTable, 130 TargetConstantPool, 131 TargetExternalSymbol, 132 TargetBlockAddress, 133 134 MCSymbol, 135 136 /// TargetIndex - Like a constant pool entry, but with completely 137 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 138 /// 64-bit index. Targets can use this however they like. 139 TargetIndex, 140 141 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 142 /// This node represents a target intrinsic function with no side effects. 143 /// The first operand is the ID number of the intrinsic from the 144 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 145 /// node returns the result of the intrinsic. 146 INTRINSIC_WO_CHAIN, 147 148 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 149 /// This node represents a target intrinsic function with side effects that 150 /// returns a result. The first operand is a chain pointer. The second is 151 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 152 /// operands to the intrinsic follow. The node has two results, the result 153 /// of the intrinsic and an output chain. 154 INTRINSIC_W_CHAIN, 155 156 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 157 /// This node represents a target intrinsic function with side effects that 158 /// does not return a result. The first operand is a chain pointer. The 159 /// second is the ID number of the intrinsic from the llvm::Intrinsic 160 /// namespace. The operands to the intrinsic follow. 161 INTRINSIC_VOID, 162 163 /// CopyToReg - This node has three operands: a chain, a register number to 164 /// set to this value, and a value. 165 CopyToReg, 166 167 /// CopyFromReg - This node indicates that the input value is a virtual or 168 /// physical register that is defined outside of the scope of this 169 /// SelectionDAG. The register is available from the RegisterSDNode object. 170 CopyFromReg, 171 172 /// UNDEF - An undefined node. 173 UNDEF, 174 175 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 176 /// a Constant, which is required to be operand #1) half of the integer or 177 /// float value specified as operand #0. This is only for use before 178 /// legalization, for values that will be broken into multiple registers. 179 EXTRACT_ELEMENT, 180 181 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 182 /// Given two values of the same integer value type, this produces a value 183 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 184 /// legalization. 185 BUILD_PAIR, 186 187 /// MERGE_VALUES - This node takes multiple discrete operands and returns 188 /// them all as its individual results. This nodes has exactly the same 189 /// number of inputs and outputs. This node is useful for some pieces of the 190 /// code generator that want to think about a single node with multiple 191 /// results, not multiple nodes. 192 MERGE_VALUES, 193 194 /// Simple integer binary arithmetic operators. 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 196 197 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 198 /// a signed/unsigned value of type i[2*N], and return the full value as 199 /// two results, each of type iN. 200 SMUL_LOHI, UMUL_LOHI, 201 202 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 203 /// remainder result. 204 SDIVREM, UDIVREM, 205 206 /// CARRY_FALSE - This node is used when folding other nodes, 207 /// like ADDC/SUBC, which indicate the carry result is always false. 208 CARRY_FALSE, 209 210 /// Carry-setting nodes for multiple precision addition and subtraction. 211 /// These nodes take two operands of the same value type, and produce two 212 /// results. The first result is the normal add or sub result, the second 213 /// result is the carry flag result. 214 ADDC, SUBC, 215 216 /// Carry-using nodes for multiple precision addition and subtraction. These 217 /// nodes take three operands: The first two are the normal lhs and rhs to 218 /// the add or sub, and the third is the input carry flag. These nodes 219 /// produce two results; the normal result of the add or sub, and the output 220 /// carry flag. These nodes both read and write a carry flag to allow them 221 /// to them to be chained together for add and sub of arbitrarily large 222 /// values. 223 ADDE, SUBE, 224 225 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 226 /// These nodes take two operands: the normal LHS and RHS to the add. They 227 /// produce two results: the normal result of the add, and a boolean that 228 /// indicates if an overflow occurred (*not* a flag, because it may be store 229 /// to memory, etc.). If the type of the boolean is not i1 then the high 230 /// bits conform to getBooleanContents. 231 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 232 SADDO, UADDO, 233 234 /// Same for subtraction. 235 SSUBO, USUBO, 236 237 /// Same for multiplication. 238 SMULO, UMULO, 239 240 /// Simple binary floating point operators. 241 FADD, FSUB, FMUL, FDIV, FREM, 242 243 /// FMA - Perform a * b + c with no intermediate rounding step. 244 FMA, 245 246 /// FMAD - Perform a * b + c, while getting the same result as the 247 /// separately rounded operations. 248 FMAD, 249 250 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 251 /// DAG node does not require that X and Y have the same type, just that 252 /// they are both floating point. X and the result must have the same type. 253 /// FCOPYSIGN(f32, f64) is allowed. 254 FCOPYSIGN, 255 256 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 257 /// value as an integer 0/1 value. 258 FGETSIGN, 259 260 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 261 /// specified, possibly variable, elements. The number of elements is 262 /// required to be a power of two. The types of the operands must all be 263 /// the same and must match the vector element type, except that integer 264 /// types are allowed to be larger than the element type, in which case 265 /// the operands are implicitly truncated. 266 BUILD_VECTOR, 267 268 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 269 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 270 /// element type then VAL is truncated before replacement. 271 INSERT_VECTOR_ELT, 272 273 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 274 /// identified by the (potentially variable) element number IDX. If the 275 /// return type is an integer type larger than the element type of the 276 /// vector, the result is extended to the width of the return type. 277 EXTRACT_VECTOR_ELT, 278 279 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 280 /// vector type with the same length and element type, this produces a 281 /// concatenated vector result value, with length equal to the sum of the 282 /// lengths of the input vectors. 283 CONCAT_VECTORS, 284 285 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 286 /// with VECTOR2 inserted into VECTOR1 at the (potentially 287 /// variable) element number IDX, which must be a multiple of the 288 /// VECTOR2 vector length. The elements of VECTOR1 starting at 289 /// IDX are overwritten with VECTOR2. Elements IDX through 290 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 291 INSERT_SUBVECTOR, 292 293 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 294 /// vector value) starting with the element number IDX, which must be a 295 /// constant multiple of the result vector length. 296 EXTRACT_SUBVECTOR, 297 298 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 299 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 300 /// values that indicate which value (or undef) each result element will 301 /// get. These constant ints are accessible through the 302 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 303 /// 'vperm' instruction, except that the indices must be constants and are 304 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 305 VECTOR_SHUFFLE, 306 307 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 308 /// scalar value into element 0 of the resultant vector type. The top 309 /// elements 1 to N-1 of the N-element vector are undefined. The type 310 /// of the operand must match the vector element type, except when they 311 /// are integer types. In this case the operand is allowed to be wider 312 /// than the vector element type, and is implicitly truncated to it. 313 SCALAR_TO_VECTOR, 314 315 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 316 /// producing an unsigned/signed value of type i[2*N], then return the top 317 /// part. 318 MULHU, MULHS, 319 320 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned 321 /// integers. 322 SMIN, SMAX, UMIN, UMAX, 323 324 /// Bitwise operators - logical and, logical or, logical xor. 325 AND, OR, XOR, 326 327 /// Shift and rotation operations. After legalization, the type of the 328 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 329 /// the shift amount can be any type, but care must be taken to ensure it is 330 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 331 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 332 /// to represent the shift amount. 333 /// When the 1st operand is a vector, the shift amount must be in the same 334 /// type. (TLI.getShiftAmountTy() will return the same type when the input 335 /// type is a vector.) 336 SHL, SRA, SRL, ROTL, ROTR, 337 338 /// Byte Swap and Counting operators. 339 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, 340 341 /// Bit counting operators with an undefined result for zero inputs. 342 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 343 344 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 345 /// i1 then the high bits must conform to getBooleanContents. 346 SELECT, 347 348 /// Select with a vector condition (op #0) and two vector operands (ops #1 349 /// and #2), returning a vector result. All vectors have the same length. 350 /// Much like the scalar select and setcc, each bit in the condition selects 351 /// whether the corresponding result element is taken from op #1 or op #2. 352 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 353 /// change the condition type in order to match the VSELECT node using a 354 /// pattern. The condition follows the BooleanContent format of the target. 355 VSELECT, 356 357 /// Select with condition operator - This selects between a true value and 358 /// a false value (ops #2 and #3) based on the boolean result of comparing 359 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 360 /// condition code in op #4, a CondCodeSDNode. 361 SELECT_CC, 362 363 /// SetCC operator - This evaluates to a true value iff the condition is 364 /// true. If the result value type is not i1 then the high bits conform 365 /// to getBooleanContents. The operands to this are the left and right 366 /// operands to compare (ops #0, and #1) and the condition code to compare 367 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 368 /// then the result type must also be a vector type. 369 SETCC, 370 371 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but 372 /// op #2 is a *carry value*. This operator checks the result of 373 /// "LHS - RHS - Carry", and can be used to compare two wide integers: 374 /// (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers. 375 SETCCE, 376 377 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 378 /// integer shift operations. The operation ordering is: 379 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 380 SHL_PARTS, SRA_PARTS, SRL_PARTS, 381 382 /// Conversion operators. These are all single input single output 383 /// operations. For all of these, the result type must be strictly 384 /// wider or narrower (depending on the operation) than the source 385 /// type. 386 387 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 388 /// into new bits. 389 SIGN_EXTEND, 390 391 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 392 ZERO_EXTEND, 393 394 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 395 ANY_EXTEND, 396 397 /// TRUNCATE - Completely drop the high bits. 398 TRUNCATE, 399 400 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 401 /// depends on the first letter) to floating point. 402 SINT_TO_FP, 403 UINT_TO_FP, 404 405 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 406 /// sign extend a small value in a large integer register (e.g. sign 407 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 408 /// with the 7th bit). The size of the smaller type is indicated by the 1th 409 /// operand, a ValueType node. 410 SIGN_EXTEND_INREG, 411 412 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 413 /// in-register any-extension of the low lanes of an integer vector. The 414 /// result type must have fewer elements than the operand type, and those 415 /// elements must be larger integer types such that the total size of the 416 /// operand type and the result type match. Each of the low operand 417 /// elements is any-extended into the corresponding, wider result 418 /// elements with the high bits becoming undef. 419 ANY_EXTEND_VECTOR_INREG, 420 421 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 422 /// in-register sign-extension of the low lanes of an integer vector. The 423 /// result type must have fewer elements than the operand type, and those 424 /// elements must be larger integer types such that the total size of the 425 /// operand type and the result type match. Each of the low operand 426 /// elements is sign-extended into the corresponding, wider result 427 /// elements. 428 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 429 // scalars, but it also doesn't handle vectors well. Either it should be 430 // restricted to scalars or this node (and its handling) should be merged 431 // into it. 432 SIGN_EXTEND_VECTOR_INREG, 433 434 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 435 /// in-register zero-extension of the low lanes of an integer vector. The 436 /// result type must have fewer elements than the operand type, and those 437 /// elements must be larger integer types such that the total size of the 438 /// operand type and the result type match. Each of the low operand 439 /// elements is zero-extended into the corresponding, wider result 440 /// elements. 441 ZERO_EXTEND_VECTOR_INREG, 442 443 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 444 /// integer. 445 FP_TO_SINT, 446 FP_TO_UINT, 447 448 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 449 /// down to the precision of the destination VT. TRUNC is a flag, which is 450 /// always an integer that is zero or one. If TRUNC is 0, this is a 451 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 452 /// value of Y. 453 /// 454 /// The TRUNC = 1 case is used in cases where we know that the value will 455 /// not be modified by the node, because Y is not using any of the extra 456 /// precision of source type. This allows certain transformations like 457 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 458 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 459 FP_ROUND, 460 461 /// FLT_ROUNDS_ - Returns current rounding mode: 462 /// -1 Undefined 463 /// 0 Round to 0 464 /// 1 Round to nearest 465 /// 2 Round to +inf 466 /// 3 Round to -inf 467 FLT_ROUNDS_, 468 469 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 470 /// rounds it to a floating point value. It then promotes it and returns it 471 /// in a register of the same size. This operation effectively just 472 /// discards excess precision. The type to round down to is specified by 473 /// the VT operand, a VTSDNode. 474 FP_ROUND_INREG, 475 476 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 477 FP_EXTEND, 478 479 /// BITCAST - This operator converts between integer, vector and FP 480 /// values, as if the value was stored to memory with one type and loaded 481 /// from the same address with the other type (or equivalently for vector 482 /// format conversions, etc). The source and result are required to have 483 /// the same bit size (e.g. f32 <-> i32). This can also be used for 484 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 485 /// getNode(). 486 BITCAST, 487 488 /// ADDRSPACECAST - This operator converts between pointers of different 489 /// address spaces. 490 ADDRSPACECAST, 491 492 /// CONVERT_RNDSAT - This operator is used to support various conversions 493 /// between various types (float, signed, unsigned and vectors of those 494 /// types) with rounding and saturation. NOTE: Avoid using this operator as 495 /// most target don't support it and the operator might be removed in the 496 /// future. It takes the following arguments: 497 /// 0) value 498 /// 1) dest type (type to convert to) 499 /// 2) src type (type to convert from) 500 /// 3) rounding imm 501 /// 4) saturation imm 502 /// 5) ISD::CvtCode indicating the type of conversion to do 503 CONVERT_RNDSAT, 504 505 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 506 /// and truncation for half-precision (16 bit) floating numbers. These nodes 507 /// form a semi-softened interface for dealing with f16 (as an i16), which 508 /// is often a storage-only type but has native conversions. 509 FP16_TO_FP, FP_TO_FP16, 510 511 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 512 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 513 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 514 /// floating point operations. These are inspired by libm. 515 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 516 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 517 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 518 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two 519 /// values. 520 /// In the case where a single input is NaN, the non-NaN input is returned. 521 /// 522 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0. 523 FMINNUM, FMAXNUM, 524 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that 525 /// when a single input is NaN, NaN is returned. 526 FMINNAN, FMAXNAN, 527 528 /// FSINCOS - Compute both fsin and fcos as a single operation. 529 FSINCOS, 530 531 /// LOAD and STORE have token chains as their first operand, then the same 532 /// operands as an LLVM load/store instruction, then an offset node that 533 /// is added / subtracted from the base pointer to form the address (for 534 /// indexed memory ops). 535 LOAD, STORE, 536 537 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 538 /// to a specified boundary. This node always has two return values: a new 539 /// stack pointer value and a chain. The first operand is the token chain, 540 /// the second is the number of bytes to allocate, and the third is the 541 /// alignment boundary. The size is guaranteed to be a multiple of the 542 /// stack alignment, and the alignment is guaranteed to be bigger than the 543 /// stack alignment (if required) or 0 to get standard stack alignment. 544 DYNAMIC_STACKALLOC, 545 546 /// Control flow instructions. These all have token chains. 547 548 /// BR - Unconditional branch. The first operand is the chain 549 /// operand, the second is the MBB to branch to. 550 BR, 551 552 /// BRIND - Indirect branch. The first operand is the chain, the second 553 /// is the value to branch to, which must be of the same type as the 554 /// target's pointer type. 555 BRIND, 556 557 /// BR_JT - Jumptable branch. The first operand is the chain, the second 558 /// is the jumptable index, the last one is the jumptable entry index. 559 BR_JT, 560 561 /// BRCOND - Conditional branch. The first operand is the chain, the 562 /// second is the condition, the third is the block to branch to if the 563 /// condition is true. If the type of the condition is not i1, then the 564 /// high bits must conform to getBooleanContents. 565 BRCOND, 566 567 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 568 /// that the condition is represented as condition code, and two nodes to 569 /// compare, rather than as a combined SetCC node. The operands in order 570 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 571 BR_CC, 572 573 /// INLINEASM - Represents an inline asm block. This node always has two 574 /// return values: a chain and a flag result. The inputs are as follows: 575 /// Operand #0 : Input chain. 576 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 577 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 578 /// Operand #3 : HasSideEffect, IsAlignStack bits. 579 /// After this, it is followed by a list of operands with this format: 580 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 581 /// of operands that follow, etc. See InlineAsm.h. 582 /// ... however many operands ... 583 /// Operand #last: Optional, an incoming flag. 584 /// 585 /// The variable width operands are required to represent target addressing 586 /// modes as a single "operand", even though they may have multiple 587 /// SDOperands. 588 INLINEASM, 589 590 /// EH_LABEL - Represents a label in mid basic block used to track 591 /// locations needed for debug and exception handling tables. These nodes 592 /// take a chain as input and return a chain. 593 EH_LABEL, 594 595 /// CATCHPAD - Represents a catchpad instruction. 596 CATCHPAD, 597 598 /// CATCHRET - Represents a return from a catch block funclet. Used for 599 /// MSVC compatible exception handling. Takes a chain operand and a 600 /// destination basic block operand. 601 CATCHRET, 602 603 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for 604 /// MSVC compatible exception handling. Takes only a chain operand. 605 CLEANUPRET, 606 607 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 608 /// value, the same type as the pointer type for the system, and an output 609 /// chain. 610 STACKSAVE, 611 612 /// STACKRESTORE has two operands, an input chain and a pointer to restore 613 /// to it returns an output chain. 614 STACKRESTORE, 615 616 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 617 /// of a call sequence, and carry arbitrary information that target might 618 /// want to know. The first operand is a chain, the rest are specified by 619 /// the target and not touched by the DAG optimizers. 620 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 621 CALLSEQ_START, // Beginning of a call sequence 622 CALLSEQ_END, // End of a call sequence 623 624 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 625 /// and the alignment. It returns a pair of values: the vaarg value and a 626 /// new chain. 627 VAARG, 628 629 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 630 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 631 /// source. 632 VACOPY, 633 634 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 635 /// pointer, and a SRCVALUE. 636 VAEND, VASTART, 637 638 /// SRCVALUE - This is a node type that holds a Value* that is used to 639 /// make reference to a value in the LLVM IR. 640 SRCVALUE, 641 642 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 643 /// reference metadata in the IR. 644 MDNODE_SDNODE, 645 646 /// PCMARKER - This corresponds to the pcmarker intrinsic. 647 PCMARKER, 648 649 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 650 /// It produces a chain and one i64 value. The only operand is a chain. 651 /// If i64 is not legal, the result will be expanded into smaller values. 652 /// Still, it returns an i64, so targets should set legality for i64. 653 /// The result is the content of the architecture-specific cycle 654 /// counter-like register (or other high accuracy low latency clock source). 655 READCYCLECOUNTER, 656 657 /// HANDLENODE node - Used as a handle for various purposes. 658 HANDLENODE, 659 660 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 661 /// takes as input a token chain, the pointer to the trampoline, the pointer 662 /// to the nested function, the pointer to pass for the 'nest' parameter, a 663 /// SRCVALUE for the trampoline and another for the nested function 664 /// (allowing targets to access the original Function*). 665 /// It produces a token chain as output. 666 INIT_TRAMPOLINE, 667 668 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 669 /// It takes a pointer to the trampoline and produces a (possibly) new 670 /// pointer to the same trampoline with platform-specific adjustments 671 /// applied. The pointer it returns points to an executable block of code. 672 ADJUST_TRAMPOLINE, 673 674 /// TRAP - Trapping instruction 675 TRAP, 676 677 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 678 DEBUGTRAP, 679 680 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 681 /// is the chain. The other operands are the address to prefetch, 682 /// read / write specifier, locality specifier and instruction / data cache 683 /// specifier. 684 PREFETCH, 685 686 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 687 /// This corresponds to the fence instruction. It takes an input chain, and 688 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 689 ATOMIC_FENCE, 690 691 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 692 /// This corresponds to "load atomic" instruction. 693 ATOMIC_LOAD, 694 695 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 696 /// This corresponds to "store atomic" instruction. 697 ATOMIC_STORE, 698 699 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 700 /// For double-word atomic operations: 701 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 702 /// swapLo, swapHi) 703 /// This corresponds to the cmpxchg instruction. 704 ATOMIC_CMP_SWAP, 705 706 /// Val, Success, OUTCHAIN 707 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 708 /// N.b. this is still a strong cmpxchg operation, so 709 /// Success == "Val == cmp". 710 ATOMIC_CMP_SWAP_WITH_SUCCESS, 711 712 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 713 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 714 /// For double-word atomic operations: 715 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 716 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 717 /// These correspond to the atomicrmw instruction. 718 ATOMIC_SWAP, 719 ATOMIC_LOAD_ADD, 720 ATOMIC_LOAD_SUB, 721 ATOMIC_LOAD_AND, 722 ATOMIC_LOAD_OR, 723 ATOMIC_LOAD_XOR, 724 ATOMIC_LOAD_NAND, 725 ATOMIC_LOAD_MIN, 726 ATOMIC_LOAD_MAX, 727 ATOMIC_LOAD_UMIN, 728 ATOMIC_LOAD_UMAX, 729 730 // Masked load and store - consecutive vector load and store operations 731 // with additional mask operand that prevents memory accesses to the 732 // masked-off lanes. 733 MLOAD, MSTORE, 734 735 // Masked gather and scatter - load and store operations for a vector of 736 // random addresses with additional mask operand that prevents memory 737 // accesses to the masked-off lanes. 738 MGATHER, MSCATTER, 739 740 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 741 /// is the chain and the second operand is the alloca pointer. 742 LIFETIME_START, LIFETIME_END, 743 744 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the 745 /// beginning and end of GC transition sequence, and carry arbitrary 746 /// information that target might need for lowering. The first operand is 747 /// a chain, the rest are specified by the target and not touched by the DAG 748 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be 749 /// nested. 750 GC_TRANSITION_START, 751 GC_TRANSITION_END, 752 753 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of 754 /// the most recent dynamic alloca. For most targets that would be 0, but 755 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time 756 /// known nonzero constant. The only operand here is the chain. 757 GET_DYNAMIC_AREA_OFFSET, 758 759 /// BUILTIN_OP_END - This must be the last enum value in this list. 760 /// The target-specific pre-isel opcode values start here. 761 BUILTIN_OP_END 762 }; 763 764 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 765 /// which do not reference a specific memory location should be less than 766 /// this value. Those that do must not be less than this value, and can 767 /// be used with SelectionDAG::getMemIntrinsicNode. 768 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300; 769 770 //===--------------------------------------------------------------------===// 771 /// MemIndexedMode enum - This enum defines the load / store indexed 772 /// addressing modes. 773 /// 774 /// UNINDEXED "Normal" load / store. The effective address is already 775 /// computed and is available in the base pointer. The offset 776 /// operand is always undefined. In addition to producing a 777 /// chain, an unindexed load produces one value (result of the 778 /// load); an unindexed store does not produce a value. 779 /// 780 /// PRE_INC Similar to the unindexed mode where the effective address is 781 /// PRE_DEC the value of the base pointer add / subtract the offset. 782 /// It considers the computation as being folded into the load / 783 /// store operation (i.e. the load / store does the address 784 /// computation as well as performing the memory transaction). 785 /// The base operand is always undefined. In addition to 786 /// producing a chain, pre-indexed load produces two values 787 /// (result of the load and the result of the address 788 /// computation); a pre-indexed store produces one value (result 789 /// of the address computation). 790 /// 791 /// POST_INC The effective address is the value of the base pointer. The 792 /// POST_DEC value of the offset operand is then added to / subtracted 793 /// from the base after memory transaction. In addition to 794 /// producing a chain, post-indexed load produces two values 795 /// (the result of the load and the result of the base +/- offset 796 /// computation); a post-indexed store produces one value (the 797 /// the result of the base +/- offset computation). 798 enum MemIndexedMode { 799 UNINDEXED = 0, 800 PRE_INC, 801 PRE_DEC, 802 POST_INC, 803 POST_DEC, 804 LAST_INDEXED_MODE 805 }; 806 807 //===--------------------------------------------------------------------===// 808 /// LoadExtType enum - This enum defines the three variants of LOADEXT 809 /// (load with extension). 810 /// 811 /// SEXTLOAD loads the integer operand and sign extends it to a larger 812 /// integer result type. 813 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 814 /// integer result type. 815 /// EXTLOAD is used for two things: floating point extending loads and 816 /// integer extending loads [the top bits are undefined]. 817 enum LoadExtType { 818 NON_EXTLOAD = 0, 819 EXTLOAD, 820 SEXTLOAD, 821 ZEXTLOAD, 822 LAST_LOADEXT_TYPE 823 }; 824 825 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 826 827 //===--------------------------------------------------------------------===// 828 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 829 /// below work out, when considering SETFALSE (something that never exists 830 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 831 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 832 /// to. If the "N" column is 1, the result of the comparison is undefined if 833 /// the input is a NAN. 834 /// 835 /// All of these (except for the 'always folded ops') should be handled for 836 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 837 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 838 /// 839 /// Note that these are laid out in a specific order to allow bit-twiddling 840 /// to transform conditions. 841 enum CondCode { 842 // Opcode N U L G E Intuitive operation 843 SETFALSE, // 0 0 0 0 Always false (always folded) 844 SETOEQ, // 0 0 0 1 True if ordered and equal 845 SETOGT, // 0 0 1 0 True if ordered and greater than 846 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 847 SETOLT, // 0 1 0 0 True if ordered and less than 848 SETOLE, // 0 1 0 1 True if ordered and less than or equal 849 SETONE, // 0 1 1 0 True if ordered and operands are unequal 850 SETO, // 0 1 1 1 True if ordered (no nans) 851 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 852 SETUEQ, // 1 0 0 1 True if unordered or equal 853 SETUGT, // 1 0 1 0 True if unordered or greater than 854 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 855 SETULT, // 1 1 0 0 True if unordered or less than 856 SETULE, // 1 1 0 1 True if unordered, less than, or equal 857 SETUNE, // 1 1 1 0 True if unordered or not equal 858 SETTRUE, // 1 1 1 1 Always true (always folded) 859 // Don't care operations: undefined if the input is a nan. 860 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 861 SETEQ, // 1 X 0 0 1 True if equal 862 SETGT, // 1 X 0 1 0 True if greater than 863 SETGE, // 1 X 0 1 1 True if greater than or equal 864 SETLT, // 1 X 1 0 0 True if less than 865 SETLE, // 1 X 1 0 1 True if less than or equal 866 SETNE, // 1 X 1 1 0 True if not equal 867 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 868 869 SETCC_INVALID // Marker value. 870 }; 871 872 /// isSignedIntSetCC - Return true if this is a setcc instruction that 873 /// performs a signed comparison when used with integer operands. isSignedIntSetCC(CondCode Code)874 inline bool isSignedIntSetCC(CondCode Code) { 875 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 876 } 877 878 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 879 /// performs an unsigned comparison when used with integer operands. isUnsignedIntSetCC(CondCode Code)880 inline bool isUnsignedIntSetCC(CondCode Code) { 881 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 882 } 883 884 /// isTrueWhenEqual - Return true if the specified condition returns true if 885 /// the two operands to the condition are equal. Note that if one of the two 886 /// operands is a NaN, this value is meaningless. isTrueWhenEqual(CondCode Cond)887 inline bool isTrueWhenEqual(CondCode Cond) { 888 return ((int)Cond & 1) != 0; 889 } 890 891 /// getUnorderedFlavor - This function returns 0 if the condition is always 892 /// false if an operand is a NaN, 1 if the condition is always true if the 893 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 894 /// NaN. getUnorderedFlavor(CondCode Cond)895 inline unsigned getUnorderedFlavor(CondCode Cond) { 896 return ((int)Cond >> 3) & 3; 897 } 898 899 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 900 /// 'op' is a valid SetCC operation. 901 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 902 903 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 904 /// when given the operation for (X op Y). 905 CondCode getSetCCSwappedOperands(CondCode Operation); 906 907 /// getSetCCOrOperation - Return the result of a logical OR between different 908 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 909 /// function returns SETCC_INVALID if it is not possible to represent the 910 /// resultant comparison. 911 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 912 913 /// getSetCCAndOperation - Return the result of a logical AND between 914 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 915 /// function returns SETCC_INVALID if it is not possible to represent the 916 /// resultant comparison. 917 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 918 919 //===--------------------------------------------------------------------===// 920 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 921 /// supports. 922 enum CvtCode { 923 CVT_FF, /// Float from Float 924 CVT_FS, /// Float from Signed 925 CVT_FU, /// Float from Unsigned 926 CVT_SF, /// Signed from Float 927 CVT_UF, /// Unsigned from Float 928 CVT_SS, /// Signed from Signed 929 CVT_SU, /// Signed from Unsigned 930 CVT_US, /// Unsigned from Signed 931 CVT_UU, /// Unsigned from Unsigned 932 CVT_INVALID /// Marker - Invalid opcode 933 }; 934 935 } // end llvm::ISD namespace 936 937 } // end llvm namespace 938 939 #endif 940