1 /* tc-m68k.c -- Assemble for the m68k family
2    Copyright (C) 1987-2014 Free Software Foundation, Inc.
3 
4    This file is part of GAS, the GNU Assembler.
5 
6    GAS is free software; you can redistribute it and/or modify
7    it under the terms of the GNU General Public License as published by
8    the Free Software Foundation; either version 3, or (at your option)
9    any later version.
10 
11    GAS is distributed in the hope that it will be useful,
12    but WITHOUT ANY WARRANTY; without even the implied warranty of
13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14    GNU General Public License for more details.
15 
16    You should have received a copy of the GNU General Public License
17    along with GAS; see the file COPYING.  If not, write to the Free
18    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19    02110-1301, USA.  */
20 
21 #include "as.h"
22 #include "safe-ctype.h"
23 #include "obstack.h"
24 #include "subsegs.h"
25 #include "dwarf2dbg.h"
26 #include "dw2gencfi.h"
27 
28 #include "opcode/m68k.h"
29 #include "m68k-parse.h"
30 
31 #if defined (OBJ_ELF)
32 #include "elf/m68k.h"
33 #endif
34 
35 #ifdef M68KCOFF
36 #include "obj-coff.h"
37 #endif
38 
39 #ifdef OBJ_ELF
40 static void m68k_elf_cons (int);
41 #endif
42 
43 /* This string holds the chars that always start a comment.  If the
44    pre-processor is disabled, these aren't very useful.  The macro
45    tc_comment_chars points to this.  We use this, rather than the
46    usual comment_chars, so that the --bitwise-or option will work.  */
47 #if defined (TE_SVR4) || defined (TE_DELTA)
48 const char *m68k_comment_chars = "|#";
49 #else
50 const char *m68k_comment_chars = "|";
51 #endif
52 
53 /* This array holds the chars that only start a comment at the beginning of
54    a line.  If the line seems to have the form '# 123 filename'
55    .line and .file directives will appear in the pre-processed output */
56 /* Note that input_file.c hand checks for '#' at the beginning of the
57    first line of the input file.  This is because the compiler outputs
58    #NO_APP at the beginning of its output.  */
59 /* Also note that comments like this one will always work.  */
60 const char line_comment_chars[] = "#*";
61 
62 const char line_separator_chars[] = ";";
63 
64 /* Chars that can be used to separate mant from exp in floating point nums.  */
65 const char EXP_CHARS[] = "eE";
66 
67 /* Chars that mean this number is a floating point constant, as
68    in "0f12.456" or "0d1.2345e12".  */
69 
70 const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
71 
72 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
73    changed in read.c .  Ideally it shouldn't have to know about it at all,
74    but nothing is ideal around here.  */
75 
76 /* Are we trying to generate PIC code?  If so, absolute references
77    ought to be made into linkage table references or pc-relative
78    references.  Not implemented.  For ELF there are other means
79    to denote pic relocations.  */
80 int flag_want_pic;
81 
82 static int flag_short_refs;	/* -l option.  */
83 static int flag_long_jumps;	/* -S option.  */
84 static int flag_keep_pcrel;	/* --pcrel option.  */
85 
86 #ifdef REGISTER_PREFIX_OPTIONAL
87 int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
88 #else
89 int flag_reg_prefix_optional;
90 #endif
91 
92 /* Whether --register-prefix-optional was used on the command line.  */
93 static int reg_prefix_optional_seen;
94 
95 /* The floating point coprocessor to use by default.  */
96 static enum m68k_register m68k_float_copnum = COP1;
97 
98 /* If this is non-zero, then references to number(%pc) will be taken
99    to refer to number, rather than to %pc + number.  */
100 static int m68k_abspcadd;
101 
102 /* If this is non-zero, then the quick forms of the move, add, and sub
103    instructions are used when possible.  */
104 static int m68k_quick = 1;
105 
106 /* If this is non-zero, then if the size is not specified for a base
107    or outer displacement, the assembler assumes that the size should
108    be 32 bits.  */
109 static int m68k_rel32 = 1;
110 
111 /* This is non-zero if m68k_rel32 was set from the command line.  */
112 static int m68k_rel32_from_cmdline;
113 
114 /* The default width to use for an index register when using a base
115    displacement.  */
116 static enum m68k_size m68k_index_width_default = SIZE_LONG;
117 
118 /* We want to warn if any text labels are misaligned.  In order to get
119    the right line number, we need to record the line number for each
120    label.  */
121 struct label_line
122 {
123   struct label_line *next;
124   symbolS *label;
125   char *file;
126   unsigned int line;
127   int text;
128 };
129 
130 /* The list of labels.  */
131 
132 static struct label_line *labels;
133 
134 /* The current label.  */
135 
136 static struct label_line *current_label;
137 
138 /* Pointer to list holding the opcodes sorted by name.  */
139 static struct m68k_opcode const ** m68k_sorted_opcodes;
140 
141 /* Its an arbitrary name:  This means I don't approve of it.
142    See flames below.  */
143 static struct obstack robyn;
144 
145 struct m68k_incant
146   {
147     const char *m_operands;
148     unsigned long m_opcode;
149     short m_opnum;
150     short m_codenum;
151     int m_arch;
152     struct m68k_incant *m_next;
153   };
154 
155 #define getone(x)	((((x)->m_opcode)>>16)&0xffff)
156 #define gettwo(x)	(((x)->m_opcode)&0xffff)
157 
158 static const enum m68k_register m68000_ctrl[] = { 0 };
159 static const enum m68k_register m68010_ctrl[] = {
160   SFC, DFC, USP, VBR,
161   0
162 };
163 static const enum m68k_register m68020_ctrl[] = {
164   SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
165   0
166 };
167 static const enum m68k_register m68040_ctrl[] = {
168   SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
169   USP, VBR, MSP, ISP, MMUSR, URP, SRP,
170   0
171 };
172 static const enum m68k_register m68060_ctrl[] = {
173   SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
174   USP, VBR, URP, SRP, PCR,
175   0
176 };
177 static const enum m68k_register mcf_ctrl[] = {
178   CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
179   RAMBAR0, RAMBAR1, RAMBAR, MBAR,
180   0
181 };
182 static const enum m68k_register mcf51_ctrl[] = {
183   VBR, CPUCR,
184   0
185 };
186 static const enum m68k_register mcf5206_ctrl[] = {
187   CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
188   0
189 };
190 static const enum m68k_register mcf5208_ctrl[] = {
191   CACR, ACR0, ACR1, VBR,  RAMBAR, RAMBAR1,
192   0
193 };
194 static const enum m68k_register mcf5210a_ctrl[] = {
195   VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
196   0
197 };
198 static const enum m68k_register mcf5213_ctrl[] = {
199   VBR, RAMBAR, RAMBAR1, FLASHBAR,
200   0
201 };
202 static const enum m68k_register mcf5216_ctrl[] = {
203   VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
204   0
205 };
206 static const enum m68k_register mcf5221x_ctrl[] = {
207   VBR, FLASHBAR, RAMBAR, RAMBAR1,
208   0
209 };
210 static const enum m68k_register mcf52223_ctrl[] = {
211   VBR, FLASHBAR, RAMBAR, RAMBAR1,
212   0
213 };
214 static const enum m68k_register mcf52235_ctrl[] = {
215   VBR, FLASHBAR, RAMBAR, RAMBAR1,
216   0
217 };
218 static const enum m68k_register mcf5225_ctrl[] = {
219   VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
220   0
221 };
222 static const enum m68k_register mcf52259_ctrl[] = {
223   VBR, FLASHBAR, RAMBAR, RAMBAR1,
224   0
225 };
226 static const enum m68k_register mcf52277_ctrl[] = {
227   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
228   0
229 };
230 static const enum m68k_register mcf5235_ctrl[] = {
231   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
232   0
233 };
234 static const enum m68k_register mcf5249_ctrl[] = {
235   VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
236   0
237 };
238 static const enum m68k_register mcf5250_ctrl[] = {
239   VBR,
240   0
241 };
242 static const enum m68k_register mcf5253_ctrl[] = {
243   VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
244   0
245 };
246 static const enum m68k_register mcf5271_ctrl[] = {
247   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
248   0
249 };
250 static const enum m68k_register mcf5272_ctrl[] = {
251   VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
252   0
253 };
254 static const enum m68k_register mcf5275_ctrl[] = {
255   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
256   0
257 };
258 static const enum m68k_register mcf5282_ctrl[] = {
259   VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
260   0
261 };
262 static const enum m68k_register mcf53017_ctrl[] = {
263   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
264   0
265 };
266 static const enum m68k_register mcf5307_ctrl[] = {
267   VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
268   0
269 };
270 static const enum m68k_register mcf5329_ctrl[] = {
271   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
272   0
273 };
274 static const enum m68k_register mcf5373_ctrl[] = {
275   VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
276   0
277 };
278 static const enum m68k_register mcfv4e_ctrl[] = {
279   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
280   VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
281   MBAR, SECMBAR,
282   MPCR /* Multiprocessor Control register */,
283   EDRAMBAR /* Embedded DRAM Base Address Register */,
284   /* Permutation control registers.  */
285   PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
286   PCR3U0, PCR3L0, PCR3U1, PCR3L1,
287   /* Legacy names */
288   TC /* ASID */, BUSCR /* MMUBAR */,
289   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
290   MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
291   ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
292   0
293 };
294 static const enum m68k_register mcf5407_ctrl[] = {
295   CACR, ASID, ACR0, ACR1, ACR2, ACR3,
296   VBR, PC, RAMBAR0, RAMBAR1, MBAR,
297   /* Legacy names */
298   TC /* ASID */,
299   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
300   MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
301   0
302 };
303 static const enum m68k_register mcf54418_ctrl[] = {
304   CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
305   VBR, PC, RAMBAR1,
306   /* Legacy names */
307   TC /* ASID */, BUSCR /* MMUBAR */,
308   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
309   RAMBAR /* RAMBAR1 */,
310   0
311 };
312 static const enum m68k_register mcf54455_ctrl[] = {
313   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
314   VBR, PC, RAMBAR1,
315   /* Legacy names */
316   TC /* ASID */, BUSCR /* MMUBAR */,
317   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
318   RAMBAR /* RAMBAR1 */,
319   0
320 };
321 static const enum m68k_register mcf5475_ctrl[] = {
322   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
323   VBR, PC, RAMBAR0, RAMBAR1, MBAR,
324   /* Legacy names */
325   TC /* ASID */, BUSCR /* MMUBAR */,
326   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
327   MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
328   0
329 };
330 static const enum m68k_register mcf5485_ctrl[] = {
331   CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
332   VBR, PC, RAMBAR0, RAMBAR1, MBAR,
333   /* Legacy names */
334   TC /* ASID */, BUSCR /* MMUBAR */,
335   ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
336   MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
337   0
338 };
339 static const enum m68k_register fido_ctrl[] = {
340   SFC, DFC, USP, VBR, CAC, MBO,
341   0
342 };
343 #define cpu32_ctrl m68010_ctrl
344 
345 static const enum m68k_register *control_regs;
346 
347 /* Internal form of a 68020 instruction.  */
348 struct m68k_it
349 {
350   const char *error;
351   const char *args;		/* List of opcode info.  */
352   int numargs;
353 
354   int numo;			/* Number of shorts in opcode.  */
355   short opcode[11];
356 
357   struct m68k_op operands[6];
358 
359   int nexp;			/* Number of exprs in use.  */
360   struct m68k_exp exprs[4];
361 
362   int nfrag;			/* Number of frags we have to produce.  */
363   struct
364     {
365       int fragoff;		/* Where in the current opcode the frag ends.  */
366       symbolS *fadd;
367       offsetT foff;
368       int fragty;
369     }
370   fragb[4];
371 
372   int nrel;			/* Num of reloc strucs in use.  */
373   struct
374     {
375       int n;
376       expressionS exp;
377       char wid;
378       char pcrel;
379       /* In a pc relative address the difference between the address
380 	 of the offset and the address that the offset is relative
381 	 to.  This depends on the addressing mode.  Basically this
382 	 is the value to put in the offset field to address the
383 	 first byte of the offset, without regarding the special
384 	 significance of some values (in the branch instruction, for
385 	 example).  */
386       int pcrel_fix;
387 #ifdef OBJ_ELF
388       /* Whether this expression needs special pic relocation, and if
389 	 so, which.  */
390       enum pic_relocation pic_reloc;
391 #endif
392     }
393   reloc[5];			/* Five is enough???  */
394 };
395 
396 #define cpu_of_arch(x)		((x) & (m68000up | mcfisa_a | fido_a))
397 #define float_of_arch(x)	((x) & mfloat)
398 #define mmu_of_arch(x)		((x) & mmmu)
399 #define arch_coldfire_p(x)	((x) & mcfisa_a)
400 #define arch_coldfire_fpu(x)	((x) & cfloat)
401 
402 /* Macros for determining if cpu supports a specific addressing mode.  */
403 #define HAVE_LONG_DISP(x)	\
404 	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
405 #define HAVE_LONG_CALL(x)	\
406 	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
407 #define HAVE_LONG_COND(x)	\
408 	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
409 #define HAVE_LONG_BRANCH(x)	\
410 	((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
411 #define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
412 
413 static struct m68k_it the_ins;	/* The instruction being assembled.  */
414 
415 #define op(ex)		((ex)->exp.X_op)
416 #define adds(ex)	((ex)->exp.X_add_symbol)
417 #define subs(ex)	((ex)->exp.X_op_symbol)
418 #define offs(ex)	((ex)->exp.X_add_number)
419 
420 /* Macros for adding things to the m68k_it struct.  */
421 #define addword(w)	(the_ins.opcode[the_ins.numo++] = (w))
422 
423 /* Like addword, but goes BEFORE general operands.  */
424 
425 static void
insop(int w,const struct m68k_incant * opcode)426 insop (int w, const struct m68k_incant *opcode)
427 {
428   int z;
429   for (z = the_ins.numo; z > opcode->m_codenum; --z)
430     the_ins.opcode[z] = the_ins.opcode[z - 1];
431   for (z = 0; z < the_ins.nrel; z++)
432     the_ins.reloc[z].n += 2;
433   for (z = 0; z < the_ins.nfrag; z++)
434     the_ins.fragb[z].fragoff++;
435   the_ins.opcode[opcode->m_codenum] = w;
436   the_ins.numo++;
437 }
438 
439 /* The numo+1 kludge is so we can hit the low order byte of the prev word.
440    Blecch.  */
441 static void
add_fix(int width,struct m68k_exp * exp,int pc_rel,int pc_fix)442 add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
443 {
444   the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
445 				   ? the_ins.numo * 2 - 1
446 				   : (width == 'b'
447 				      ? the_ins.numo * 2 + 1
448 				      : the_ins.numo * 2));
449   the_ins.reloc[the_ins.nrel].exp = exp->exp;
450   the_ins.reloc[the_ins.nrel].wid = width;
451   the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
452 #ifdef OBJ_ELF
453   the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
454 #endif
455   the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
456 }
457 
458 /* Cause an extra frag to be generated here, inserting up to 10 bytes
459    (that value is chosen in the frag_var call in md_assemble).  TYPE
460    is the subtype of the frag to be generated; its primary type is
461    rs_machine_dependent.
462 
463    The TYPE parameter is also used by md_convert_frag_1 and
464    md_estimate_size_before_relax.  The appropriate type of fixup will
465    be emitted by md_convert_frag_1.
466 
467    ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
468 static void
add_frag(symbolS * add,offsetT off,int type)469 add_frag (symbolS *add, offsetT off, int type)
470 {
471   the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
472   the_ins.fragb[the_ins.nfrag].fadd = add;
473   the_ins.fragb[the_ins.nfrag].foff = off;
474   the_ins.fragb[the_ins.nfrag++].fragty = type;
475 }
476 
477 #define isvar(ex) \
478   (op (ex) != O_constant && op (ex) != O_big)
479 
480 static char *crack_operand (char *str, struct m68k_op *opP);
481 static int get_num (struct m68k_exp *exp, int ok);
482 static int reverse_16_bits (int in);
483 static int reverse_8_bits (int in);
484 static void install_gen_operand (int mode, int val);
485 static void install_operand (int mode, int val);
486 static void s_bss (int);
487 static void s_data1 (int);
488 static void s_data2 (int);
489 static void s_even (int);
490 static void s_proc (int);
491 static void s_chip (int);
492 static void s_fopt (int);
493 static void s_opt (int);
494 static void s_reg (int);
495 static void s_restore (int);
496 static void s_save (int);
497 static void s_mri_if (int);
498 static void s_mri_else (int);
499 static void s_mri_endi (int);
500 static void s_mri_break (int);
501 static void s_mri_next (int);
502 static void s_mri_for (int);
503 static void s_mri_endf (int);
504 static void s_mri_repeat (int);
505 static void s_mri_until (int);
506 static void s_mri_while (int);
507 static void s_mri_endw (int);
508 static void s_m68k_cpu (int);
509 static void s_m68k_arch (int);
510 
511 struct m68k_cpu
512 {
513   unsigned long arch;	/* Architecture features.  */
514   const enum m68k_register *control_regs;	/* Control regs on chip */
515   const char *name;	/* Name */
516   int alias;       	/* Alias for a cannonical name.  If 1, then
517 			   succeeds canonical name, if -1 then
518 			   succeeds canonical name, if <-1 ||>1 this is a
519 			   deprecated name, and the next/previous name
520 			   should be used. */
521 };
522 
523 /* We hold flags for features explicitly enabled and explicitly
524    disabled.  */
525 static int current_architecture;
526 static int not_current_architecture;
527 static const struct m68k_cpu *selected_arch;
528 static const struct m68k_cpu *selected_cpu;
529 static int initialized;
530 
531 /* Architecture models.  */
532 static const struct m68k_cpu m68k_archs[] =
533 {
534   {m68000,					m68000_ctrl, "68000", 0},
535   {m68010,					m68010_ctrl, "68010", 0},
536   {m68020|m68881|m68851,			m68020_ctrl, "68020", 0},
537   {m68030|m68881|m68851,			m68020_ctrl, "68030", 0},
538   {m68040,					m68040_ctrl, "68040", 0},
539   {m68060,					m68060_ctrl, "68060", 0},
540   {cpu32|m68881,				cpu32_ctrl, "cpu32", 0},
541   {fido_a,					fido_ctrl, "fidoa", 0},
542   {mcfisa_a|mcfhwdiv,				NULL, "isaa", 0},
543   {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp,		NULL, "isaaplus", 0},
544   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp,		NULL, "isab", 0},
545   {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp,		NULL, "isac", 0},
546   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp,	mcf_ctrl, "cfv4", 0},
547   {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
548   {0,0,NULL, 0}
549 };
550 
551 /* For -mno-mac we want to turn off all types of mac.  */
552 static const unsigned no_mac = mcfmac | mcfemac;
553 
554 /* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
555    for either.  */
556 static const struct m68k_cpu m68k_extensions[] =
557 {
558   {m68851,					NULL, "68851", -1},
559   {m68881,					NULL, "68881", -1},
560   {m68881,					NULL, "68882", -1},
561 
562   {cfloat|m68881,				NULL, "float", 0},
563 
564   {mcfhwdiv,					NULL, "div", 1},
565   {mcfusp,					NULL, "usp", 1},
566   {mcfmac,					(void *)&no_mac, "mac", 1},
567   {mcfemac,					NULL, "emac", 1},
568 
569   {0,NULL,NULL, 0}
570 };
571 
572 /* Processor list */
573 static const struct m68k_cpu m68k_cpus[] =
574 {
575   {m68000,					m68000_ctrl, "68000", 0},
576   {m68000,					m68000_ctrl, "68ec000", 1},
577   {m68000,					m68000_ctrl, "68hc000", 1},
578   {m68000,					m68000_ctrl, "68hc001", 1},
579   {m68000,					m68000_ctrl, "68008", 1},
580   {m68000,					m68000_ctrl, "68302", 1},
581   {m68000,					m68000_ctrl, "68306", 1},
582   {m68000,					m68000_ctrl, "68307", 1},
583   {m68000,					m68000_ctrl, "68322", 1},
584   {m68000,					m68000_ctrl, "68356", 1},
585   {m68010,					m68010_ctrl, "68010", 0},
586   {m68020|m68881|m68851,			m68020_ctrl, "68020", 0},
587   {m68020|m68881|m68851,			m68020_ctrl, "68k", 1},
588   {m68020|m68881|m68851,			m68020_ctrl, "68ec020", 1},
589   {m68030|m68881|m68851,			m68020_ctrl, "68030", 0},
590   {m68030|m68881|m68851,			m68020_ctrl, "68ec030", 1},
591   {m68040,					m68040_ctrl, "68040", 0},
592   {m68040,					m68040_ctrl, "68ec040", 1},
593   {m68060,					m68060_ctrl, "68060", 0},
594   {m68060,					m68060_ctrl, "68ec060", 1},
595 
596   {cpu32|m68881,				cpu32_ctrl, "cpu32",  0},
597   {cpu32|m68881,				cpu32_ctrl, "68330", 1},
598   {cpu32|m68881,				cpu32_ctrl, "68331", 1},
599   {cpu32|m68881,				cpu32_ctrl, "68332", 1},
600   {cpu32|m68881,				cpu32_ctrl, "68333", 1},
601   {cpu32|m68881,				cpu32_ctrl, "68334", 1},
602   {cpu32|m68881,				cpu32_ctrl, "68336", 1},
603   {cpu32|m68881,				cpu32_ctrl, "68340", 1},
604   {cpu32|m68881,				cpu32_ctrl, "68341", 1},
605   {cpu32|m68881,				cpu32_ctrl, "68349", 1},
606   {cpu32|m68881,				cpu32_ctrl, "68360", 1},
607 
608   {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51", 0},
609   {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51ac", 1},
610   {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51ag", 1},
611   {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51cn", 1},
612   {mcfisa_a|mcfisa_c|mcfusp|mcfmac,  		mcf51_ctrl, "51em", 1},
613   {mcfisa_a|mcfisa_c|mcfusp|mcfmac,  		mcf51_ctrl, "51je", 1},
614   {mcfisa_a|mcfisa_c|mcfusp|mcfemac,            mcf51_ctrl, "51jf", 1},
615   {mcfisa_a|mcfisa_c|mcfusp|mcfemac,            mcf51_ctrl, "51jg", 1},
616   {mcfisa_a|mcfisa_c|mcfusp,  			mcf51_ctrl, "51jm", 1},
617   {mcfisa_a|mcfisa_c|mcfusp|mcfmac,  		mcf51_ctrl, "51mm", 1},
618   {mcfisa_a|mcfisa_c|mcfusp,                    mcf51_ctrl, "51qe", 1},
619   {mcfisa_a|mcfisa_c|mcfusp|mcfemac,            mcf51_ctrl, "51qm", 1},
620 
621   {mcfisa_a,					mcf_ctrl, "5200", 0},
622   {mcfisa_a,					mcf_ctrl, "5202", 1},
623   {mcfisa_a,					mcf_ctrl, "5204", 1},
624   {mcfisa_a,					mcf5206_ctrl, "5206", 1},
625 
626   {mcfisa_a|mcfhwdiv|mcfmac,			mcf5206_ctrl, "5206e", 0},
627 
628   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5207", -1},
629   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5208_ctrl, "5208", 0},
630 
631   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5210a_ctrl, "5210a", 0},
632   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5210a_ctrl, "5211a", 1},
633 
634   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5211", -1},
635   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5212", -1},
636   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,	mcf5213_ctrl, "5213", 0},
637 
638   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5214", -1},
639   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "5216", 0},
640   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5216_ctrl, "521x", 2},
641 
642   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5221x_ctrl, "5221x", 0},
643 
644   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52221", -1},
645   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf52223_ctrl, "52223", 0},
646 
647   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52230", -1},
648   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52233", -1},
649   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52234", -1},
650   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52235_ctrl, "52235", 0},
651 
652   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5224", -1},
653   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp,   mcf5225_ctrl, "5225", 0},
654 
655   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52277_ctrl, "52274", -1},
656   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,  mcf52277_ctrl, "52277", 0},
657 
658   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5232", -1},
659   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5233", -1},
660   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5234", -1},
661   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "5235", -1},
662   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5235_ctrl, "523x", 0},
663 
664   {mcfisa_a|mcfhwdiv|mcfemac,			mcf5249_ctrl, "5249", 0},
665   {mcfisa_a|mcfhwdiv|mcfemac,			mcf5250_ctrl, "5250", 0},
666   {mcfisa_a|mcfhwdiv|mcfemac, 			mcf5253_ctrl, "5253", 0},
667 
668   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52252", -1},
669   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52254", -1},
670   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52255", -1},
671   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52256", -1},
672   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52258", -1},
673   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf52259_ctrl, "52259", 0},
674 
675   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5270", -1},
676   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5271_ctrl, "5271", 0},
677 
678   {mcfisa_a|mcfhwdiv|mcfmac,			mcf5272_ctrl, "5272", 0},
679 
680   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5275_ctrl, "5274", -1},
681   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5275_ctrl, "5275", 0},
682 
683   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5280", -1},
684   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5281", -1},
685   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "5282", -1},
686   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5282_ctrl, "528x", 0},
687 
688   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53011", -1},
689   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53012", -1},
690   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53013", -1},
691   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53014", -1},
692   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53015", -1},
693   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53016", -1},
694   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf53017_ctrl, "53017", 0},
695 
696   {mcfisa_a|mcfhwdiv|mcfmac,			mcf5307_ctrl, "5307", 0},
697 
698   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5327", -1},
699   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5328", -1},
700   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "5329", -1},
701   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5329_ctrl, "532x", 0},
702 
703   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "5372", -1},
704   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "5373", -1},
705   {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp,	mcf5373_ctrl, "537x", 0},
706 
707   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac,		mcf5407_ctrl, "5407",0},
708 
709   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54410", -1},
710   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54415", -1},
711   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54416", -1},
712   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54417", -1},
713   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54418_ctrl, "54418", 0},
714 
715   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54450", -1},
716   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54451", -1},
717   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54452", -1},
718   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54453", -1},
719   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54454", -1},
720   {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp,   mcf54455_ctrl, "54455", 0},
721 
722   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
723   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
724   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
725   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
726   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
727   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
728   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
729 
730   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
731   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
732   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
733   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
734   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
735   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
736   {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
737 
738   {fido_a,				fido_ctrl, "fidoa", 0},
739   {fido_a,				fido_ctrl, "fido", 1},
740 
741   {0,NULL,NULL, 0}
742   };
743 
744 static const struct m68k_cpu *m68k_lookup_cpu
745 (const char *, const struct m68k_cpu *, int, int *);
746 static int m68k_set_arch (const char *, int, int);
747 static int m68k_set_cpu (const char *, int, int);
748 static int m68k_set_extension (const char *, int, int);
749 static void m68k_init_arch (void);
750 
751 /* This is the assembler relaxation table for m68k. m68k is a rich CISC
752    architecture and we have a lot of relaxation modes.  */
753 
754 /* Macros used in the relaxation code.  */
755 #define TAB(x,y)	(((x) << 2) + (y))
756 #define TABTYPE(x)      ((x) >> 2)
757 
758 /* Relaxation states.  */
759 #define BYTE		0
760 #define SHORT		1
761 #define LONG		2
762 #define SZ_UNDEF	3
763 
764 /* Here are all the relaxation modes we support.  First we can relax ordinary
765    branches.  On 68020 and higher and on CPU32 all branch instructions take
766    three forms, so on these CPUs all branches always remain as such.  When we
767    have to expand to the LONG form on a 68000, though, we substitute an
768    absolute jump instead.  This is a direct replacement for unconditional
769    branches and a branch over a jump for conditional branches.  However, if the
770    user requires PIC and disables this with --pcrel, we can only relax between
771    BYTE and SHORT forms, punting if that isn't enough.  This gives us four
772    different relaxation modes for branches:  */
773 
774 #define BRANCHBWL	0	/* Branch byte, word, or long.  */
775 #define BRABSJUNC	1	/* Absolute jump for LONG, unconditional.  */
776 #define BRABSJCOND	2	/* Absolute jump for LONG, conditional.  */
777 #define BRANCHBW	3	/* Branch byte or word.  */
778 
779 /* We also relax coprocessor branches and DBcc's.  All CPUs that support
780    coprocessor branches support them in word and long forms, so we have only
781    one relaxation mode for them.  DBcc's are word only on all CPUs.  We can
782    relax them to the LONG form with a branch-around sequence.  This sequence
783    can use a long branch (if available) or an absolute jump (if acceptable).
784    This gives us two relaxation modes.  If long branches are not available and
785    absolute jumps are not acceptable, we don't relax DBcc's.  */
786 
787 #define FBRANCH		4	/* Coprocessor branch.  */
788 #define DBCCLBR		5	/* DBcc relaxable with a long branch.  */
789 #define DBCCABSJ	6	/* DBcc relaxable with an absolute jump.  */
790 
791 /* That's all for instruction relaxation.  However, we also relax PC-relative
792    operands.  Specifically, we have three operand relaxation modes.  On the
793    68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
794    on CPU32 they may be 16-bit or 32-bit.  For the latter we relax between the
795    two.  Also PC+displacement+index operands in their simple form (with a non-
796    suppressed index without memory indirection) are supported on all CPUs, but
797    on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
798    and on CPU32 we relax it to SHORT and LONG forms as well using the extended
799    form of the PC+displacement+index operand.  Finally, some absolute operands
800    can be relaxed down to 16-bit PC-relative.  */
801 
802 #define PCREL1632	7	/* 16-bit or 32-bit PC-relative.  */
803 #define PCINDEX		8	/* PC + displacement + index. */
804 #define ABSTOPCREL	9	/* Absolute relax down to 16-bit PC-relative.  */
805 
806 /* This relaxation is required for branches where there is no long
807    branch and we are in pcrel mode.  We generate a bne/beq pair.  */
808 #define BRANCHBWPL	10      /* Branch byte, word or pair of longs
809 				   */
810 
811 /* Note that calls to frag_var need to specify the maximum expansion
812    needed; this is currently 12 bytes for bne/beq pair.  */
813 #define FRAG_VAR_SIZE 12
814 
815 /* The fields are:
816    How far Forward this mode will reach:
817    How far Backward this mode will reach:
818    How many bytes this mode will add to the size of the frag
819    Which mode to go to if the offset won't fit in this one
820 
821    Please check tc-m68k.h:md_prepare_relax_scan if changing this table.  */
822 relax_typeS md_relax_table[] =
823 {
824   {   127,   -128,  0, TAB (BRANCHBWL, SHORT) },
825   { 32767, -32768,  2, TAB (BRANCHBWL, LONG) },
826   {     0,	0,  4, 0 },
827   {     1,	1,  0, 0 },
828 
829   {   127,   -128,  0, TAB (BRABSJUNC, SHORT) },
830   { 32767, -32768,  2, TAB (BRABSJUNC, LONG) },
831   {	0,	0,  4, 0 },
832   {	1,	1,  0, 0 },
833 
834   {   127,   -128,  0, TAB (BRABSJCOND, SHORT) },
835   { 32767, -32768,  2, TAB (BRABSJCOND, LONG) },
836   {	0,	0,  6, 0 },
837   {	1,	1,  0, 0 },
838 
839   {   127,   -128,  0, TAB (BRANCHBW, SHORT) },
840   {	0,	0,  2, 0 },
841   {	1,	1,  0, 0 },
842   {	1,	1,  0, 0 },
843 
844   {	1, 	1,  0, 0 },		/* FBRANCH doesn't come BYTE.  */
845   { 32767, -32768,  2, TAB (FBRANCH, LONG) },
846   {	0,	0,  4, 0 },
847   {	1, 	1,  0, 0 },
848 
849   {	1,	1,  0, 0 },		/* DBCC doesn't come BYTE.  */
850   { 32767, -32768,  2, TAB (DBCCLBR, LONG) },
851   {	0,	0, 10, 0 },
852   {	1,	1,  0, 0 },
853 
854   {	1,	1,  0, 0 },		/* DBCC doesn't come BYTE.  */
855   { 32767, -32768,  2, TAB (DBCCABSJ, LONG) },
856   {	0,	0, 10, 0 },
857   {	1,	1,  0, 0 },
858 
859   {	1, 	1,  0, 0 },		/* PCREL1632 doesn't come BYTE.  */
860   { 32767, -32768,  2, TAB (PCREL1632, LONG) },
861   {	0,	0,  6, 0 },
862   {	1,	1,  0, 0 },
863 
864   {   125,   -130,  0, TAB (PCINDEX, SHORT) },
865   { 32765, -32770,  2, TAB (PCINDEX, LONG) },
866   {	0,	0,  4, 0 },
867   {	1,	1,  0, 0 },
868 
869   {	1,	1,  0, 0 },		/* ABSTOPCREL doesn't come BYTE.  */
870   { 32767, -32768,  2, TAB (ABSTOPCREL, LONG) },
871   {	0,	0,  4, 0 },
872   {	1,	1,  0, 0 },
873 
874   {   127,   -128,  0, TAB (BRANCHBWPL, SHORT) },
875   { 32767, -32768,  2, TAB (BRANCHBWPL, LONG) },
876   {     0,	0,  10, 0 },
877   {     1,	1,  0, 0 },
878 };
879 
880 /* These are the machine dependent pseudo-ops.  These are included so
881    the assembler can work on the output from the SUN C compiler, which
882    generates these.  */
883 
884 /* This table describes all the machine specific pseudo-ops the assembler
885    has to support.  The fields are:
886    pseudo-op name without dot
887    function to call to execute this pseudo-op
888    Integer arg to pass to the function.  */
889 const pseudo_typeS md_pseudo_table[] =
890 {
891   {"data1", s_data1, 0},
892   {"data2", s_data2, 0},
893   {"bss", s_bss, 0},
894   {"even", s_even, 0},
895   {"skip", s_space, 0},
896   {"proc", s_proc, 0},
897 #if defined (TE_SUN3) || defined (OBJ_ELF)
898   {"align", s_align_bytes, 0},
899 #endif
900 #ifdef OBJ_ELF
901   {"swbeg", s_ignore, 0},
902   {"long", m68k_elf_cons, 4},
903 #endif
904   {"extend", float_cons, 'x'},
905   {"ldouble", float_cons, 'x'},
906 
907   {"arch", s_m68k_arch, 0},
908   {"cpu", s_m68k_cpu, 0},
909 
910   /* The following pseudo-ops are supported for MRI compatibility.  */
911   {"chip", s_chip, 0},
912   {"comline", s_space, 1},
913   {"fopt", s_fopt, 0},
914   {"mask2", s_ignore, 0},
915   {"opt", s_opt, 0},
916   {"reg", s_reg, 0},
917   {"restore", s_restore, 0},
918   {"save", s_save, 0},
919 
920   {"if", s_mri_if, 0},
921   {"if.b", s_mri_if, 'b'},
922   {"if.w", s_mri_if, 'w'},
923   {"if.l", s_mri_if, 'l'},
924   {"else", s_mri_else, 0},
925   {"else.s", s_mri_else, 's'},
926   {"else.l", s_mri_else, 'l'},
927   {"endi", s_mri_endi, 0},
928   {"break", s_mri_break, 0},
929   {"break.s", s_mri_break, 's'},
930   {"break.l", s_mri_break, 'l'},
931   {"next", s_mri_next, 0},
932   {"next.s", s_mri_next, 's'},
933   {"next.l", s_mri_next, 'l'},
934   {"for", s_mri_for, 0},
935   {"for.b", s_mri_for, 'b'},
936   {"for.w", s_mri_for, 'w'},
937   {"for.l", s_mri_for, 'l'},
938   {"endf", s_mri_endf, 0},
939   {"repeat", s_mri_repeat, 0},
940   {"until", s_mri_until, 0},
941   {"until.b", s_mri_until, 'b'},
942   {"until.w", s_mri_until, 'w'},
943   {"until.l", s_mri_until, 'l'},
944   {"while", s_mri_while, 0},
945   {"while.b", s_mri_while, 'b'},
946   {"while.w", s_mri_while, 'w'},
947   {"while.l", s_mri_while, 'l'},
948   {"endw", s_mri_endw, 0},
949 
950   {0, 0, 0}
951 };
952 
953 /* The mote pseudo ops are put into the opcode table, since they
954    don't start with a . they look like opcodes to gas.  */
955 
956 const pseudo_typeS mote_pseudo_table[] =
957 {
958 
959   {"dcl", cons, 4},
960   {"dc", cons, 2},
961   {"dcw", cons, 2},
962   {"dcb", cons, 1},
963 
964   {"dsl", s_space, 4},
965   {"ds", s_space, 2},
966   {"dsw", s_space, 2},
967   {"dsb", s_space, 1},
968 
969   {"xdef", s_globl, 0},
970 #ifdef OBJ_ELF
971   {"align", s_align_bytes, 0},
972 #else
973   {"align", s_align_ptwo, 0},
974 #endif
975 #ifdef M68KCOFF
976   {"sect", obj_coff_section, 0},
977   {"section", obj_coff_section, 0},
978 #endif
979   {0, 0, 0}
980 };
981 
982 /* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
983    gives identical results to a 32-bit host.  */
984 #define TRUNC(X)	((valueT) (X) & 0xffffffff)
985 #define SEXT(X)		((TRUNC (X) ^ 0x80000000) - 0x80000000)
986 
987 #define issbyte(x)	((valueT) SEXT (x) + 0x80 < 0x100)
988 #define isubyte(x)	((valueT) TRUNC (x) < 0x100)
989 #define issword(x)	((valueT) SEXT (x) + 0x8000 < 0x10000)
990 #define isuword(x)	((valueT) TRUNC (x) < 0x10000)
991 
992 #define isbyte(x)	((valueT) SEXT (x) + 0xff < 0x1ff)
993 #define isword(x)	((valueT) SEXT (x) + 0xffff < 0x1ffff)
994 #define islong(x)	(1)
995 
996 static char notend_table[256];
997 static char alt_notend_table[256];
998 #define notend(s)						\
999   (! (notend_table[(unsigned char) *s]				\
1000       || (*s == ':'						\
1001 	  && alt_notend_table[(unsigned char) s[1]])))
1002 
1003 #ifdef OBJ_ELF
1004 
1005 /* Return zero if the reference to SYMBOL from within the same segment may
1006    be relaxed.  */
1007 
1008 /* On an ELF system, we can't relax an externally visible symbol,
1009    because it may be overridden by a shared library.  However, if
1010    TARGET_OS is "elf", then we presume that we are assembling for an
1011    embedded system, in which case we don't have to worry about shared
1012    libraries, and we can relax any external sym.  */
1013 
1014 #define relaxable_symbol(symbol) \
1015   (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
1016      || S_IS_WEAK (symbol)))
1017 
1018 /* Compute the relocation code for a fixup of SIZE bytes, using pc
1019    relative relocation if PCREL is non-zero.  PIC says whether a special
1020    pic relocation was requested.  */
1021 
1022 static bfd_reloc_code_real_type
get_reloc_code(int size,int pcrel,enum pic_relocation pic)1023 get_reloc_code (int size, int pcrel, enum pic_relocation pic)
1024 {
1025   switch (pic)
1026     {
1027     case pic_got_pcrel:
1028       switch (size)
1029 	{
1030 	case 1:
1031 	  return BFD_RELOC_8_GOT_PCREL;
1032 	case 2:
1033 	  return BFD_RELOC_16_GOT_PCREL;
1034 	case 4:
1035 	  return BFD_RELOC_32_GOT_PCREL;
1036 	}
1037       break;
1038 
1039     case pic_got_off:
1040       switch (size)
1041 	{
1042 	case 1:
1043 	  return BFD_RELOC_8_GOTOFF;
1044 	case 2:
1045 	  return BFD_RELOC_16_GOTOFF;
1046 	case 4:
1047 	  return BFD_RELOC_32_GOTOFF;
1048 	}
1049       break;
1050 
1051     case pic_plt_pcrel:
1052       switch (size)
1053 	{
1054 	case 1:
1055 	  return BFD_RELOC_8_PLT_PCREL;
1056 	case 2:
1057 	  return BFD_RELOC_16_PLT_PCREL;
1058 	case 4:
1059 	  return BFD_RELOC_32_PLT_PCREL;
1060 	}
1061       break;
1062 
1063     case pic_plt_off:
1064       switch (size)
1065 	{
1066 	case 1:
1067 	  return BFD_RELOC_8_PLTOFF;
1068 	case 2:
1069 	  return BFD_RELOC_16_PLTOFF;
1070 	case 4:
1071 	  return BFD_RELOC_32_PLTOFF;
1072 	}
1073       break;
1074 
1075     case pic_tls_gd:
1076       switch (size)
1077 	{
1078 	case 1:
1079 	  return BFD_RELOC_68K_TLS_GD8;
1080 	case 2:
1081 	  return BFD_RELOC_68K_TLS_GD16;
1082 	case 4:
1083 	  return BFD_RELOC_68K_TLS_GD32;
1084 	}
1085       break;
1086 
1087     case pic_tls_ldm:
1088       switch (size)
1089 	{
1090 	case 1:
1091 	  return BFD_RELOC_68K_TLS_LDM8;
1092 	case 2:
1093 	  return BFD_RELOC_68K_TLS_LDM16;
1094 	case 4:
1095 	  return BFD_RELOC_68K_TLS_LDM32;
1096 	}
1097       break;
1098 
1099     case pic_tls_ldo:
1100       switch (size)
1101 	{
1102 	case 1:
1103 	  return BFD_RELOC_68K_TLS_LDO8;
1104 	case 2:
1105 	  return BFD_RELOC_68K_TLS_LDO16;
1106 	case 4:
1107 	  return BFD_RELOC_68K_TLS_LDO32;
1108 	}
1109       break;
1110 
1111     case pic_tls_ie:
1112       switch (size)
1113 	{
1114 	case 1:
1115 	  return BFD_RELOC_68K_TLS_IE8;
1116 	case 2:
1117 	  return BFD_RELOC_68K_TLS_IE16;
1118 	case 4:
1119 	  return BFD_RELOC_68K_TLS_IE32;
1120 	}
1121       break;
1122 
1123     case pic_tls_le:
1124       switch (size)
1125 	{
1126 	case 1:
1127 	  return BFD_RELOC_68K_TLS_LE8;
1128 	case 2:
1129 	  return BFD_RELOC_68K_TLS_LE16;
1130 	case 4:
1131 	  return BFD_RELOC_68K_TLS_LE32;
1132 	}
1133       break;
1134 
1135     case pic_none:
1136       if (pcrel)
1137 	{
1138 	  switch (size)
1139 	    {
1140 	    case 1:
1141 	      return BFD_RELOC_8_PCREL;
1142 	    case 2:
1143 	      return BFD_RELOC_16_PCREL;
1144 	    case 4:
1145 	      return BFD_RELOC_32_PCREL;
1146 	    }
1147 	}
1148       else
1149 	{
1150 	  switch (size)
1151 	    {
1152 	    case 1:
1153 	      return BFD_RELOC_8;
1154 	    case 2:
1155 	      return BFD_RELOC_16;
1156 	    case 4:
1157 	      return BFD_RELOC_32;
1158 	    }
1159 	}
1160     }
1161 
1162   if (pcrel)
1163     {
1164       if (pic == pic_none)
1165 	as_bad (_("Can not do %d byte pc-relative relocation"), size);
1166       else
1167 	as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1168     }
1169   else
1170     {
1171       if (pic == pic_none)
1172 	as_bad (_("Can not do %d byte relocation"), size);
1173       else
1174 	as_bad (_("Can not do %d byte pic relocation"), size);
1175     }
1176 
1177   return BFD_RELOC_NONE;
1178 }
1179 
1180 /* Here we decide which fixups can be adjusted to make them relative
1181    to the beginning of the section instead of the symbol.  Basically
1182    we need to make sure that the dynamic relocations are done
1183    correctly, so in some cases we force the original symbol to be
1184    used.  */
1185 int
tc_m68k_fix_adjustable(fixS * fixP)1186 tc_m68k_fix_adjustable (fixS *fixP)
1187 {
1188   /* Adjust_reloc_syms doesn't know about the GOT.  */
1189   switch (fixP->fx_r_type)
1190     {
1191     case BFD_RELOC_8_GOT_PCREL:
1192     case BFD_RELOC_16_GOT_PCREL:
1193     case BFD_RELOC_32_GOT_PCREL:
1194     case BFD_RELOC_8_GOTOFF:
1195     case BFD_RELOC_16_GOTOFF:
1196     case BFD_RELOC_32_GOTOFF:
1197     case BFD_RELOC_8_PLT_PCREL:
1198     case BFD_RELOC_16_PLT_PCREL:
1199     case BFD_RELOC_32_PLT_PCREL:
1200     case BFD_RELOC_8_PLTOFF:
1201     case BFD_RELOC_16_PLTOFF:
1202     case BFD_RELOC_32_PLTOFF:
1203     case BFD_RELOC_68K_TLS_GD32:
1204     case BFD_RELOC_68K_TLS_GD16:
1205     case BFD_RELOC_68K_TLS_GD8:
1206     case BFD_RELOC_68K_TLS_LDM32:
1207     case BFD_RELOC_68K_TLS_LDM16:
1208     case BFD_RELOC_68K_TLS_LDM8:
1209     case BFD_RELOC_68K_TLS_LDO32:
1210     case BFD_RELOC_68K_TLS_LDO16:
1211     case BFD_RELOC_68K_TLS_LDO8:
1212     case BFD_RELOC_68K_TLS_IE32:
1213     case BFD_RELOC_68K_TLS_IE16:
1214     case BFD_RELOC_68K_TLS_IE8:
1215     case BFD_RELOC_68K_TLS_LE32:
1216     case BFD_RELOC_68K_TLS_LE16:
1217     case BFD_RELOC_68K_TLS_LE8:
1218       return 0;
1219 
1220     case BFD_RELOC_VTABLE_INHERIT:
1221     case BFD_RELOC_VTABLE_ENTRY:
1222       return 0;
1223 
1224     default:
1225       return 1;
1226     }
1227 }
1228 
1229 #else /* !OBJ_ELF */
1230 
1231 #define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1232 
1233 /* PR gas/3041 Weak symbols are not relaxable
1234    because they must be treated as extern.  */
1235 #define relaxable_symbol(symbol)   (!(S_IS_WEAK (symbol)))
1236 
1237 #endif /* OBJ_ELF */
1238 
1239 arelent *
tc_gen_reloc(asection * section ATTRIBUTE_UNUSED,fixS * fixp)1240 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
1241 {
1242   arelent *reloc;
1243   bfd_reloc_code_real_type code;
1244 
1245   /* If the tcbit is set, then this was a fixup of a negative value
1246      that was never resolved.  We do not have a reloc to handle this,
1247      so just return.  We assume that other code will have detected this
1248      situation and produced a helpful error message, so we just tell the
1249      user that the reloc cannot be produced.  */
1250   if (fixp->fx_tcbit)
1251     {
1252       if (fixp->fx_addsy)
1253 	as_bad_where (fixp->fx_file, fixp->fx_line,
1254 		      _("Unable to produce reloc against symbol '%s'"),
1255 		      S_GET_NAME (fixp->fx_addsy));
1256       return NULL;
1257     }
1258 
1259   if (fixp->fx_r_type != BFD_RELOC_NONE)
1260     {
1261       code = fixp->fx_r_type;
1262 
1263       /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1264          that fixup_segment converted a non-PC relative reloc into a
1265          PC relative reloc.  In such a case, we need to convert the
1266          reloc code.  */
1267       if (fixp->fx_pcrel)
1268 	{
1269 	  switch (code)
1270 	    {
1271 	    case BFD_RELOC_8:
1272 	      code = BFD_RELOC_8_PCREL;
1273 	      break;
1274 	    case BFD_RELOC_16:
1275 	      code = BFD_RELOC_16_PCREL;
1276 	      break;
1277 	    case BFD_RELOC_32:
1278 	      code = BFD_RELOC_32_PCREL;
1279 	      break;
1280 	    case BFD_RELOC_8_PCREL:
1281 	    case BFD_RELOC_16_PCREL:
1282 	    case BFD_RELOC_32_PCREL:
1283 	    case BFD_RELOC_8_GOT_PCREL:
1284 	    case BFD_RELOC_16_GOT_PCREL:
1285 	    case BFD_RELOC_32_GOT_PCREL:
1286 	    case BFD_RELOC_8_GOTOFF:
1287 	    case BFD_RELOC_16_GOTOFF:
1288 	    case BFD_RELOC_32_GOTOFF:
1289 	    case BFD_RELOC_8_PLT_PCREL:
1290 	    case BFD_RELOC_16_PLT_PCREL:
1291 	    case BFD_RELOC_32_PLT_PCREL:
1292 	    case BFD_RELOC_8_PLTOFF:
1293 	    case BFD_RELOC_16_PLTOFF:
1294 	    case BFD_RELOC_32_PLTOFF:
1295 	    case BFD_RELOC_68K_TLS_GD32:
1296 	    case BFD_RELOC_68K_TLS_GD16:
1297 	    case BFD_RELOC_68K_TLS_GD8:
1298 	    case BFD_RELOC_68K_TLS_LDM32:
1299 	    case BFD_RELOC_68K_TLS_LDM16:
1300 	    case BFD_RELOC_68K_TLS_LDM8:
1301 	    case BFD_RELOC_68K_TLS_LDO32:
1302 	    case BFD_RELOC_68K_TLS_LDO16:
1303 	    case BFD_RELOC_68K_TLS_LDO8:
1304 	    case BFD_RELOC_68K_TLS_IE32:
1305 	    case BFD_RELOC_68K_TLS_IE16:
1306 	    case BFD_RELOC_68K_TLS_IE8:
1307 	    case BFD_RELOC_68K_TLS_LE32:
1308 	    case BFD_RELOC_68K_TLS_LE16:
1309 	    case BFD_RELOC_68K_TLS_LE8:
1310 	      break;
1311 	    default:
1312 	      as_bad_where (fixp->fx_file, fixp->fx_line,
1313 			    _("Cannot make %s relocation PC relative"),
1314 			    bfd_get_reloc_code_name (code));
1315 	    }
1316 	}
1317     }
1318   else
1319     {
1320 #define F(SZ,PCREL)		(((SZ) << 1) + (PCREL))
1321       switch (F (fixp->fx_size, fixp->fx_pcrel))
1322 	{
1323 #define MAP(SZ,PCREL,TYPE)	case F(SZ,PCREL): code = (TYPE); break
1324 	  MAP (1, 0, BFD_RELOC_8);
1325 	  MAP (2, 0, BFD_RELOC_16);
1326 	  MAP (4, 0, BFD_RELOC_32);
1327 	  MAP (1, 1, BFD_RELOC_8_PCREL);
1328 	  MAP (2, 1, BFD_RELOC_16_PCREL);
1329 	  MAP (4, 1, BFD_RELOC_32_PCREL);
1330 	default:
1331 	  abort ();
1332 	}
1333     }
1334 #undef F
1335 #undef MAP
1336 
1337   reloc = (arelent *) xmalloc (sizeof (arelent));
1338   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1339   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
1340   reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1341 #ifndef OBJ_ELF
1342   if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1343       && fixp->fx_addsy
1344       && S_IS_WEAK (fixp->fx_addsy)
1345       && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1346     {
1347       /* PR gas/3041 References to weak symbols must be treated as extern
1348 	 in order to be overridable by the linker, even if they are defined
1349 	 in the same object file. So the original addend must be written
1350 	 "as is" into the output section without further processing.
1351 	 The addend value must be hacked here in order to force
1352 	 bfd_install_relocation() to write the original value into the
1353 	 output section.
1354 	 1) MD_APPLY_SYM_VALUE() is set to 1 for m68k/a.out, so the symbol
1355 	 value has already been added to the addend in fixup_segment(). We
1356 	 have to remove it.
1357 	 2) bfd_install_relocation() will incorrectly treat this symbol as
1358 	 resolved, so it will write the symbol value plus its addend and
1359 	 section VMA. As a workaround we can tweak the addend value here in
1360 	 order to get the original value in the section after the call to
1361 	 bfd_install_relocation().  */
1362       reloc->addend = fixp->fx_addnumber
1363 		      /* Fix because of MD_APPLY_SYM_VALUE() */
1364 		      - S_GET_VALUE (fixp->fx_addsy)
1365 		      /* Fix for bfd_install_relocation() */
1366 		      - (S_GET_VALUE (fixp->fx_addsy)
1367 			 + S_GET_SEGMENT (fixp->fx_addsy)->vma);
1368     }
1369   else if (fixp->fx_pcrel)
1370     reloc->addend = fixp->fx_addnumber;
1371   else
1372     reloc->addend = 0;
1373 #else
1374   if (!fixp->fx_pcrel)
1375     reloc->addend = fixp->fx_addnumber;
1376   else
1377     reloc->addend = (section->vma
1378 		     + fixp->fx_pcrel_adjust
1379 		     + fixp->fx_addnumber
1380 		     + md_pcrel_from (fixp));
1381 #endif
1382 
1383   reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1384   gas_assert (reloc->howto != 0);
1385 
1386   return reloc;
1387 }
1388 
1389 /* Handle of the OPCODE hash table.  NULL means any use before
1390    m68k_ip_begin() will crash.  */
1391 static struct hash_control *op_hash;
1392 
1393 /* Assemble an m68k instruction.  */
1394 
1395 static void
m68k_ip(char * instring)1396 m68k_ip (char *instring)
1397 {
1398   char *p;
1399   struct m68k_op *opP;
1400   const struct m68k_incant *opcode;
1401   const char *s;
1402   int tmpreg = 0, baseo = 0, outro = 0, nextword;
1403   char *pdot, *pdotmove;
1404   enum m68k_size siz1, siz2;
1405   char c;
1406   int losing;
1407   int opsfound;
1408   struct m68k_op operands_backup[6];
1409   LITTLENUM_TYPE words[6];
1410   LITTLENUM_TYPE *wordp;
1411   unsigned long ok_arch = 0;
1412 
1413   if (*instring == ' ')
1414     instring++;			/* Skip leading whitespace.  */
1415 
1416   /* Scan up to end of operation-code, which MUST end in end-of-string
1417      or exactly 1 space.  */
1418   pdot = 0;
1419   for (p = instring; *p != '\0'; p++)
1420     {
1421       if (*p == ' ')
1422 	break;
1423       if (*p == '.')
1424 	pdot = p;
1425     }
1426 
1427   if (p == instring)
1428     {
1429       the_ins.error = _("No operator");
1430       return;
1431     }
1432 
1433   /* p now points to the end of the opcode name, probably whitespace.
1434      Make sure the name is null terminated by clobbering the
1435      whitespace, look it up in the hash table, then fix it back.
1436      Remove a dot, first, since the opcode tables have none.  */
1437   if (pdot != NULL)
1438     {
1439       for (pdotmove = pdot; pdotmove < p; pdotmove++)
1440 	*pdotmove = pdotmove[1];
1441       p--;
1442     }
1443 
1444   c = *p;
1445   *p = '\0';
1446   opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1447   *p = c;
1448 
1449   if (pdot != NULL)
1450     {
1451       for (pdotmove = p; pdotmove > pdot; pdotmove--)
1452 	*pdotmove = pdotmove[-1];
1453       *pdot = '.';
1454       ++p;
1455     }
1456 
1457   if (opcode == NULL)
1458     {
1459       the_ins.error = _("Unknown operator");
1460       return;
1461     }
1462 
1463   /* Found a legitimate opcode, start matching operands.  */
1464   while (*p == ' ')
1465     ++p;
1466 
1467   if (opcode->m_operands == 0)
1468     {
1469       char *old = input_line_pointer;
1470       *old = '\n';
1471       input_line_pointer = p;
1472       /* Ahh - it's a motorola style psuedo op.  */
1473       mote_pseudo_table[opcode->m_opnum].poc_handler
1474 	(mote_pseudo_table[opcode->m_opnum].poc_val);
1475       input_line_pointer = old;
1476       *old = 0;
1477 
1478       return;
1479     }
1480 
1481   if (flag_mri && opcode->m_opnum == 0)
1482     {
1483       /* In MRI mode, random garbage is allowed after an instruction
1484          which accepts no operands.  */
1485       the_ins.args = opcode->m_operands;
1486       the_ins.numargs = opcode->m_opnum;
1487       the_ins.numo = opcode->m_codenum;
1488       the_ins.opcode[0] = getone (opcode);
1489       the_ins.opcode[1] = gettwo (opcode);
1490       return;
1491     }
1492 
1493   for (opP = &the_ins.operands[0]; *p; opP++)
1494     {
1495       p = crack_operand (p, opP);
1496 
1497       if (opP->error)
1498 	{
1499 	  the_ins.error = opP->error;
1500 	  return;
1501 	}
1502     }
1503 
1504   opsfound = opP - &the_ins.operands[0];
1505 
1506   /* This ugly hack is to support the floating pt opcodes in their
1507      standard form.  Essentially, we fake a first enty of type COP#1 */
1508   if (opcode->m_operands[0] == 'I')
1509     {
1510       int n;
1511 
1512       for (n = opsfound; n > 0; --n)
1513 	the_ins.operands[n] = the_ins.operands[n - 1];
1514 
1515       memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
1516       the_ins.operands[0].mode = CONTROL;
1517       the_ins.operands[0].reg = m68k_float_copnum;
1518       opsfound++;
1519     }
1520 
1521   /* We've got the operands.  Find an opcode that'll accept them.  */
1522   for (losing = 0;;)
1523     {
1524       /* If we didn't get the right number of ops, or we have no
1525 	 common model with this pattern then reject this pattern.  */
1526 
1527       ok_arch |= opcode->m_arch;
1528       if (opsfound != opcode->m_opnum
1529 	  || ((opcode->m_arch & current_architecture) == 0))
1530 	++losing;
1531       else
1532 	{
1533 	  int i;
1534 
1535 	  /* Make a copy of the operands of this insn so that
1536 	     we can modify them safely, should we want to.  */
1537 	  gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1538 	  for (i = 0; i < opsfound; i++)
1539 	    operands_backup[i] = the_ins.operands[i];
1540 
1541 	  for (s = opcode->m_operands, opP = &operands_backup[0];
1542 	       *s && !losing;
1543 	       s += 2, opP++)
1544 	    {
1545 	      /* Warning: this switch is huge! */
1546 	      /* I've tried to organize the cases into this order:
1547 		 non-alpha first, then alpha by letter.  Lower-case
1548 		 goes directly before uppercase counterpart.  */
1549 	      /* Code with multiple case ...: gets sorted by the lowest
1550 		 case ... it belongs to.  I hope this makes sense.  */
1551 	      switch (*s)
1552 		{
1553 		case '!':
1554 		  switch (opP->mode)
1555 		    {
1556 		    case IMMED:
1557 		    case DREG:
1558 		    case AREG:
1559 		    case FPREG:
1560 		    case CONTROL:
1561 		    case AINC:
1562 		    case ADEC:
1563 		    case REGLST:
1564 		      losing++;
1565 		      break;
1566 		    default:
1567 		      break;
1568 		    }
1569 		  break;
1570 
1571 		case '<':
1572 		  switch (opP->mode)
1573 		    {
1574 		    case DREG:
1575 		    case AREG:
1576 		    case FPREG:
1577 		    case CONTROL:
1578 		    case IMMED:
1579 		    case ADEC:
1580 		    case REGLST:
1581 		      losing++;
1582 		      break;
1583 		    default:
1584 		      break;
1585 		    }
1586 		  break;
1587 
1588 		case '>':
1589 		  switch (opP->mode)
1590 		    {
1591 		    case DREG:
1592 		    case AREG:
1593 		    case FPREG:
1594 		    case CONTROL:
1595 		    case IMMED:
1596 		    case AINC:
1597 		    case REGLST:
1598 		      losing++;
1599 		      break;
1600 		    case ABSL:
1601 		      break;
1602 		    default:
1603 		      if (opP->reg == PC
1604 			  || opP->reg == ZPC)
1605 			losing++;
1606 		      break;
1607 		    }
1608 		  break;
1609 
1610 		case 'm':
1611 		  switch (opP->mode)
1612 		    {
1613 		    case DREG:
1614 		    case AREG:
1615 		    case AINDR:
1616 		    case AINC:
1617 		    case ADEC:
1618 		      break;
1619 		    default:
1620 		      losing++;
1621 		    }
1622 		  break;
1623 
1624 		case 'n':
1625 		  switch (opP->mode)
1626 		    {
1627 		    case DISP:
1628 		      break;
1629 		    default:
1630 		      losing++;
1631 		    }
1632 		  break;
1633 
1634 		case 'o':
1635 		  switch (opP->mode)
1636 		    {
1637 		    case BASE:
1638 		    case ABSL:
1639 		    case IMMED:
1640 		      break;
1641 		    default:
1642 		      losing++;
1643 		    }
1644 		  break;
1645 
1646 		case 'p':
1647 		  switch (opP->mode)
1648 		    {
1649 		    case DREG:
1650 		    case AREG:
1651 		    case AINDR:
1652 		    case AINC:
1653 		    case ADEC:
1654 		      break;
1655 		    case DISP:
1656 		      if (opP->reg == PC || opP->reg == ZPC)
1657 			losing++;
1658 		      break;
1659 		    default:
1660 		      losing++;
1661 		    }
1662 		  break;
1663 
1664 		case 'q':
1665 		  switch (opP->mode)
1666 		    {
1667 		    case DREG:
1668 		    case AINDR:
1669 		    case AINC:
1670 		    case ADEC:
1671 		      break;
1672 		    case DISP:
1673 		      if (opP->reg == PC || opP->reg == ZPC)
1674 			losing++;
1675 		      break;
1676 		    default:
1677 		      losing++;
1678 		      break;
1679 		    }
1680 		  break;
1681 
1682 		case 'v':
1683 		  switch (opP->mode)
1684 		    {
1685 		    case DREG:
1686 		    case AINDR:
1687 		    case AINC:
1688 		    case ADEC:
1689 		    case ABSL:
1690 		      break;
1691 		    case DISP:
1692 		      if (opP->reg == PC || opP->reg == ZPC)
1693 			losing++;
1694 		      break;
1695 		    default:
1696 		      losing++;
1697 		      break;
1698 		    }
1699 		  break;
1700 
1701 		case '#':
1702 		  if (opP->mode != IMMED)
1703 		    losing++;
1704 		  else if (s[1] == 'b'
1705 			   && ! isvar (&opP->disp)
1706 			   && (opP->disp.exp.X_op != O_constant
1707 			       || ! isbyte (opP->disp.exp.X_add_number)))
1708 		    losing++;
1709 		  else if (s[1] == 'B'
1710 			   && ! isvar (&opP->disp)
1711 			   && (opP->disp.exp.X_op != O_constant
1712 			       || ! issbyte (opP->disp.exp.X_add_number)))
1713 		    losing++;
1714 		  else if (s[1] == 'w'
1715 			   && ! isvar (&opP->disp)
1716 			   && (opP->disp.exp.X_op != O_constant
1717 			       || ! isword (opP->disp.exp.X_add_number)))
1718 		    losing++;
1719 		  else if (s[1] == 'W'
1720 			   && ! isvar (&opP->disp)
1721 			   && (opP->disp.exp.X_op != O_constant
1722 			       || ! issword (opP->disp.exp.X_add_number)))
1723 		    losing++;
1724 		  break;
1725 
1726 		case '^':
1727 		case 'T':
1728 		  if (opP->mode != IMMED)
1729 		    losing++;
1730 		  break;
1731 
1732 		case '$':
1733 		  if (opP->mode == AREG
1734 		      || opP->mode == CONTROL
1735 		      || opP->mode == FPREG
1736 		      || opP->mode == IMMED
1737 		      || opP->mode == REGLST
1738 		      || (opP->mode != ABSL
1739 			  && (opP->reg == PC
1740 			      || opP->reg == ZPC)))
1741 		    losing++;
1742 		  break;
1743 
1744 		case '%':
1745 		  if (opP->mode == CONTROL
1746 		      || opP->mode == FPREG
1747 		      || opP->mode == REGLST
1748 		      || opP->mode == IMMED
1749 		      || (opP->mode != ABSL
1750 			  && (opP->reg == PC
1751 			      || opP->reg == ZPC)))
1752 		    losing++;
1753 		  break;
1754 
1755 		case '&':
1756 		  switch (opP->mode)
1757 		    {
1758 		    case DREG:
1759 		    case AREG:
1760 		    case FPREG:
1761 		    case CONTROL:
1762 		    case IMMED:
1763 		    case AINC:
1764 		    case ADEC:
1765 		    case REGLST:
1766 		      losing++;
1767 		      break;
1768 		    case ABSL:
1769 		      break;
1770 		    default:
1771 		      if (opP->reg == PC
1772 			  || opP->reg == ZPC)
1773 			losing++;
1774 		      break;
1775 		    }
1776 		  break;
1777 
1778 		case '*':
1779 		  if (opP->mode == CONTROL
1780 		      || opP->mode == FPREG
1781 		      || opP->mode == REGLST)
1782 		    losing++;
1783 		  break;
1784 
1785 		case '+':
1786 		  if (opP->mode != AINC)
1787 		    losing++;
1788 		  break;
1789 
1790 		case '-':
1791 		  if (opP->mode != ADEC)
1792 		    losing++;
1793 		  break;
1794 
1795 		case '/':
1796 		  switch (opP->mode)
1797 		    {
1798 		    case AREG:
1799 		    case CONTROL:
1800 		    case FPREG:
1801 		    case AINC:
1802 		    case ADEC:
1803 		    case IMMED:
1804 		    case REGLST:
1805 		      losing++;
1806 		      break;
1807 		    default:
1808 		      break;
1809 		    }
1810 		  break;
1811 
1812 		case ';':
1813 		  switch (opP->mode)
1814 		    {
1815 		    case AREG:
1816 		    case CONTROL:
1817 		    case FPREG:
1818 		    case REGLST:
1819 		      losing++;
1820 		      break;
1821 		    default:
1822 		      break;
1823 		    }
1824 		  break;
1825 
1826 		case '?':
1827 		  switch (opP->mode)
1828 		    {
1829 		    case AREG:
1830 		    case CONTROL:
1831 		    case FPREG:
1832 		    case AINC:
1833 		    case ADEC:
1834 		    case IMMED:
1835 		    case REGLST:
1836 		      losing++;
1837 		      break;
1838 		    case ABSL:
1839 		      break;
1840 		    default:
1841 		      if (opP->reg == PC || opP->reg == ZPC)
1842 			losing++;
1843 		      break;
1844 		    }
1845 		  break;
1846 
1847 		case '@':
1848 		  switch (opP->mode)
1849 		    {
1850 		    case AREG:
1851 		    case CONTROL:
1852 		    case FPREG:
1853 		    case IMMED:
1854 		    case REGLST:
1855 		      losing++;
1856 		      break;
1857 		    default:
1858 		      break;
1859 		    }
1860 		  break;
1861 
1862 		case '~':	/* For now! (JF FOO is this right?) */
1863 		  switch (opP->mode)
1864 		    {
1865 		    case DREG:
1866 		    case AREG:
1867 		    case CONTROL:
1868 		    case FPREG:
1869 		    case IMMED:
1870 		    case REGLST:
1871 		      losing++;
1872 		      break;
1873 		    case ABSL:
1874 		      break;
1875 		    default:
1876 		      if (opP->reg == PC
1877 			  || opP->reg == ZPC)
1878 			losing++;
1879 		      break;
1880 		    }
1881 		  break;
1882 
1883 		case '3':
1884 		  if (opP->mode != CONTROL
1885 		      || (opP->reg != TT0 && opP->reg != TT1))
1886 		    losing++;
1887 		  break;
1888 
1889 		case 'A':
1890 		  if (opP->mode != AREG)
1891 		    losing++;
1892 		  break;
1893 
1894 		case 'a':
1895 		  if (opP->mode != AINDR)
1896 		    ++losing;
1897 		  break;
1898 
1899 		case '4':
1900 		  if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1901 		      && (opP->mode != DISP
1902 			   || opP->reg < ADDR0
1903 			   || opP->reg > ADDR7))
1904 		    ++losing;
1905 		  break;
1906 
1907 		case 'B':	/* FOO */
1908 		  if (opP->mode != ABSL
1909 		      || (flag_long_jumps
1910 			  && strncmp (instring, "jbsr", 4) == 0))
1911 		    losing++;
1912 		  break;
1913 
1914                 case 'b':
1915                   switch (opP->mode)
1916                     {
1917                     case IMMED:
1918                     case ABSL:
1919                     case AREG:
1920                     case FPREG:
1921                     case CONTROL:
1922                     case POST:
1923                     case PRE:
1924                     case REGLST:
1925 		      losing++;
1926 		      break;
1927 		    default:
1928 		      break;
1929                     }
1930                   break;
1931 
1932 		case 'C':
1933 		  if (opP->mode != CONTROL || opP->reg != CCR)
1934 		    losing++;
1935 		  break;
1936 
1937 		case 'd':
1938 		  if (opP->mode != DISP
1939 		      || opP->reg < ADDR0
1940 		      || opP->reg > ADDR7)
1941 		    losing++;
1942 		  break;
1943 
1944 		case 'D':
1945 		  if (opP->mode != DREG)
1946 		    losing++;
1947 		  break;
1948 
1949 		case 'E':
1950 		  if (opP->reg != ACC)
1951 		    losing++;
1952 		  break;
1953 
1954 		case 'e':
1955 		  if (opP->reg != ACC && opP->reg != ACC1
1956 		      && opP->reg != ACC2 && opP->reg != ACC3)
1957 		    losing++;
1958 		  break;
1959 
1960 		case 'F':
1961 		  if (opP->mode != FPREG)
1962 		    losing++;
1963 		  break;
1964 
1965 		case 'G':
1966 		  if (opP->reg != MACSR)
1967 		    losing++;
1968 		  break;
1969 
1970 		case 'g':
1971 		  if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1972 		    losing++;
1973 		  break;
1974 
1975 		case 'H':
1976 		  if (opP->reg != MASK)
1977 		    losing++;
1978 		  break;
1979 
1980 		case 'I':
1981 		  if (opP->mode != CONTROL
1982 		      || opP->reg < COP0
1983 		      || opP->reg > COP7)
1984 		    losing++;
1985 		  break;
1986 
1987 		case 'i':
1988 		  if (opP->mode != LSH && opP->mode != RSH)
1989 		    losing++;
1990 		  break;
1991 
1992 		case 'J':
1993 		  if (opP->mode != CONTROL
1994 		      || opP->reg < USP
1995 		      || opP->reg > last_movec_reg
1996 		      || !control_regs)
1997 		    losing++;
1998 		  else
1999 		    {
2000 		      const enum m68k_register *rp;
2001 
2002 		      for (rp = control_regs; *rp; rp++)
2003 			{
2004 			  if (*rp == opP->reg)
2005 			    break;
2006 			  /* In most CPUs RAMBAR refers to control reg
2007 	     	 	     c05 (RAMBAR1), but a few CPUs have it
2008 	     	 	     refer to c04 (RAMBAR0).  */
2009 			  else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
2010 			    {
2011 			      opP->reg = RAMBAR_ALT;
2012 			      break;
2013 			    }
2014 			}
2015 		      if (*rp == 0)
2016 			losing++;
2017 		    }
2018 		  break;
2019 
2020 		case 'k':
2021 		  if (opP->mode != IMMED)
2022 		    losing++;
2023 		  break;
2024 
2025 		case 'l':
2026 		case 'L':
2027 		  if (opP->mode == DREG
2028 		      || opP->mode == AREG
2029 		      || opP->mode == FPREG)
2030 		    {
2031 		      if (s[1] == '8')
2032 			losing++;
2033 		      else
2034 			{
2035 			  switch (opP->mode)
2036 			    {
2037 			    case DREG:
2038 			      opP->mask = 1 << (opP->reg - DATA0);
2039 			      break;
2040 			    case AREG:
2041 			      opP->mask = 1 << (opP->reg - ADDR0 + 8);
2042 			      break;
2043 			    case FPREG:
2044 			      opP->mask = 1 << (opP->reg - FP0 + 16);
2045 			      break;
2046 			    default:
2047 			      abort ();
2048 			    }
2049 			  opP->mode = REGLST;
2050 			}
2051 		    }
2052 		  else if (opP->mode == CONTROL)
2053 		    {
2054 		      if (s[1] != '8')
2055 			losing++;
2056 		      else
2057 			{
2058 			  switch (opP->reg)
2059 			    {
2060 			    case FPI:
2061 			      opP->mask = 1 << 24;
2062 			      break;
2063 			    case FPS:
2064 			      opP->mask = 1 << 25;
2065 			      break;
2066 			    case FPC:
2067 			      opP->mask = 1 << 26;
2068 			      break;
2069 			    default:
2070 			      losing++;
2071 			      break;
2072 			    }
2073 			  opP->mode = REGLST;
2074 			}
2075 		    }
2076 		  else if (opP->mode != REGLST)
2077 		    losing++;
2078 		  else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2079 		    losing++;
2080 		  else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2081 		    losing++;
2082 		  break;
2083 
2084 		case 'M':
2085 		  if (opP->mode != IMMED)
2086 		    losing++;
2087 		  else if (opP->disp.exp.X_op != O_constant
2088 			   || ! issbyte (opP->disp.exp.X_add_number))
2089 		    losing++;
2090 		  else if (! m68k_quick
2091 			   && instring[3] != 'q'
2092 			   && instring[4] != 'q')
2093 		    losing++;
2094 		  break;
2095 
2096 		case 'O':
2097 		  if (opP->mode != DREG
2098 		      && opP->mode != IMMED
2099 		      && opP->mode != ABSL)
2100 		    losing++;
2101 		  break;
2102 
2103 		case 'Q':
2104 		  if (opP->mode != IMMED)
2105 		    losing++;
2106 		  else if (opP->disp.exp.X_op != O_constant
2107 			   || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2108 		    losing++;
2109 		  else if (! m68k_quick
2110 			   && (strncmp (instring, "add", 3) == 0
2111 			       || strncmp (instring, "sub", 3) == 0)
2112 			   && instring[3] != 'q')
2113 		    losing++;
2114 		  break;
2115 
2116 		case 'R':
2117 		  if (opP->mode != DREG && opP->mode != AREG)
2118 		    losing++;
2119 		  break;
2120 
2121 		case 'r':
2122 		  if (opP->mode != AINDR
2123 		      && (opP->mode != BASE
2124 			  || (opP->reg != 0
2125 			      && opP->reg != ZADDR0)
2126 			  || opP->disp.exp.X_op != O_absent
2127 			  || ((opP->index.reg < DATA0
2128 			       || opP->index.reg > DATA7)
2129 			      && (opP->index.reg < ADDR0
2130 				  || opP->index.reg > ADDR7))
2131 			  || opP->index.size != SIZE_UNSPEC
2132 			  || opP->index.scale != 1))
2133 		    losing++;
2134 		  break;
2135 
2136 		case 's':
2137 		  if (opP->mode != CONTROL
2138 		      || ! (opP->reg == FPI
2139 			    || opP->reg == FPS
2140 			    || opP->reg == FPC))
2141 		    losing++;
2142 		  break;
2143 
2144 		case 'S':
2145 		  if (opP->mode != CONTROL || opP->reg != SR)
2146 		    losing++;
2147 		  break;
2148 
2149 		case 't':
2150 		  if (opP->mode != IMMED)
2151 		    losing++;
2152 		  else if (opP->disp.exp.X_op != O_constant
2153 			   || TRUNC (opP->disp.exp.X_add_number) > 7)
2154 		    losing++;
2155 		  break;
2156 
2157 		case 'U':
2158 		  if (opP->mode != CONTROL || opP->reg != USP)
2159 		    losing++;
2160 		  break;
2161 
2162 		case 'x':
2163 		  if (opP->mode != IMMED)
2164 		    losing++;
2165 		  else if (opP->disp.exp.X_op != O_constant
2166 			   || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2167 			       && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
2168 		    losing++;
2169 		  break;
2170 
2171 		case 'j':
2172 		  if (opP->mode != IMMED)
2173 		    losing++;
2174 		  else if (opP->disp.exp.X_op != O_constant
2175 			   || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2176 		    losing++;
2177 		  break;
2178 
2179 		case 'K':
2180 		  if (opP->mode != IMMED)
2181 		    losing++;
2182 		  else if (opP->disp.exp.X_op != O_constant
2183 			   || TRUNC (opP->disp.exp.X_add_number) > 511)
2184 		    losing++;
2185 		  break;
2186 
2187 		  /* JF these are out of order.  We could put them
2188 		     in order if we were willing to put up with
2189 		     bunches of #ifdef m68851s in the code.
2190 
2191 		     Don't forget that you need these operands
2192 		     to use 68030 MMU instructions.  */
2193 #ifndef NO_68851
2194 		  /* Memory addressing mode used by pflushr.  */
2195 		case '|':
2196 		  if (opP->mode == CONTROL
2197 		      || opP->mode == FPREG
2198 		      || opP->mode == DREG
2199 		      || opP->mode == AREG
2200 		      || opP->mode == REGLST)
2201 		    losing++;
2202 		  /* We should accept immediate operands, but they
2203                      supposedly have to be quad word, and we don't
2204                      handle that.  I would like to see what a Motorola
2205                      assembler does before doing something here.  */
2206 		  if (opP->mode == IMMED)
2207 		    losing++;
2208 		  break;
2209 
2210 		case 'f':
2211 		  if (opP->mode != CONTROL
2212 		      || (opP->reg != SFC && opP->reg != DFC))
2213 		    losing++;
2214 		  break;
2215 
2216 		case '0':
2217 		  if (opP->mode != CONTROL || opP->reg != TC)
2218 		    losing++;
2219 		  break;
2220 
2221 		case '1':
2222 		  if (opP->mode != CONTROL || opP->reg != AC)
2223 		    losing++;
2224 		  break;
2225 
2226 		case '2':
2227 		  if (opP->mode != CONTROL
2228 		      || (opP->reg != CAL
2229 			  && opP->reg != VAL
2230 			  && opP->reg != SCC))
2231 		    losing++;
2232 		  break;
2233 
2234 		case 'V':
2235 		  if (opP->mode != CONTROL
2236 		      || opP->reg != VAL)
2237 		    losing++;
2238 		  break;
2239 
2240 		case 'W':
2241 		  if (opP->mode != CONTROL
2242 		      || (opP->reg != DRP
2243 			  && opP->reg != SRP
2244 			  && opP->reg != CRP))
2245 		    losing++;
2246 		  break;
2247 
2248 		case 'w':
2249 		  switch (opP->mode)
2250 		    {
2251 		      case IMMED:
2252 		      case ABSL:
2253 		      case AREG:
2254 		      case DREG:
2255 		      case FPREG:
2256 		      case CONTROL:
2257 		      case POST:
2258 		      case PRE:
2259 		      case REGLST:
2260 			losing++;
2261 			break;
2262 		      default:
2263 			break;
2264 		    }
2265 		  break;
2266 
2267 		case 'X':
2268 		  if (opP->mode != CONTROL
2269 		      || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2270 			  && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2271 		    losing++;
2272 		  break;
2273 
2274 		case 'Y':
2275 		  if (opP->mode != CONTROL || opP->reg != PSR)
2276 		    losing++;
2277 		  break;
2278 
2279 		case 'Z':
2280 		  if (opP->mode != CONTROL || opP->reg != PCSR)
2281 		    losing++;
2282 		  break;
2283 #endif
2284 		case 'c':
2285 		  if (opP->mode != CONTROL
2286 		      || (opP->reg != NC
2287 			  && opP->reg != IC
2288 			  && opP->reg != DC
2289 			  && opP->reg != BC))
2290 		    losing++;
2291 		  break;
2292 
2293 		case '_':
2294 		  if (opP->mode != ABSL)
2295 		    ++losing;
2296 		  break;
2297 
2298 		case 'u':
2299 		  if (opP->reg < DATA0L || opP->reg > ADDR7U)
2300 		    losing++;
2301 		  /* FIXME: kludge instead of fixing parser:
2302                      upper/lower registers are *not* CONTROL
2303                      registers, but ordinary ones.  */
2304 		  if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2305 		      || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2306 		    opP->mode = DREG;
2307 		  else
2308 		    opP->mode = AREG;
2309 		  break;
2310 
2311 		 case 'y':
2312 		   if (!(opP->mode == AINDR
2313 			 || (opP->mode == DISP
2314 			     && !(opP->reg == PC || opP->reg == ZPC))))
2315 		     losing++;
2316 		   break;
2317 
2318 		 case 'z':
2319 		   if (!(opP->mode == AINDR || opP->mode == DISP))
2320 		     losing++;
2321 		   break;
2322 
2323 		default:
2324 		  abort ();
2325 		}
2326 
2327 	      if (losing)
2328 		break;
2329 	    }
2330 
2331 	  /* Since we have found the correct instruction, copy
2332 	     in the modifications that we may have made.  */
2333 	  if (!losing)
2334 	    for (i = 0; i < opsfound; i++)
2335 	      the_ins.operands[i] = operands_backup[i];
2336 	}
2337 
2338       if (!losing)
2339 	break;
2340 
2341       opcode = opcode->m_next;
2342 
2343       if (!opcode)
2344 	{
2345 	  if (ok_arch
2346 	      && !(ok_arch & current_architecture))
2347 	    {
2348 	      const struct m68k_cpu *cpu;
2349 	      int any = 0;
2350 	      size_t space = 400;
2351 	      char *buf = xmalloc (space + 1);
2352 	      size_t len;
2353 	      int paren = 1;
2354 
2355 	      the_ins.error = buf;
2356 	      /* Make sure there's a NUL at the end of the buffer -- strncpy
2357 		 won't write one when it runs out of buffer.  */
2358 	      buf[space] = 0;
2359 #define APPEND(STRING) \
2360   (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2361 
2362 	      APPEND (_("invalid instruction for this architecture; needs "));
2363 	      switch (ok_arch)
2364 		{
2365 		case mcfisa_a:
2366 		  APPEND ("ColdFire ISA_A");
2367 		  break;
2368 		case mcfhwdiv:
2369 		  APPEND ("ColdFire ");
2370 		  APPEND (_("hardware divide"));
2371 		  break;
2372 		case mcfisa_aa:
2373 		  APPEND ("ColdFire ISA_A+");
2374 		  break;
2375 		case mcfisa_b:
2376 		  APPEND ("ColdFire ISA_B");
2377 		  break;
2378 		case mcfisa_c:
2379 		  APPEND ("ColdFire ISA_C");
2380 		  break;
2381 		case cfloat:
2382 		  APPEND ("ColdFire fpu");
2383 		  break;
2384 		case mfloat:
2385 		  APPEND ("M68K fpu");
2386 		  break;
2387 		case mmmu:
2388 		  APPEND ("M68K mmu");
2389 		  break;
2390 		case m68020up:
2391 		  APPEND ("68020 ");
2392 		  APPEND (_("or higher"));
2393 		  break;
2394 		case m68000up:
2395 		  APPEND ("68000 ");
2396 		  APPEND (_("or higher"));
2397 		  break;
2398 		case m68010up:
2399 		  APPEND ("68010 ");
2400 		  APPEND (_("or higher"));
2401 		  break;
2402 		default:
2403 		  paren = 0;
2404 		}
2405 	      if (paren)
2406 		APPEND (" (");
2407 
2408 	      for (cpu = m68k_cpus; cpu->name; cpu++)
2409 		if (!cpu->alias && (cpu->arch & ok_arch))
2410 		  {
2411 		    const struct m68k_cpu *alias;
2412 		    int seen_master = 0;
2413 
2414 		    if (any)
2415 		      APPEND (", ");
2416 		    any = 0;
2417 		    APPEND (cpu->name);
2418 		    for (alias = cpu; alias != m68k_cpus; alias--)
2419 		      if (alias[-1].alias >= 0)
2420 			break;
2421 		    for (; !seen_master || alias->alias > 0; alias++)
2422 			{
2423 			  if (!alias->alias)
2424 			    seen_master = 1;
2425 			  else
2426 			    {
2427 			      if (any)
2428 				APPEND (", ");
2429 			      else
2430 				APPEND (" [");
2431 			      APPEND (alias->name);
2432 			      any = 1;
2433 			    }
2434 			}
2435 		    if (any)
2436 		      APPEND ("]");
2437 		    any = 1;
2438 		  }
2439 	      if (paren)
2440 		APPEND (")");
2441 #undef APPEND
2442 	      if (!space)
2443 		{
2444 		  /* We ran out of space, so replace the end of the list
2445 		     with ellipsis.  */
2446 		  buf -= 4;
2447 		  while (*buf != ' ')
2448 		    buf--;
2449 		  strcpy (buf, " ...");
2450 		}
2451 	    }
2452 	  else
2453 	    the_ins.error = _("operands mismatch");
2454 	  return;
2455 	}
2456 
2457       losing = 0;
2458     }
2459 
2460   /* Now assemble it.  */
2461   the_ins.args = opcode->m_operands;
2462   the_ins.numargs = opcode->m_opnum;
2463   the_ins.numo = opcode->m_codenum;
2464   the_ins.opcode[0] = getone (opcode);
2465   the_ins.opcode[1] = gettwo (opcode);
2466 
2467   for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2468     {
2469       int have_disp = 0;
2470       int use_pl = 0;
2471 
2472       /* This switch is a doozy.
2473 	 Watch the first step; its a big one! */
2474       switch (s[0])
2475 	{
2476 
2477 	case '*':
2478 	case '~':
2479 	case '%':
2480 	case ';':
2481 	case '@':
2482 	case '!':
2483 	case '&':
2484 	case '$':
2485 	case '?':
2486 	case '/':
2487 	case '<':
2488 	case '>':
2489 	case 'b':
2490 	case 'm':
2491 	case 'n':
2492 	case 'o':
2493 	case 'p':
2494 	case 'q':
2495 	case 'v':
2496 	case 'w':
2497 	case 'y':
2498 	case 'z':
2499 	case '4':
2500 #ifndef NO_68851
2501 	case '|':
2502 #endif
2503 	  switch (opP->mode)
2504 	    {
2505 	    case IMMED:
2506 	      tmpreg = 0x3c;	/* 7.4 */
2507 	      if (strchr ("bwl", s[1]))
2508 		nextword = get_num (&opP->disp, 90);
2509 	      else
2510 		nextword = get_num (&opP->disp, 0);
2511 	      if (isvar (&opP->disp))
2512 		add_fix (s[1], &opP->disp, 0, 0);
2513 	      switch (s[1])
2514 		{
2515 		case 'b':
2516 		  if (!isbyte (nextword))
2517 		    opP->error = _("operand out of range");
2518 		  addword (nextword);
2519 		  baseo = 0;
2520 		  break;
2521 		case 'w':
2522 		  if (!isword (nextword))
2523 		    opP->error = _("operand out of range");
2524 		  addword (nextword);
2525 		  baseo = 0;
2526 		  break;
2527 		case 'W':
2528 		  if (!issword (nextword))
2529 		    opP->error = _("operand out of range");
2530 		  addword (nextword);
2531 		  baseo = 0;
2532 		  break;
2533 		case 'l':
2534 		  addword (nextword >> 16);
2535 		  addword (nextword);
2536 		  baseo = 0;
2537 		  break;
2538 
2539 		case 'f':
2540 		  baseo = 2;
2541 		  outro = 8;
2542 		  break;
2543 		case 'F':
2544 		  baseo = 4;
2545 		  outro = 11;
2546 		  break;
2547 		case 'x':
2548 		  baseo = 6;
2549 		  outro = 15;
2550 		  break;
2551 		case 'p':
2552 		  baseo = 6;
2553 		  outro = -1;
2554 		  break;
2555 		default:
2556 		  abort ();
2557 		}
2558 	      if (!baseo)
2559 		break;
2560 
2561 	      /* We gotta put out some float.  */
2562 	      if (op (&opP->disp) != O_big)
2563 		{
2564 		  valueT val;
2565 		  int gencnt;
2566 
2567 		  /* Can other cases happen here?  */
2568 		  if (op (&opP->disp) != O_constant)
2569 		    abort ();
2570 
2571 		  val = (valueT) offs (&opP->disp);
2572 		  gencnt = 0;
2573 		  do
2574 		    {
2575 		      generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2576 		      val >>= LITTLENUM_NUMBER_OF_BITS;
2577 		      ++gencnt;
2578 		    }
2579 		  while (val != 0);
2580 		  offs (&opP->disp) = gencnt;
2581 		}
2582 	      if (offs (&opP->disp) > 0)
2583 		{
2584 		  if (offs (&opP->disp) > baseo)
2585 		    {
2586 		      as_warn (_("Bignum too big for %c format; truncated"),
2587 			       s[1]);
2588 		      offs (&opP->disp) = baseo;
2589 		    }
2590 		  baseo -= offs (&opP->disp);
2591 		  while (baseo--)
2592 		    addword (0);
2593 		  for (wordp = generic_bignum + offs (&opP->disp) - 1;
2594 		       offs (&opP->disp)--;
2595 		       --wordp)
2596 		    addword (*wordp);
2597 		  break;
2598 		}
2599 	      gen_to_words (words, baseo, (long) outro);
2600 	      for (wordp = words; baseo--; wordp++)
2601 		addword (*wordp);
2602 	      break;
2603 	    case DREG:
2604 	      tmpreg = opP->reg - DATA;	/* 0.dreg */
2605 	      break;
2606 	    case AREG:
2607 	      tmpreg = 0x08 + opP->reg - ADDR;	/* 1.areg */
2608 	      break;
2609 	    case AINDR:
2610 	      tmpreg = 0x10 + opP->reg - ADDR;	/* 2.areg */
2611 	      break;
2612 	    case ADEC:
2613 	      tmpreg = 0x20 + opP->reg - ADDR;	/* 4.areg */
2614 	      break;
2615 	    case AINC:
2616 	      tmpreg = 0x18 + opP->reg - ADDR;	/* 3.areg */
2617 	      break;
2618 	    case DISP:
2619 
2620 	      nextword = get_num (&opP->disp, 90);
2621 
2622 	      /* Convert mode 5 addressing with a zero offset into
2623 		 mode 2 addressing to reduce the instruction size by a
2624 		 word.  */
2625 	      if (! isvar (&opP->disp)
2626 		  && (nextword == 0)
2627 		  && (opP->disp.size == SIZE_UNSPEC)
2628 		  && (opP->reg >= ADDR0)
2629 		  && (opP->reg <= ADDR7))
2630 		{
2631 		  tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2632 		  break;
2633 		}
2634 
2635 	      if (opP->reg == PC
2636 		  && ! isvar (&opP->disp)
2637 		  && m68k_abspcadd)
2638 		{
2639 		  opP->disp.exp.X_op = O_symbol;
2640 		  opP->disp.exp.X_add_symbol =
2641 		    section_symbol (absolute_section);
2642 		}
2643 
2644 	      /* Force into index mode.  Hope this works.  */
2645 
2646 	      /* We do the first bit for 32-bit displacements, and the
2647 		 second bit for 16 bit ones.  It is possible that we
2648 		 should make the default be WORD instead of LONG, but
2649 		 I think that'd break GCC, so we put up with a little
2650 		 inefficiency for the sake of working output.  */
2651 
2652 	      if (!issword (nextword)
2653 		  || (isvar (&opP->disp)
2654 		      && ((opP->disp.size == SIZE_UNSPEC
2655 			   && flag_short_refs == 0
2656 			   && cpu_of_arch (current_architecture) >= m68020
2657 			   && ! arch_coldfire_p (current_architecture))
2658 			  || opP->disp.size == SIZE_LONG)))
2659 		{
2660 		  if (cpu_of_arch (current_architecture) < m68020
2661 		      || arch_coldfire_p (current_architecture))
2662 		    opP->error =
2663 		      _("displacement too large for this architecture; needs 68020 or higher");
2664 		  if (opP->reg == PC)
2665 		    tmpreg = 0x3B;	/* 7.3 */
2666 		  else
2667 		    tmpreg = 0x30 + opP->reg - ADDR;	/* 6.areg */
2668 		  if (isvar (&opP->disp))
2669 		    {
2670 		      if (opP->reg == PC)
2671 			{
2672 			  if (opP->disp.size == SIZE_LONG
2673 #ifdef OBJ_ELF
2674 			      /* If the displacement needs pic
2675 				 relocation it cannot be relaxed.  */
2676 			      || opP->disp.pic_reloc != pic_none
2677 #endif
2678 			      )
2679 			    {
2680 			      addword (0x0170);
2681 			      add_fix ('l', &opP->disp, 1, 2);
2682 			    }
2683 			  else
2684 			    {
2685 			      add_frag (adds (&opP->disp),
2686 					SEXT (offs (&opP->disp)),
2687 					TAB (PCREL1632, SZ_UNDEF));
2688 			      break;
2689 			    }
2690 			}
2691 		      else
2692 			{
2693 			  addword (0x0170);
2694 			  add_fix ('l', &opP->disp, 0, 0);
2695 			}
2696 		    }
2697 		  else
2698 		    addword (0x0170);
2699 		  addword (nextword >> 16);
2700 		}
2701 	      else
2702 		{
2703 		  if (opP->reg == PC)
2704 		    tmpreg = 0x3A;	/* 7.2 */
2705 		  else
2706 		    tmpreg = 0x28 + opP->reg - ADDR;	/* 5.areg */
2707 
2708 		  if (isvar (&opP->disp))
2709 		    {
2710 		      if (opP->reg == PC)
2711 			{
2712 			  add_fix ('w', &opP->disp, 1, 0);
2713 			}
2714 		      else
2715 			add_fix ('w', &opP->disp, 0, 0);
2716 		    }
2717 		}
2718 	      addword (nextword);
2719 	      break;
2720 
2721 	    case POST:
2722 	    case PRE:
2723 	    case BASE:
2724 	      nextword = 0;
2725 	      baseo = get_num (&opP->disp, 90);
2726 	      if (opP->mode == POST || opP->mode == PRE)
2727 		outro = get_num (&opP->odisp, 90);
2728 	      /* Figure out the `addressing mode'.
2729 		 Also turn on the BASE_DISABLE bit, if needed.  */
2730 	      if (opP->reg == PC || opP->reg == ZPC)
2731 		{
2732 		  tmpreg = 0x3b;	/* 7.3 */
2733 		  if (opP->reg == ZPC)
2734 		    nextword |= 0x80;
2735 		}
2736 	      else if (opP->reg == 0)
2737 		{
2738 		  nextword |= 0x80;
2739 		  tmpreg = 0x30;	/* 6.garbage */
2740 		}
2741 	      else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2742 		{
2743 		  nextword |= 0x80;
2744 		  tmpreg = 0x30 + opP->reg - ZADDR0;
2745 		}
2746 	      else
2747 		tmpreg = 0x30 + opP->reg - ADDR;	/* 6.areg */
2748 
2749 	      siz1 = opP->disp.size;
2750 	      if (opP->mode == POST || opP->mode == PRE)
2751 		siz2 = opP->odisp.size;
2752 	      else
2753 		siz2 = SIZE_UNSPEC;
2754 
2755 	      /* Index register stuff.  */
2756 	      if (opP->index.reg != 0
2757 		  && opP->index.reg >= DATA
2758 		  && opP->index.reg <= ADDR7)
2759 		{
2760 		  nextword |= (opP->index.reg - DATA) << 12;
2761 
2762 		  if (opP->index.size == SIZE_LONG
2763 		      || (opP->index.size == SIZE_UNSPEC
2764 			  && m68k_index_width_default == SIZE_LONG))
2765 		    nextword |= 0x800;
2766 
2767 		  if ((opP->index.scale != 1
2768 		       && cpu_of_arch (current_architecture) < m68020)
2769 		      || (opP->index.scale == 8
2770 			  && (arch_coldfire_p (current_architecture)
2771                               && !arch_coldfire_fpu (current_architecture))))
2772 		    {
2773 		      opP->error =
2774 			_("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2775 		    }
2776 
2777 		  if (arch_coldfire_p (current_architecture)
2778 		      && opP->index.size == SIZE_WORD)
2779 		    opP->error = _("invalid index size for coldfire");
2780 
2781 		  switch (opP->index.scale)
2782 		    {
2783 		    case 1:
2784 		      break;
2785 		    case 2:
2786 		      nextword |= 0x200;
2787 		      break;
2788 		    case 4:
2789 		      nextword |= 0x400;
2790 		      break;
2791 		    case 8:
2792 		      nextword |= 0x600;
2793 		      break;
2794 		    default:
2795 		      abort ();
2796 		    }
2797 		  /* IF its simple,
2798 		     GET US OUT OF HERE! */
2799 
2800 		  /* Must be INDEX, with an index register.  Address
2801 		     register cannot be ZERO-PC, and either :b was
2802 		     forced, or we know it will fit.  For a 68000 or
2803 		     68010, force this mode anyways, because the
2804 		     larger modes aren't supported.  */
2805 		  if (opP->mode == BASE
2806 		      && ((opP->reg >= ADDR0
2807 			   && opP->reg <= ADDR7)
2808 			  || opP->reg == PC))
2809 		    {
2810 		      if (siz1 == SIZE_BYTE
2811 			  || cpu_of_arch (current_architecture) < m68020
2812 			  || arch_coldfire_p (current_architecture)
2813 			  || (siz1 == SIZE_UNSPEC
2814 			      && ! isvar (&opP->disp)
2815 			      && issbyte (baseo)))
2816 			{
2817  			  nextword += baseo & 0xff;
2818  			  addword (nextword);
2819  			  if (isvar (&opP->disp))
2820 			    {
2821 			      /* Do a byte relocation.  If it doesn't
2822 				 fit (possible on m68000) let the
2823 				 fixup processing complain later.  */
2824 			      if (opP->reg == PC)
2825 				add_fix ('B', &opP->disp, 1, 1);
2826 			      else
2827 				add_fix ('B', &opP->disp, 0, 0);
2828 			    }
2829 			  else if (siz1 != SIZE_BYTE)
2830 			    {
2831 			      if (siz1 != SIZE_UNSPEC)
2832 				as_warn (_("Forcing byte displacement"));
2833 			      if (! issbyte (baseo))
2834 				opP->error = _("byte displacement out of range");
2835 			    }
2836 
2837 			  break;
2838 			}
2839 		      else if (siz1 == SIZE_UNSPEC
2840 			       && opP->reg == PC
2841 			       && isvar (&opP->disp)
2842 			       && subs (&opP->disp) == NULL
2843 #ifdef OBJ_ELF
2844 			       /* If the displacement needs pic
2845 				  relocation it cannot be relaxed.  */
2846 			       && opP->disp.pic_reloc == pic_none
2847 #endif
2848 			       )
2849 			{
2850 			  /* The code in md_convert_frag_1 needs to be
2851                              able to adjust nextword.  Call frag_grow
2852                              to ensure that we have enough space in
2853                              the frag obstack to make all the bytes
2854                              contiguous.  */
2855 			  frag_grow (14);
2856 			  nextword += baseo & 0xff;
2857 			  addword (nextword);
2858 			  add_frag (adds (&opP->disp),
2859 				    SEXT (offs (&opP->disp)),
2860 				    TAB (PCINDEX, SZ_UNDEF));
2861 
2862 			  break;
2863 			}
2864 		    }
2865 		}
2866 	      else
2867 		{
2868 		  nextword |= 0x40;	/* No index reg.  */
2869 		  if (opP->index.reg >= ZDATA0
2870 		      && opP->index.reg <= ZDATA7)
2871 		    nextword |= (opP->index.reg - ZDATA0) << 12;
2872 		  else if (opP->index.reg >= ZADDR0
2873 			   || opP->index.reg <= ZADDR7)
2874 		    nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2875 		}
2876 
2877 	      /* It isn't simple.  */
2878 
2879 	      if (cpu_of_arch (current_architecture) < m68020
2880 		  || arch_coldfire_p (current_architecture))
2881 		opP->error =
2882 		  _("invalid operand mode for this architecture; needs 68020 or higher");
2883 
2884 	      nextword |= 0x100;
2885 	      /* If the guy specified a width, we assume that it is
2886 		 wide enough.  Maybe it isn't.  If so, we lose.  */
2887 	      switch (siz1)
2888 		{
2889 		case SIZE_UNSPEC:
2890 		  if (isvar (&opP->disp)
2891 		      ? m68k_rel32
2892 		      : ! issword (baseo))
2893 		    {
2894 		      siz1 = SIZE_LONG;
2895 		      nextword |= 0x30;
2896 		    }
2897 		  else if (! isvar (&opP->disp) && baseo == 0)
2898 		    nextword |= 0x10;
2899 		  else
2900 		    {
2901 		      nextword |= 0x20;
2902 		      siz1 = SIZE_WORD;
2903 		    }
2904 		  break;
2905 		case SIZE_BYTE:
2906 		  as_warn (_(":b not permitted; defaulting to :w"));
2907 		  /* Fall through.  */
2908 		case SIZE_WORD:
2909 		  nextword |= 0x20;
2910 		  break;
2911 		case SIZE_LONG:
2912 		  nextword |= 0x30;
2913 		  break;
2914 		}
2915 
2916 	      /* Figure out inner displacement stuff.  */
2917 	      if (opP->mode == POST || opP->mode == PRE)
2918 		{
2919 		  if (cpu_of_arch (current_architecture) & cpu32)
2920 		    opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2921 		  switch (siz2)
2922 		    {
2923 		    case SIZE_UNSPEC:
2924 		      if (isvar (&opP->odisp)
2925 			  ? m68k_rel32
2926 			  : ! issword (outro))
2927 			{
2928 			  siz2 = SIZE_LONG;
2929 			  nextword |= 0x3;
2930 			}
2931 		      else if (! isvar (&opP->odisp) && outro == 0)
2932 			nextword |= 0x1;
2933 		      else
2934 			{
2935 			  nextword |= 0x2;
2936 			  siz2 = SIZE_WORD;
2937 			}
2938 		      break;
2939 		    case 1:
2940 		      as_warn (_(":b not permitted; defaulting to :w"));
2941 		      /* Fall through.  */
2942 		    case 2:
2943 		      nextword |= 0x2;
2944 		      break;
2945 		    case 3:
2946 		      nextword |= 0x3;
2947 		      break;
2948 		    }
2949 		  if (opP->mode == POST
2950 		      && (nextword & 0x40) == 0)
2951 		    nextword |= 0x04;
2952 		}
2953 	      addword (nextword);
2954 
2955 	      if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2956 		{
2957 		  if (opP->reg == PC || opP->reg == ZPC)
2958 		    add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2959 		  else
2960 		    add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2961 		}
2962 	      if (siz1 == SIZE_LONG)
2963 		addword (baseo >> 16);
2964 	      if (siz1 != SIZE_UNSPEC)
2965 		addword (baseo);
2966 
2967 	      if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2968 		add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2969 	      if (siz2 == SIZE_LONG)
2970 		addword (outro >> 16);
2971 	      if (siz2 != SIZE_UNSPEC)
2972 		addword (outro);
2973 
2974 	      break;
2975 
2976 	    case ABSL:
2977 	      nextword = get_num (&opP->disp, 90);
2978 	      switch (opP->disp.size)
2979 		{
2980 		default:
2981 		  abort ();
2982 		case SIZE_UNSPEC:
2983 		  if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2984 		    {
2985 		      tmpreg = 0x38;	/* 7.0 */
2986 		      addword (nextword);
2987 		      break;
2988 		    }
2989 		  if (isvar (&opP->disp)
2990 		      && !subs (&opP->disp)
2991 		      && adds (&opP->disp)
2992 #ifdef OBJ_ELF
2993 		      /* If the displacement needs pic relocation it
2994 			 cannot be relaxed.  */
2995 		      && opP->disp.pic_reloc == pic_none
2996 #endif
2997 		      && !flag_long_jumps
2998 		      && !strchr ("~%&$?", s[0]))
2999 		    {
3000 		      tmpreg = 0x3A;	/* 7.2 */
3001 		      add_frag (adds (&opP->disp),
3002 				SEXT (offs (&opP->disp)),
3003 				TAB (ABSTOPCREL, SZ_UNDEF));
3004 		      break;
3005 		    }
3006 		  /* Fall through into long.  */
3007 		case SIZE_LONG:
3008 		  if (isvar (&opP->disp))
3009 		    add_fix ('l', &opP->disp, 0, 0);
3010 
3011 		  tmpreg = 0x39;/* 7.1 mode */
3012 		  addword (nextword >> 16);
3013 		  addword (nextword);
3014 		  break;
3015 
3016 		case SIZE_BYTE:
3017 		  as_bad (_("unsupported byte value; use a different suffix"));
3018 		  /* Fall through.  */
3019 
3020 		case SIZE_WORD:
3021 		  if (isvar (&opP->disp))
3022 		    add_fix ('w', &opP->disp, 0, 0);
3023 
3024 		  tmpreg = 0x38;/* 7.0 mode */
3025 		  addword (nextword);
3026 		  break;
3027 		}
3028 	      break;
3029 	    case CONTROL:
3030 	    case FPREG:
3031 	    default:
3032 	      as_bad (_("unknown/incorrect operand"));
3033 	      /* abort (); */
3034 	    }
3035 
3036 	  /* If s[0] is '4', then this is for the mac instructions
3037 	     that can have a trailing_ampersand set.  If so, set 0x100
3038 	     bit on tmpreg so install_gen_operand can check for it and
3039 	     set the appropriate bit (word2, bit 5).  */
3040 	  if (s[0] == '4')
3041 	    {
3042 	      if (opP->trailing_ampersand)
3043 		tmpreg |= 0x100;
3044 	    }
3045 	  install_gen_operand (s[1], tmpreg);
3046 	  break;
3047 
3048 	case '#':
3049 	case '^':
3050 	  switch (s[1])
3051 	    {			/* JF: I hate floating point! */
3052 	    case 'j':
3053 	      tmpreg = 70;
3054 	      break;
3055 	    case '8':
3056 	      tmpreg = 20;
3057 	      break;
3058 	    case 'C':
3059 	      tmpreg = 50;
3060 	      break;
3061 	    case '3':
3062 	    default:
3063 	      tmpreg = 90;
3064 	      break;
3065 	    }
3066 	  tmpreg = get_num (&opP->disp, tmpreg);
3067 	  if (isvar (&opP->disp))
3068 	    add_fix (s[1], &opP->disp, 0, 0);
3069 	  switch (s[1])
3070 	    {
3071 	    case 'b':		/* Danger:  These do no check for
3072 				   certain types of overflow.
3073 				   user beware! */
3074 	      if (!isbyte (tmpreg))
3075 		opP->error = _("out of range");
3076 	      insop (tmpreg, opcode);
3077 	      if (isvar (&opP->disp))
3078 		the_ins.reloc[the_ins.nrel - 1].n =
3079 		  (opcode->m_codenum) * 2 + 1;
3080 	      break;
3081 	    case 'B':
3082 	      if (!issbyte (tmpreg))
3083 		opP->error = _("out of range");
3084 	      the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3085 	      if (isvar (&opP->disp))
3086 		the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3087 	      break;
3088 	    case 'w':
3089 	      if (!isword (tmpreg))
3090 		opP->error = _("out of range");
3091 	      insop (tmpreg, opcode);
3092 	      if (isvar (&opP->disp))
3093 		the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3094 	      break;
3095 	    case 'W':
3096 	      if (!issword (tmpreg))
3097 		opP->error = _("out of range");
3098 	      insop (tmpreg, opcode);
3099 	      if (isvar (&opP->disp))
3100 		the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3101 	      break;
3102 	    case 'l':
3103 	      /* Because of the way insop works, we put these two out
3104 		 backwards.  */
3105 	      insop (tmpreg, opcode);
3106 	      insop (tmpreg >> 16, opcode);
3107 	      if (isvar (&opP->disp))
3108 		the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3109 	      break;
3110 	    case '3':
3111 	      tmpreg &= 0xFF;
3112 	    case '8':
3113 	    case 'C':
3114 	    case 'j':
3115 	      install_operand (s[1], tmpreg);
3116 	      break;
3117 	    default:
3118 	      abort ();
3119 	    }
3120 	  break;
3121 
3122 	case '+':
3123 	case '-':
3124 	case 'A':
3125 	case 'a':
3126 	  install_operand (s[1], opP->reg - ADDR);
3127 	  break;
3128 
3129 	case 'B':
3130 	  tmpreg = get_num (&opP->disp, 90);
3131 
3132 	  switch (s[1])
3133 	    {
3134 	    case 'B':
3135 	      add_fix ('B', &opP->disp, 1, -1);
3136 	      break;
3137 	    case 'W':
3138 	      add_fix ('w', &opP->disp, 1, 0);
3139 	      addword (0);
3140 	      break;
3141 	    case 'L':
3142 	    long_branch:
3143 	      the_ins.opcode[0] |= 0xff;
3144 	      add_fix ('l', &opP->disp, 1, 0);
3145 	      addword (0);
3146 	      addword (0);
3147 	      break;
3148 	    case 'g': /* Conditional branch */
3149 	      have_disp = HAVE_LONG_CALL (current_architecture);
3150 	      goto var_branch;
3151 
3152 	    case 'b': /* Unconditional branch */
3153 	      have_disp = HAVE_LONG_BRANCH (current_architecture);
3154 	      use_pl = LONG_BRANCH_VIA_COND (current_architecture);
3155 	      goto var_branch;
3156 
3157 	    case 's': /* Unconditional subroutine */
3158 	      have_disp = HAVE_LONG_CALL (current_architecture);
3159 
3160 	      var_branch:
3161 	      if (subs (&opP->disp)	/* We can't relax it.  */
3162 #ifdef OBJ_ELF
3163 		  /* If the displacement needs pic relocation it cannot be
3164 		     relaxed.  */
3165 		  || opP->disp.pic_reloc != pic_none
3166 #endif
3167 		  || 0)
3168 		{
3169 		  if (!have_disp)
3170 		    as_warn (_("Can't use long branches on this architecture"));
3171 		  goto long_branch;
3172 		}
3173 
3174 	      /* This could either be a symbol, or an absolute
3175 		 address.  If it's an absolute address, turn it into
3176 		 an absolute jump right here and keep it out of the
3177 		 relaxer.  */
3178 	      if (adds (&opP->disp) == 0)
3179 		{
3180 		  if (the_ins.opcode[0] == 0x6000)	/* jbra */
3181 		    the_ins.opcode[0] = 0x4EF9;
3182 		  else if (the_ins.opcode[0] == 0x6100)	/* jbsr */
3183 		    the_ins.opcode[0] = 0x4EB9;
3184 		  else					/* jCC */
3185 		    {
3186 		      the_ins.opcode[0] ^= 0x0100;
3187 		      the_ins.opcode[0] |= 0x0006;
3188 		      addword (0x4EF9);
3189 		    }
3190 		  add_fix ('l', &opP->disp, 0, 0);
3191 		  addword (0);
3192 		  addword (0);
3193 		  break;
3194 		}
3195 
3196 	      /* Now we know it's going into the relaxer.  Now figure
3197 		 out which mode.  We try in this order of preference:
3198 		 long branch, absolute jump, byte/word branches only.  */
3199 	      if (have_disp)
3200 		add_frag (adds (&opP->disp),
3201 			  SEXT (offs (&opP->disp)),
3202 			  TAB (BRANCHBWL, SZ_UNDEF));
3203 	      else if (! flag_keep_pcrel)
3204 		{
3205 		  if ((the_ins.opcode[0] == 0x6000)
3206 		      || (the_ins.opcode[0] == 0x6100))
3207 		    add_frag (adds (&opP->disp),
3208 			      SEXT (offs (&opP->disp)),
3209 			      TAB (BRABSJUNC, SZ_UNDEF));
3210 		  else
3211 		    add_frag (adds (&opP->disp),
3212 			      SEXT (offs (&opP->disp)),
3213 			      TAB (BRABSJCOND, SZ_UNDEF));
3214 		}
3215 	      else
3216 		add_frag (adds (&opP->disp),
3217 			  SEXT (offs (&opP->disp)),
3218 			  (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3219 			   : TAB (BRANCHBW, SZ_UNDEF)));
3220 	      break;
3221 	    case 'w':
3222 	      if (isvar (&opP->disp))
3223 		{
3224 		  /* Check for DBcc instructions.  We can relax them,
3225 		     but only if we have long branches and/or absolute
3226 		     jumps.  */
3227 		  if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3228 		      && (HAVE_LONG_BRANCH (current_architecture)
3229 			  || ! flag_keep_pcrel))
3230 		    {
3231 		      if (HAVE_LONG_BRANCH (current_architecture))
3232 			add_frag (adds (&opP->disp),
3233 				  SEXT (offs (&opP->disp)),
3234 				  TAB (DBCCLBR, SZ_UNDEF));
3235 		      else
3236 			add_frag (adds (&opP->disp),
3237 				  SEXT (offs (&opP->disp)),
3238 				  TAB (DBCCABSJ, SZ_UNDEF));
3239 		      break;
3240 		    }
3241 		  add_fix ('w', &opP->disp, 1, 0);
3242 		}
3243 	      addword (0);
3244 	      break;
3245 	    case 'C':		/* Fixed size LONG coproc branches.  */
3246 	      add_fix ('l', &opP->disp, 1, 0);
3247 	      addword (0);
3248 	      addword (0);
3249 	      break;
3250 	    case 'c':		/* Var size Coprocesssor branches.  */
3251 	      if (subs (&opP->disp) || (adds (&opP->disp) == 0))
3252 		{
3253 		  the_ins.opcode[the_ins.numo - 1] |= 0x40;
3254 		  add_fix ('l', &opP->disp, 1, 0);
3255 		  addword (0);
3256 		  addword (0);
3257 		}
3258 	      else
3259 		add_frag (adds (&opP->disp),
3260 			  SEXT (offs (&opP->disp)),
3261 			  TAB (FBRANCH, SZ_UNDEF));
3262 	      break;
3263 	    default:
3264 	      abort ();
3265 	    }
3266 	  break;
3267 
3268 	case 'C':		/* Ignore it.  */
3269 	  break;
3270 
3271 	case 'd':		/* JF this is a kludge.  */
3272 	  install_operand ('s', opP->reg - ADDR);
3273 	  tmpreg = get_num (&opP->disp, 90);
3274 	  if (!issword (tmpreg))
3275 	    {
3276 	      as_warn (_("Expression out of range, using 0"));
3277 	      tmpreg = 0;
3278 	    }
3279 	  addword (tmpreg);
3280 	  break;
3281 
3282 	case 'D':
3283 	  install_operand (s[1], opP->reg - DATA);
3284 	  break;
3285 
3286 	case 'e':  /* EMAC ACCx, reg/reg.  */
3287 	  install_operand (s[1], opP->reg - ACC);
3288 	  break;
3289 
3290 	case 'E':		/* Ignore it.  */
3291 	  break;
3292 
3293 	case 'F':
3294 	  install_operand (s[1], opP->reg - FP0);
3295 	  break;
3296 
3297 	case 'g':  /* EMAC ACCEXTx.  */
3298 	  install_operand (s[1], opP->reg - ACCEXT01);
3299 	  break;
3300 
3301 	case 'G':		/* Ignore it.  */
3302 	case 'H':
3303 	  break;
3304 
3305 	case 'I':
3306 	  tmpreg = opP->reg - COP0;
3307 	  install_operand (s[1], tmpreg);
3308 	  break;
3309 
3310 	case 'i':  /* MAC/EMAC scale factor.  */
3311 	  install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3312 	  break;
3313 
3314 	case 'J':		/* JF foo.  */
3315 	  switch (opP->reg)
3316 	    {
3317 	    case SFC:
3318 	      tmpreg = 0x000;
3319 	      break;
3320 	    case DFC:
3321 	      tmpreg = 0x001;
3322 	      break;
3323 	    case CACR:
3324 	      tmpreg = 0x002;
3325 	      break;
3326 	    case TC:
3327 	    case ASID:
3328 	      tmpreg = 0x003;
3329 	      break;
3330 	    case ACR0:
3331 	    case ITT0:
3332 	      tmpreg = 0x004;
3333 	      break;
3334 	    case ACR1:
3335 	    case ITT1:
3336 	      tmpreg = 0x005;
3337 	      break;
3338 	    case ACR2:
3339 	    case DTT0:
3340 	      tmpreg = 0x006;
3341 	      break;
3342 	    case ACR3:
3343 	    case DTT1:
3344 	      tmpreg = 0x007;
3345 	      break;
3346 	    case BUSCR:
3347 	    case MMUBAR:
3348 	      tmpreg = 0x008;
3349 	      break;
3350 	    case RGPIOBAR:
3351 	      tmpreg = 0x009;
3352 	      break;
3353 	    case ACR4:
3354 	    case ACR5:
3355 	    case ACR6:
3356 	    case ACR7:
3357 	      tmpreg = 0x00c + (opP->reg - ACR4);
3358 	      break;
3359 
3360 	    case USP:
3361 	      tmpreg = 0x800;
3362 	      break;
3363 	    case VBR:
3364 	      tmpreg = 0x801;
3365 	      break;
3366 	    case CAAR:
3367 	    case CPUCR:
3368 	      tmpreg = 0x802;
3369 	      break;
3370 	    case MSP:
3371 	      tmpreg = 0x803;
3372 	      break;
3373 	    case ISP:
3374 	      tmpreg = 0x804;
3375 	      break;
3376 	    case MMUSR:
3377 	      tmpreg = 0x805;
3378 	      break;
3379 	    case URP:
3380 	      tmpreg = 0x806;
3381 	      break;
3382 	    case SRP:
3383 	      tmpreg = 0x807;
3384 	      break;
3385 	    case PCR:
3386 	      tmpreg = 0x808;
3387 	      break;
3388             case ROMBAR:
3389             case ROMBAR0:
3390 	      tmpreg = 0xC00;
3391 	      break;
3392             case ROMBAR1:
3393               tmpreg = 0xC01;
3394               break;
3395 	    case FLASHBAR:
3396 	    case RAMBAR0:
3397 	    case RAMBAR_ALT:
3398 	      tmpreg = 0xC04;
3399 	      break;
3400 	    case RAMBAR:
3401 	    case RAMBAR1:
3402 	      tmpreg = 0xC05;
3403 	      break;
3404             case MPCR:
3405               tmpreg = 0xC0C;
3406               break;
3407             case EDRAMBAR:
3408               tmpreg = 0xC0D;
3409               break;
3410             case MBAR0:
3411             case MBAR2:
3412             case SECMBAR:
3413               tmpreg = 0xC0E;
3414               break;
3415             case MBAR1:
3416 	    case MBAR:
3417 	      tmpreg = 0xC0F;
3418 	      break;
3419             case PCR1U0:
3420               tmpreg = 0xD02;
3421               break;
3422             case PCR1L0:
3423               tmpreg = 0xD03;
3424               break;
3425             case PCR2U0:
3426               tmpreg = 0xD04;
3427               break;
3428             case PCR2L0:
3429               tmpreg = 0xD05;
3430               break;
3431             case PCR3U0:
3432               tmpreg = 0xD06;
3433               break;
3434             case PCR3L0:
3435               tmpreg = 0xD07;
3436               break;
3437             case PCR1L1:
3438               tmpreg = 0xD0A;
3439               break;
3440             case PCR1U1:
3441               tmpreg = 0xD0B;
3442               break;
3443             case PCR2L1:
3444               tmpreg = 0xD0C;
3445               break;
3446             case PCR2U1:
3447               tmpreg = 0xD0D;
3448               break;
3449             case PCR3L1:
3450               tmpreg = 0xD0E;
3451               break;
3452             case PCR3U1:
3453               tmpreg = 0xD0F;
3454               break;
3455             case CAC:
3456               tmpreg = 0xFFE;
3457               break;
3458             case MBO:
3459               tmpreg = 0xFFF;
3460               break;
3461 	    default:
3462 	      abort ();
3463 	    }
3464 	  install_operand (s[1], tmpreg);
3465 	  break;
3466 
3467 	case 'k':
3468 	  tmpreg = get_num (&opP->disp, 55);
3469 	  install_operand (s[1], tmpreg & 0x7f);
3470 	  break;
3471 
3472 	case 'l':
3473 	  tmpreg = opP->mask;
3474 	  if (s[1] == 'w')
3475 	    {
3476 	      if (tmpreg & 0x7FF0000)
3477 		as_bad (_("Floating point register in register list"));
3478 	      insop (reverse_16_bits (tmpreg), opcode);
3479 	    }
3480 	  else
3481 	    {
3482 	      if (tmpreg & 0x700FFFF)
3483 		as_bad (_("Wrong register in floating-point reglist"));
3484 	      install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3485 	    }
3486 	  break;
3487 
3488 	case 'L':
3489 	  tmpreg = opP->mask;
3490 	  if (s[1] == 'w')
3491 	    {
3492 	      if (tmpreg & 0x7FF0000)
3493 		as_bad (_("Floating point register in register list"));
3494 	      insop (tmpreg, opcode);
3495 	    }
3496 	  else if (s[1] == '8')
3497 	    {
3498 	      if (tmpreg & 0x0FFFFFF)
3499 		as_bad (_("incorrect register in reglist"));
3500 	      install_operand (s[1], tmpreg >> 24);
3501 	    }
3502 	  else
3503 	    {
3504 	      if (tmpreg & 0x700FFFF)
3505 		as_bad (_("wrong register in floating-point reglist"));
3506 	      else
3507 		install_operand (s[1], tmpreg >> 16);
3508 	    }
3509 	  break;
3510 
3511 	case 'M':
3512 	  install_operand (s[1], get_num (&opP->disp, 60));
3513 	  break;
3514 
3515 	case 'O':
3516 	  tmpreg = ((opP->mode == DREG)
3517 		    ? 0x20 + (int) (opP->reg - DATA)
3518 		    : (get_num (&opP->disp, 40) & 0x1F));
3519 	  install_operand (s[1], tmpreg);
3520 	  break;
3521 
3522 	case 'Q':
3523 	  tmpreg = get_num (&opP->disp, 10);
3524 	  if (tmpreg == 8)
3525 	    tmpreg = 0;
3526 	  install_operand (s[1], tmpreg);
3527 	  break;
3528 
3529 	case 'R':
3530 	  /* This depends on the fact that ADDR registers are eight
3531 	     more than their corresponding DATA regs, so the result
3532 	     will have the ADDR_REG bit set.  */
3533 	  install_operand (s[1], opP->reg - DATA);
3534 	  break;
3535 
3536 	case 'r':
3537 	  if (opP->mode == AINDR)
3538 	    install_operand (s[1], opP->reg - DATA);
3539 	  else
3540 	    install_operand (s[1], opP->index.reg - DATA);
3541 	  break;
3542 
3543 	case 's':
3544 	  if (opP->reg == FPI)
3545 	    tmpreg = 0x1;
3546 	  else if (opP->reg == FPS)
3547 	    tmpreg = 0x2;
3548 	  else if (opP->reg == FPC)
3549 	    tmpreg = 0x4;
3550 	  else
3551 	    abort ();
3552 	  install_operand (s[1], tmpreg);
3553 	  break;
3554 
3555 	case 'S':		/* Ignore it.  */
3556 	  break;
3557 
3558 	case 'T':
3559 	  install_operand (s[1], get_num (&opP->disp, 30));
3560 	  break;
3561 
3562 	case 'U':		/* Ignore it.  */
3563 	  break;
3564 
3565 	case 'c':
3566 	  switch (opP->reg)
3567 	    {
3568 	    case NC:
3569 	      tmpreg = 0;
3570 	      break;
3571 	    case DC:
3572 	      tmpreg = 1;
3573 	      break;
3574 	    case IC:
3575 	      tmpreg = 2;
3576 	      break;
3577 	    case BC:
3578 	      tmpreg = 3;
3579 	      break;
3580 	    default:
3581 	      as_fatal (_("failed sanity check"));
3582 	    }			/* switch on cache token.  */
3583 	  install_operand (s[1], tmpreg);
3584 	  break;
3585 #ifndef NO_68851
3586 	  /* JF: These are out of order, I fear.  */
3587 	case 'f':
3588 	  switch (opP->reg)
3589 	    {
3590 	    case SFC:
3591 	      tmpreg = 0;
3592 	      break;
3593 	    case DFC:
3594 	      tmpreg = 1;
3595 	      break;
3596 	    default:
3597 	      abort ();
3598 	    }
3599 	  install_operand (s[1], tmpreg);
3600 	  break;
3601 
3602 	case '0':
3603 	case '1':
3604 	case '2':
3605 	  switch (opP->reg)
3606 	    {
3607 	    case TC:
3608 	      tmpreg = 0;
3609 	      break;
3610 	    case CAL:
3611 	      tmpreg = 4;
3612 	      break;
3613 	    case VAL:
3614 	      tmpreg = 5;
3615 	      break;
3616 	    case SCC:
3617 	      tmpreg = 6;
3618 	      break;
3619 	    case AC:
3620 	      tmpreg = 7;
3621 	      break;
3622 	    default:
3623 	      abort ();
3624 	    }
3625 	  install_operand (s[1], tmpreg);
3626 	  break;
3627 
3628 	case 'V':
3629 	  if (opP->reg == VAL)
3630 	    break;
3631 	  abort ();
3632 
3633 	case 'W':
3634 	  switch (opP->reg)
3635 	    {
3636 	    case DRP:
3637 	      tmpreg = 1;
3638 	      break;
3639 	    case SRP:
3640 	      tmpreg = 2;
3641 	      break;
3642 	    case CRP:
3643 	      tmpreg = 3;
3644 	      break;
3645 	    default:
3646 	      abort ();
3647 	    }
3648 	  install_operand (s[1], tmpreg);
3649 	  break;
3650 
3651 	case 'X':
3652 	  switch (opP->reg)
3653 	    {
3654 	    case BAD:
3655 	    case BAD + 1:
3656 	    case BAD + 2:
3657 	    case BAD + 3:
3658 	    case BAD + 4:
3659 	    case BAD + 5:
3660 	    case BAD + 6:
3661 	    case BAD + 7:
3662 	      tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3663 	      break;
3664 
3665 	    case BAC:
3666 	    case BAC + 1:
3667 	    case BAC + 2:
3668 	    case BAC + 3:
3669 	    case BAC + 4:
3670 	    case BAC + 5:
3671 	    case BAC + 6:
3672 	    case BAC + 7:
3673 	      tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3674 	      break;
3675 
3676 	    default:
3677 	      abort ();
3678 	    }
3679 	  install_operand (s[1], tmpreg);
3680 	  break;
3681 	case 'Y':
3682 	  know (opP->reg == PSR);
3683 	  break;
3684 	case 'Z':
3685 	  know (opP->reg == PCSR);
3686 	  break;
3687 #endif /* m68851 */
3688 	case '3':
3689 	  switch (opP->reg)
3690 	    {
3691 	    case TT0:
3692 	      tmpreg = 2;
3693 	      break;
3694 	    case TT1:
3695 	      tmpreg = 3;
3696 	      break;
3697 	    default:
3698 	      abort ();
3699 	    }
3700 	  install_operand (s[1], tmpreg);
3701 	  break;
3702 	case 't':
3703 	  tmpreg = get_num (&opP->disp, 20);
3704 	  install_operand (s[1], tmpreg);
3705 	  break;
3706 	case '_':	/* used only for move16 absolute 32-bit address.  */
3707 	  if (isvar (&opP->disp))
3708 	    add_fix ('l', &opP->disp, 0, 0);
3709 	  tmpreg = get_num (&opP->disp, 90);
3710 	  addword (tmpreg >> 16);
3711 	  addword (tmpreg & 0xFFFF);
3712 	  break;
3713 	case 'u':
3714 	  install_operand (s[1], opP->reg - DATA0L);
3715 	  opP->reg -= (DATA0L);
3716 	  opP->reg &= 0x0F;	/* remove upper/lower bit.  */
3717 	  break;
3718 	case 'x':
3719 	  tmpreg = get_num (&opP->disp, 80);
3720 	  if (tmpreg == -1)
3721 	    tmpreg = 0;
3722 	  install_operand (s[1], tmpreg);
3723 	  break;
3724 	case 'j':
3725 	  tmpreg = get_num (&opP->disp, 10);
3726 	  install_operand (s[1], tmpreg - 1);
3727 	  break;
3728 	case 'K':
3729 	  tmpreg = get_num (&opP->disp, 65);
3730 	  install_operand (s[1], tmpreg);
3731 	  break;
3732 	default:
3733 	  abort ();
3734 	}
3735     }
3736 
3737   /* By the time whe get here (FINALLY) the_ins contains the complete
3738      instruction, ready to be emitted. . .  */
3739 }
3740 
3741 static int
reverse_16_bits(int in)3742 reverse_16_bits (int in)
3743 {
3744   int out = 0;
3745   int n;
3746 
3747   static int mask[16] =
3748   {
3749     0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3750     0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3751   };
3752   for (n = 0; n < 16; n++)
3753     {
3754       if (in & mask[n])
3755 	out |= mask[15 - n];
3756     }
3757   return out;
3758 }				/* reverse_16_bits() */
3759 
3760 static int
reverse_8_bits(int in)3761 reverse_8_bits (int in)
3762 {
3763   int out = 0;
3764   int n;
3765 
3766   static int mask[8] =
3767   {
3768     0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3769   };
3770 
3771   for (n = 0; n < 8; n++)
3772     {
3773       if (in & mask[n])
3774 	out |= mask[7 - n];
3775     }
3776   return out;
3777 }				/* reverse_8_bits() */
3778 
3779 /* Cause an extra frag to be generated here, inserting up to
3780    FRAG_VAR_SIZE bytes.  TYPE is the subtype of the frag to be
3781    generated; its primary type is rs_machine_dependent.
3782 
3783    The TYPE parameter is also used by md_convert_frag_1 and
3784    md_estimate_size_before_relax.  The appropriate type of fixup will
3785    be emitted by md_convert_frag_1.
3786 
3787    ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET.  */
3788 static void
install_operand(int mode,int val)3789 install_operand (int mode, int val)
3790 {
3791   switch (mode)
3792     {
3793     case 's':
3794       the_ins.opcode[0] |= val & 0xFF;	/* JF FF is for M kludge.  */
3795       break;
3796     case 'd':
3797       the_ins.opcode[0] |= val << 9;
3798       break;
3799     case 'E':
3800       the_ins.opcode[1] |= val << 9;
3801       break;
3802     case '1':
3803       the_ins.opcode[1] |= val << 12;
3804       break;
3805     case '2':
3806       the_ins.opcode[1] |= val << 6;
3807       break;
3808     case '3':
3809       the_ins.opcode[1] |= val;
3810       break;
3811     case '4':
3812       the_ins.opcode[2] |= val << 12;
3813       break;
3814     case '5':
3815       the_ins.opcode[2] |= val << 6;
3816       break;
3817     case '6':
3818       /* DANGER!  This is a hack to force cas2l and cas2w cmds to be
3819 	 three words long! */
3820       the_ins.numo++;
3821       the_ins.opcode[2] |= val;
3822       break;
3823     case '7':
3824       the_ins.opcode[1] |= val << 7;
3825       break;
3826     case '8':
3827       the_ins.opcode[1] |= val << 10;
3828       break;
3829 #ifndef NO_68851
3830     case '9':
3831       the_ins.opcode[1] |= val << 5;
3832       break;
3833 #endif
3834 
3835     case 't':
3836       the_ins.opcode[1] |= (val << 10) | (val << 7);
3837       break;
3838     case 'D':
3839       the_ins.opcode[1] |= (val << 12) | val;
3840       break;
3841     case 'g':
3842       the_ins.opcode[0] |= val = 0xff;
3843       break;
3844     case 'i':
3845       the_ins.opcode[0] |= val << 9;
3846       break;
3847     case 'C':
3848       the_ins.opcode[1] |= val;
3849       break;
3850     case 'j':
3851       the_ins.opcode[1] |= val;
3852       the_ins.numo++;		/* What a hack.  */
3853       break;
3854     case 'k':
3855       the_ins.opcode[1] |= val << 4;
3856       break;
3857     case 'b':
3858     case 'w':
3859     case 'W':
3860     case 'l':
3861       break;
3862     case 'e':
3863       the_ins.opcode[0] |= (val << 6);
3864       break;
3865     case 'L':
3866       the_ins.opcode[1] = (val >> 16);
3867       the_ins.opcode[2] = val & 0xffff;
3868       break;
3869     case 'm':
3870       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3871       the_ins.opcode[0] |= ((val & 0x7) << 9);
3872       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3873       break;
3874     case 'n': /* MAC/EMAC Rx on !load.  */
3875       the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3876       the_ins.opcode[0] |= ((val & 0x7) << 9);
3877       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3878       break;
3879     case 'o': /* MAC/EMAC Rx on load.  */
3880       the_ins.opcode[1] |= val << 12;
3881       the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3882       break;
3883     case 'M': /* MAC/EMAC Ry on !load.  */
3884       the_ins.opcode[0] |= (val & 0xF);
3885       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3886       break;
3887     case 'N': /* MAC/EMAC Ry on load.  */
3888       the_ins.opcode[1] |= (val & 0xF);
3889       the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3890       break;
3891     case 'h':
3892       the_ins.opcode[1] |= ((val != 1) << 10);
3893       break;
3894     case 'F':
3895       the_ins.opcode[0] |= ((val & 0x3) << 9);
3896       break;
3897     case 'f':
3898       the_ins.opcode[0] |= ((val & 0x3) << 0);
3899       break;
3900     case 'G':  /* EMAC accumulator in a EMAC load instruction.  */
3901       the_ins.opcode[0] |= ((~val & 0x1) << 7);
3902       the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3903       break;
3904     case 'H':  /* EMAC accumulator in a EMAC non-load instruction.  */
3905       the_ins.opcode[0] |= ((val & 0x1) << 7);
3906       the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3907       break;
3908     case 'I':
3909       the_ins.opcode[1] |= ((val & 0x3) << 9);
3910       break;
3911     case ']':
3912       the_ins.opcode[0] |= (val & 0x1) <<10;
3913       break;
3914     case 'c':
3915     default:
3916       as_fatal (_("failed sanity check."));
3917     }
3918 }
3919 
3920 static void
install_gen_operand(int mode,int val)3921 install_gen_operand (int mode, int val)
3922 {
3923   switch (mode)
3924     {
3925     case '/':  /* Special for mask loads for mac/msac insns with
3926 		  possible mask; trailing_ampersend set in bit 8.  */
3927       the_ins.opcode[0] |= (val & 0x3f);
3928       the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3929       break;
3930     case 's':
3931       the_ins.opcode[0] |= val;
3932       break;
3933     case 'd':
3934       /* This is a kludge!!! */
3935       the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3936       break;
3937     case 'b':
3938     case 'w':
3939     case 'l':
3940     case 'f':
3941     case 'F':
3942     case 'x':
3943     case 'p':
3944       the_ins.opcode[0] |= val;
3945       break;
3946       /* more stuff goes here.  */
3947     default:
3948       as_fatal (_("failed sanity check."));
3949     }
3950 }
3951 
3952 /* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3953    then deal with the bitfield hack.  */
3954 
3955 static char *
crack_operand(char * str,struct m68k_op * opP)3956 crack_operand (char *str, struct m68k_op *opP)
3957 {
3958   int parens;
3959   int c;
3960   char *beg_str;
3961   int inquote = 0;
3962 
3963   if (!str)
3964     {
3965       return str;
3966     }
3967   beg_str = str;
3968   for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3969     {
3970       if (! inquote)
3971 	{
3972 	  if (*str == '(')
3973 	    parens++;
3974 	  else if (*str == ')')
3975 	    {
3976 	      if (!parens)
3977 		{			/* ERROR.  */
3978 		  opP->error = _("Extra )");
3979 		  return str;
3980 		}
3981 	      --parens;
3982 	    }
3983 	}
3984       if (flag_mri && *str == '\'')
3985 	inquote = ! inquote;
3986     }
3987   if (!*str && parens)
3988     {				/* ERROR.  */
3989       opP->error = _("Missing )");
3990       return str;
3991     }
3992   c = *str;
3993   *str = '\0';
3994   if (m68k_ip_op (beg_str, opP) != 0)
3995     {
3996       *str = c;
3997       return str;
3998     }
3999   *str = c;
4000   if (c == '}')
4001     c = *++str;			/* JF bitfield hack.  */
4002   if (c)
4003     {
4004       c = *++str;
4005       if (!c)
4006 	as_bad (_("Missing operand"));
4007     }
4008 
4009   /* Detect MRI REG symbols and convert them to REGLSTs.  */
4010   if (opP->mode == CONTROL && (int)opP->reg < 0)
4011     {
4012       opP->mode = REGLST;
4013       opP->mask = ~(int)opP->reg;
4014       opP->reg = 0;
4015     }
4016 
4017   return str;
4018 }
4019 
4020 /* This is the guts of the machine-dependent assembler.  STR points to a
4021    machine dependent instruction.  This function is supposed to emit
4022    the frags/bytes it assembles to.
4023    */
4024 
4025 static void
insert_reg(const char * regname,int regnum)4026 insert_reg (const char *regname, int regnum)
4027 {
4028   char buf[100];
4029   int i;
4030 
4031 #ifdef REGISTER_PREFIX
4032   if (!flag_reg_prefix_optional)
4033     {
4034       buf[0] = REGISTER_PREFIX;
4035       strcpy (buf + 1, regname);
4036       regname = buf;
4037     }
4038 #endif
4039 
4040   symbol_table_insert (symbol_new (regname, reg_section, regnum,
4041 				   &zero_address_frag));
4042 
4043   for (i = 0; regname[i]; i++)
4044     buf[i] = TOUPPER (regname[i]);
4045   buf[i] = '\0';
4046 
4047   symbol_table_insert (symbol_new (buf, reg_section, regnum,
4048 				   &zero_address_frag));
4049 }
4050 
4051 struct init_entry
4052   {
4053     const char *name;
4054     int number;
4055   };
4056 
4057 static const struct init_entry init_table[] =
4058 {
4059   { "d0", DATA0 },
4060   { "d1", DATA1 },
4061   { "d2", DATA2 },
4062   { "d3", DATA3 },
4063   { "d4", DATA4 },
4064   { "d5", DATA5 },
4065   { "d6", DATA6 },
4066   { "d7", DATA7 },
4067   { "a0", ADDR0 },
4068   { "a1", ADDR1 },
4069   { "a2", ADDR2 },
4070   { "a3", ADDR3 },
4071   { "a4", ADDR4 },
4072   { "a5", ADDR5 },
4073   { "a6", ADDR6 },
4074   { "fp", ADDR6 },
4075   { "a7", ADDR7 },
4076   { "sp", ADDR7 },
4077   { "ssp", ADDR7 },
4078   { "fp0", FP0 },
4079   { "fp1", FP1 },
4080   { "fp2", FP2 },
4081   { "fp3", FP3 },
4082   { "fp4", FP4 },
4083   { "fp5", FP5 },
4084   { "fp6", FP6 },
4085   { "fp7", FP7 },
4086   { "fpi", FPI },
4087   { "fpiar", FPI },
4088   { "fpc", FPI },
4089   { "fps", FPS },
4090   { "fpsr", FPS },
4091   { "fpc", FPC },
4092   { "fpcr", FPC },
4093   { "control", FPC },
4094   { "status", FPS },
4095   { "iaddr", FPI },
4096 
4097   { "cop0", COP0 },
4098   { "cop1", COP1 },
4099   { "cop2", COP2 },
4100   { "cop3", COP3 },
4101   { "cop4", COP4 },
4102   { "cop5", COP5 },
4103   { "cop6", COP6 },
4104   { "cop7", COP7 },
4105   { "pc", PC },
4106   { "zpc", ZPC },
4107   { "sr", SR },
4108 
4109   { "ccr", CCR },
4110   { "cc", CCR },
4111 
4112   { "acc", ACC },
4113   { "acc0", ACC },
4114   { "acc1", ACC1 },
4115   { "acc2", ACC2 },
4116   { "acc3", ACC3 },
4117   { "accext01", ACCEXT01 },
4118   { "accext23", ACCEXT23 },
4119   { "macsr", MACSR },
4120   { "mask", MASK },
4121 
4122   /* Control registers.  */
4123   { "sfc", SFC },		/* Source Function Code.  */
4124   { "sfcr", SFC },
4125   { "dfc", DFC },		/* Destination Function Code.  */
4126   { "dfcr", DFC },
4127   { "cacr", CACR },		/* Cache Control Register.  */
4128   { "caar", CAAR },		/* Cache Address Register.  */
4129   { "cpucr", CPUCR },		/* CPU Control Register.  */
4130 
4131   { "usp", USP },		/* User Stack Pointer.  */
4132   { "vbr", VBR },		/* Vector Base Register.  */
4133   { "msp", MSP },		/* Master Stack Pointer.  */
4134   { "isp", ISP },		/* Interrupt Stack Pointer.  */
4135 
4136   { "itt0", ITT0 },		/* Instruction Transparent Translation Reg 0.  */
4137   { "itt1", ITT1 },		/* Instruction Transparent Translation Reg 1.  */
4138   { "dtt0", DTT0 },		/* Data Transparent Translation Register 0.  */
4139   { "dtt1", DTT1 },		/* Data Transparent Translation Register 1.  */
4140 
4141   /* 68ec040 versions of same */
4142   { "iacr0", ITT0 },		/* Instruction Access Control Register 0.  */
4143   { "iacr1", ITT1 },		/* Instruction Access Control Register 0.  */
4144   { "dacr0", DTT0 },		/* Data Access Control Register 0.  */
4145   { "dacr1", DTT1 },		/* Data Access Control Register 0.  */
4146 
4147   /* Coldfire versions of same.  The ColdFire programmer's reference
4148      manual indicated that the order is 2,3,0,1, but Ken Rose
4149      <rose@netcom.com> says that 0,1,2,3 is the correct order.  */
4150   { "acr0", ACR0 },		/* Access Control Unit 0.  */
4151   { "acr1", ACR1 },		/* Access Control Unit 1.  */
4152   { "acr2", ACR2 },		/* Access Control Unit 2.  */
4153   { "acr3", ACR3 },		/* Access Control Unit 3.  */
4154   { "acr4", ACR4 },		/* Access Control Unit 4.  */
4155   { "acr5", ACR5 },		/* Access Control Unit 5.  */
4156   { "acr6", ACR6 },		/* Access Control Unit 6.  */
4157   { "acr7", ACR7 },		/* Access Control Unit 7.  */
4158 
4159   { "tc", TC },			/* MMU Translation Control Register.  */
4160   { "tcr", TC },
4161   { "asid", ASID },
4162 
4163   { "mmusr", MMUSR },		/* MMU Status Register.  */
4164   { "srp", SRP },		/* User Root Pointer.  */
4165   { "urp", URP },		/* Supervisor Root Pointer.  */
4166 
4167   { "buscr", BUSCR },
4168   { "mmubar", MMUBAR },
4169   { "pcr", PCR },
4170 
4171   { "rombar", ROMBAR },		/* ROM Base Address Register.  */
4172   { "rambar0", RAMBAR0 },	/* ROM Base Address Register.  */
4173   { "rambar1", RAMBAR1 },	/* ROM Base Address Register.  */
4174   { "mbar", MBAR },		/* Module Base Address Register.  */
4175 
4176   { "mbar0",    MBAR0 },	/* mcfv4e registers.  */
4177   { "mbar1",    MBAR1 },	/* mcfv4e registers.  */
4178   { "rombar0",  ROMBAR0 },	/* mcfv4e registers.  */
4179   { "rombar1",  ROMBAR1 },	/* mcfv4e registers.  */
4180   { "mpcr",     MPCR },		/* mcfv4e registers.  */
4181   { "edrambar", EDRAMBAR },	/* mcfv4e registers.  */
4182   { "secmbar",  SECMBAR },	/* mcfv4e registers.  */
4183   { "asid",     TC },		/* mcfv4e registers.  */
4184   { "mmubar",   BUSCR },	/* mcfv4e registers.  */
4185   { "pcr1u0",   PCR1U0 },	/* mcfv4e registers.  */
4186   { "pcr1l0",   PCR1L0 },	/* mcfv4e registers.  */
4187   { "pcr2u0",   PCR2U0 },	/* mcfv4e registers.  */
4188   { "pcr2l0",   PCR2L0 },	/* mcfv4e registers.  */
4189   { "pcr3u0",   PCR3U0 },	/* mcfv4e registers.  */
4190   { "pcr3l0",   PCR3L0 },	/* mcfv4e registers.  */
4191   { "pcr1u1",   PCR1U1 },	/* mcfv4e registers.  */
4192   { "pcr1l1",   PCR1L1 },	/* mcfv4e registers.  */
4193   { "pcr2u1",   PCR2U1 },	/* mcfv4e registers.  */
4194   { "pcr2l1",   PCR2L1 },	/* mcfv4e registers.  */
4195   { "pcr3u1",   PCR3U1 },	/* mcfv4e registers.  */
4196   { "pcr3l1",   PCR3L1 },	/* mcfv4e registers.  */
4197 
4198   { "flashbar", FLASHBAR }, 	/* mcf528x registers.  */
4199   { "rambar",   RAMBAR },  	/* mcf528x registers.  */
4200 
4201   { "mbar2",    MBAR2 },  	/* mcf5249 registers.  */
4202 
4203   { "rgpiobar",	RGPIOBAR },	/* mcf54418 registers.  */
4204 
4205   { "cac",    CAC },  		/* fido registers.  */
4206   { "mbb",    MBO },  		/* fido registers (obsolete).  */
4207   { "mbo",    MBO },  		/* fido registers.  */
4208   /* End of control registers.  */
4209 
4210   { "ac", AC },
4211   { "bc", BC },
4212   { "cal", CAL },
4213   { "crp", CRP },
4214   { "drp", DRP },
4215   { "pcsr", PCSR },
4216   { "psr", PSR },
4217   { "scc", SCC },
4218   { "val", VAL },
4219   { "bad0", BAD0 },
4220   { "bad1", BAD1 },
4221   { "bad2", BAD2 },
4222   { "bad3", BAD3 },
4223   { "bad4", BAD4 },
4224   { "bad5", BAD5 },
4225   { "bad6", BAD6 },
4226   { "bad7", BAD7 },
4227   { "bac0", BAC0 },
4228   { "bac1", BAC1 },
4229   { "bac2", BAC2 },
4230   { "bac3", BAC3 },
4231   { "bac4", BAC4 },
4232   { "bac5", BAC5 },
4233   { "bac6", BAC6 },
4234   { "bac7", BAC7 },
4235 
4236   { "ic", IC },
4237   { "dc", DC },
4238   { "nc", NC },
4239 
4240   { "tt0", TT0 },
4241   { "tt1", TT1 },
4242   /* 68ec030 versions of same.  */
4243   { "ac0", TT0 },
4244   { "ac1", TT1 },
4245   /* 68ec030 access control unit, identical to 030 MMU status reg.  */
4246   { "acusr", PSR },
4247 
4248   /* Suppressed data and address registers.  */
4249   { "zd0", ZDATA0 },
4250   { "zd1", ZDATA1 },
4251   { "zd2", ZDATA2 },
4252   { "zd3", ZDATA3 },
4253   { "zd4", ZDATA4 },
4254   { "zd5", ZDATA5 },
4255   { "zd6", ZDATA6 },
4256   { "zd7", ZDATA7 },
4257   { "za0", ZADDR0 },
4258   { "za1", ZADDR1 },
4259   { "za2", ZADDR2 },
4260   { "za3", ZADDR3 },
4261   { "za4", ZADDR4 },
4262   { "za5", ZADDR5 },
4263   { "za6", ZADDR6 },
4264   { "za7", ZADDR7 },
4265 
4266   /* Upper and lower data and address registers, used by macw and msacw.  */
4267   { "d0l", DATA0L },
4268   { "d1l", DATA1L },
4269   { "d2l", DATA2L },
4270   { "d3l", DATA3L },
4271   { "d4l", DATA4L },
4272   { "d5l", DATA5L },
4273   { "d6l", DATA6L },
4274   { "d7l", DATA7L },
4275 
4276   { "a0l", ADDR0L },
4277   { "a1l", ADDR1L },
4278   { "a2l", ADDR2L },
4279   { "a3l", ADDR3L },
4280   { "a4l", ADDR4L },
4281   { "a5l", ADDR5L },
4282   { "a6l", ADDR6L },
4283   { "a7l", ADDR7L },
4284 
4285   { "d0u", DATA0U },
4286   { "d1u", DATA1U },
4287   { "d2u", DATA2U },
4288   { "d3u", DATA3U },
4289   { "d4u", DATA4U },
4290   { "d5u", DATA5U },
4291   { "d6u", DATA6U },
4292   { "d7u", DATA7U },
4293 
4294   { "a0u", ADDR0U },
4295   { "a1u", ADDR1U },
4296   { "a2u", ADDR2U },
4297   { "a3u", ADDR3U },
4298   { "a4u", ADDR4U },
4299   { "a5u", ADDR5U },
4300   { "a6u", ADDR6U },
4301   { "a7u", ADDR7U },
4302 
4303   { 0, 0 }
4304 };
4305 
4306 static void
init_regtable(void)4307 init_regtable (void)
4308 {
4309   int i;
4310   for (i = 0; init_table[i].name; i++)
4311     insert_reg (init_table[i].name, init_table[i].number);
4312 }
4313 
4314 void
md_assemble(char * str)4315 md_assemble (char *str)
4316 {
4317   const char *er;
4318   short *fromP;
4319   char *toP = NULL;
4320   int m, n = 0;
4321   char *to_beg_P;
4322   int shorts_this_frag;
4323   fixS *fixP;
4324 
4325   if (!selected_cpu && !selected_arch)
4326     {
4327       /* We've not selected an architecture yet.  Set the default
4328 	 now.  We do this lazily so that an initial .cpu or .arch directive
4329 	 can specify.  */
4330       if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4331 	as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4332     }
4333   if (!initialized)
4334     m68k_init_arch ();
4335 
4336   /* In MRI mode, the instruction and operands are separated by a
4337      space.  Anything following the operands is a comment.  The label
4338      has already been removed.  */
4339   if (flag_mri)
4340     {
4341       char *s;
4342       int fields = 0;
4343       int infield = 0;
4344       int inquote = 0;
4345 
4346       for (s = str; *s != '\0'; s++)
4347 	{
4348 	  if ((*s == ' ' || *s == '\t') && ! inquote)
4349 	    {
4350 	      if (infield)
4351 		{
4352 		  ++fields;
4353 		  if (fields >= 2)
4354 		    {
4355 		      *s = '\0';
4356 		      break;
4357 		    }
4358 		  infield = 0;
4359 		}
4360 	    }
4361 	  else
4362 	    {
4363 	      if (! infield)
4364 		infield = 1;
4365 	      if (*s == '\'')
4366 		inquote = ! inquote;
4367 	    }
4368 	}
4369     }
4370 
4371   memset (&the_ins, '\0', sizeof (the_ins));
4372   m68k_ip (str);
4373   er = the_ins.error;
4374   if (!er)
4375     {
4376       for (n = 0; n < the_ins.numargs; n++)
4377 	if (the_ins.operands[n].error)
4378 	  {
4379 	    er = the_ins.operands[n].error;
4380 	    break;
4381 	  }
4382     }
4383   if (er)
4384     {
4385       as_bad (_("%s -- statement `%s' ignored"), er, str);
4386       return;
4387     }
4388 
4389   /* If there is a current label, record that it marks an instruction.  */
4390   if (current_label != NULL)
4391     {
4392       current_label->text = 1;
4393       current_label = NULL;
4394     }
4395 
4396 #ifdef OBJ_ELF
4397   /* Tie dwarf2 debug info to the address at the start of the insn.  */
4398   dwarf2_emit_insn (0);
4399 #endif
4400 
4401   if (the_ins.nfrag == 0)
4402     {
4403       /* No frag hacking involved; just put it out.  */
4404       toP = frag_more (2 * the_ins.numo);
4405       fromP = &the_ins.opcode[0];
4406       for (m = the_ins.numo; m; --m)
4407 	{
4408 	  md_number_to_chars (toP, (long) (*fromP), 2);
4409 	  toP += 2;
4410 	  fromP++;
4411 	}
4412       /* Put out symbol-dependent info.  */
4413       for (m = 0; m < the_ins.nrel; m++)
4414 	{
4415 	  switch (the_ins.reloc[m].wid)
4416 	    {
4417 	    case 'B':
4418 	      n = 1;
4419 	      break;
4420 	    case 'b':
4421 	      n = 1;
4422 	      break;
4423 	    case '3':
4424 	      n = 1;
4425 	      break;
4426 	    case 'w':
4427 	    case 'W':
4428 	      n = 2;
4429 	      break;
4430 	    case 'l':
4431 	      n = 4;
4432 	      break;
4433 	    default:
4434 	      as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4435 			the_ins.reloc[m].wid);
4436 	    }
4437 
4438 	  fixP = fix_new_exp (frag_now,
4439 			      ((toP - frag_now->fr_literal)
4440 			       - the_ins.numo * 2 + the_ins.reloc[m].n),
4441 			      n,
4442 			      &the_ins.reloc[m].exp,
4443 			      the_ins.reloc[m].pcrel,
4444 			      get_reloc_code (n, the_ins.reloc[m].pcrel,
4445 					      the_ins.reloc[m].pic_reloc));
4446 	  fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4447 	  if (the_ins.reloc[m].wid == 'B')
4448 	    fixP->fx_signed = 1;
4449 	}
4450       return;
4451     }
4452 
4453   /* There's some frag hacking.  */
4454   {
4455     /* Calculate the max frag size.  */
4456     int wid;
4457 
4458     wid = 2 * the_ins.fragb[0].fragoff;
4459     for (n = 1; n < the_ins.nfrag; n++)
4460       wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4461     /* frag_var part.  */
4462     wid += FRAG_VAR_SIZE;
4463     /* Make sure the whole insn fits in one chunk, in particular that
4464        the var part is attached, as we access one byte before the
4465        variable frag for byte branches.  */
4466     frag_grow (wid);
4467   }
4468 
4469   for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4470     {
4471       int wid;
4472 
4473       if (n == 0)
4474 	wid = 2 * the_ins.fragb[n].fragoff;
4475       else
4476 	wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4477       toP = frag_more (wid);
4478       to_beg_P = toP;
4479       shorts_this_frag = 0;
4480       for (m = wid / 2; m; --m)
4481 	{
4482 	  md_number_to_chars (toP, (long) (*fromP), 2);
4483 	  toP += 2;
4484 	  fromP++;
4485 	  shorts_this_frag++;
4486 	}
4487       for (m = 0; m < the_ins.nrel; m++)
4488 	{
4489 	  if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4490 	    {
4491 	      the_ins.reloc[m].n -= 2 * shorts_this_frag;
4492 	      break;
4493 	    }
4494 	  wid = the_ins.reloc[m].wid;
4495 	  if (wid == 0)
4496 	    continue;
4497 	  the_ins.reloc[m].wid = 0;
4498 	  wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4499 
4500 	  fixP = fix_new_exp (frag_now,
4501 			      ((toP - frag_now->fr_literal)
4502 			       - the_ins.numo * 2 + the_ins.reloc[m].n),
4503 			      wid,
4504 			      &the_ins.reloc[m].exp,
4505 			      the_ins.reloc[m].pcrel,
4506 			      get_reloc_code (wid, the_ins.reloc[m].pcrel,
4507 					      the_ins.reloc[m].pic_reloc));
4508 	  fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4509 	}
4510       (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
4511 		       (relax_substateT) (the_ins.fragb[n].fragty),
4512 		       the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4513     }
4514   gas_assert (the_ins.nfrag >= 1);
4515   n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
4516   shorts_this_frag = 0;
4517   if (n)
4518     {
4519       toP = frag_more (n * 2);
4520       while (n--)
4521 	{
4522 	  md_number_to_chars (toP, (long) (*fromP), 2);
4523 	  toP += 2;
4524 	  fromP++;
4525 	  shorts_this_frag++;
4526 	}
4527     }
4528   for (m = 0; m < the_ins.nrel; m++)
4529     {
4530       int wid;
4531 
4532       wid = the_ins.reloc[m].wid;
4533       if (wid == 0)
4534 	continue;
4535       the_ins.reloc[m].wid = 0;
4536       wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4537 
4538       fixP = fix_new_exp (frag_now,
4539 			  ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4540 			   - shorts_this_frag * 2),
4541 			  wid,
4542 			  &the_ins.reloc[m].exp,
4543 			  the_ins.reloc[m].pcrel,
4544 			  get_reloc_code (wid, the_ins.reloc[m].pcrel,
4545 					  the_ins.reloc[m].pic_reloc));
4546       fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4547     }
4548 }
4549 
4550 /* Comparison function used by qsort to rank the opcode entries by name.  */
4551 
4552 static int
m68k_compare_opcode(const void * v1,const void * v2)4553 m68k_compare_opcode (const void * v1, const void * v2)
4554 {
4555   struct m68k_opcode * op1, * op2;
4556   int ret;
4557 
4558   if (v1 == v2)
4559     return 0;
4560 
4561   op1 = *(struct m68k_opcode **) v1;
4562   op2 = *(struct m68k_opcode **) v2;
4563 
4564   /* Compare the two names.  If different, return the comparison.
4565      If the same, return the order they are in the opcode table.  */
4566   ret = strcmp (op1->name, op2->name);
4567   if (ret)
4568     return ret;
4569   if (op1 < op2)
4570     return -1;
4571   return 1;
4572 }
4573 
4574 void
md_begin(void)4575 md_begin (void)
4576 {
4577   const struct m68k_opcode *ins;
4578   struct m68k_incant *hack, *slak;
4579   const char *retval = 0;	/* Empty string, or error msg text.  */
4580   int i;
4581 
4582   /* Set up hash tables with 68000 instructions.
4583      similar to what the vax assembler does.  */
4584   /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4585      a copy of it at runtime, adding in the information we want but isn't
4586      there.  I think it'd be better to have an awk script hack the table
4587      at compile time.  Or even just xstr the table and use it as-is.  But
4588      my lord ghod hath spoken, so we do it this way.  Excuse the ugly var
4589      names.  */
4590 
4591   if (flag_mri)
4592     {
4593       flag_reg_prefix_optional = 1;
4594       m68k_abspcadd = 1;
4595       if (! m68k_rel32_from_cmdline)
4596 	m68k_rel32 = 0;
4597     }
4598 
4599   /* First sort the opcode table into alphabetical order to seperate
4600      the order that the assembler wants to see the opcodes from the
4601      order that the disassembler wants to see them.  */
4602   m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4603   if (!m68k_sorted_opcodes)
4604     as_fatal (_("Internal Error:  Can't allocate m68k_sorted_opcodes of size %d"),
4605 	      m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
4606 
4607   for (i = m68k_numopcodes; i--;)
4608     m68k_sorted_opcodes[i] = m68k_opcodes + i;
4609 
4610   qsort (m68k_sorted_opcodes, m68k_numopcodes,
4611 	 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4612 
4613   op_hash = hash_new ();
4614 
4615   obstack_begin (&robyn, 4000);
4616   for (i = 0; i < m68k_numopcodes; i++)
4617     {
4618       hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4619       do
4620 	{
4621 	  ins = m68k_sorted_opcodes[i];
4622 
4623 	  /* We must enter all insns into the table, because .arch and
4624 	     .cpu directives can change things.  */
4625 	  slak->m_operands = ins->args;
4626 	  slak->m_arch = ins->arch;
4627 	  slak->m_opcode = ins->opcode;
4628 
4629 	  /* In most cases we can determine the number of opcode words
4630 	     by checking the second word of the mask.  Unfortunately
4631 	     some instructions have 2 opcode words, but no fixed bits
4632 	     in the second word.  A leading dot in the operands
4633 	     string also indicates 2 opcodes.  */
4634 	  if (*slak->m_operands == '.')
4635 	    {
4636 	      slak->m_operands++;
4637 	      slak->m_codenum = 2;
4638 	    }
4639 	  else if (ins->match & 0xffffL)
4640 	    slak->m_codenum = 2;
4641 	  else
4642 	    slak->m_codenum = 1;
4643 	  slak->m_opnum = strlen (slak->m_operands) / 2;
4644 
4645 	  if (i + 1 != m68k_numopcodes
4646 	      && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
4647 	    {
4648 	      slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4649 	      i++;
4650 	    }
4651 	  else
4652 	    slak->m_next = 0;
4653 	  slak = slak->m_next;
4654 	}
4655       while (slak);
4656 
4657       retval = hash_insert (op_hash, ins->name, (char *) hack);
4658       if (retval)
4659 	as_fatal (_("Internal Error:  Can't hash %s: %s"), ins->name, retval);
4660     }
4661 
4662   for (i = 0; i < m68k_numaliases; i++)
4663     {
4664       const char *name = m68k_opcode_aliases[i].primary;
4665       const char *alias = m68k_opcode_aliases[i].alias;
4666       void *val = hash_find (op_hash, name);
4667 
4668       if (!val)
4669 	as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4670       retval = hash_insert (op_hash, alias, val);
4671       if (retval)
4672 	as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4673     }
4674 
4675   /* In MRI mode, all unsized branches are variable sized.  Normally,
4676      they are word sized.  */
4677   if (flag_mri)
4678     {
4679       static struct m68k_opcode_alias mri_aliases[] =
4680 	{
4681 	  { "bhi",	"jhi", },
4682 	  { "bls",	"jls", },
4683 	  { "bcc",	"jcc", },
4684 	  { "bcs",	"jcs", },
4685 	  { "bne",	"jne", },
4686 	  { "beq",	"jeq", },
4687 	  { "bvc",	"jvc", },
4688 	  { "bvs",	"jvs", },
4689 	  { "bpl",	"jpl", },
4690 	  { "bmi",	"jmi", },
4691 	  { "bge",	"jge", },
4692 	  { "blt",	"jlt", },
4693 	  { "bgt",	"jgt", },
4694 	  { "ble",	"jle", },
4695 	  { "bra",	"jra", },
4696 	  { "bsr",	"jbsr", },
4697 	};
4698 
4699       for (i = 0;
4700 	   i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4701 	   i++)
4702 	{
4703 	  const char *name = mri_aliases[i].primary;
4704 	  const char *alias = mri_aliases[i].alias;
4705 	  void *val = hash_find (op_hash, name);
4706 
4707 	  if (!val)
4708 	    as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4709 	  retval = hash_jam (op_hash, alias, val);
4710 	  if (retval)
4711 	    as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4712 	}
4713     }
4714 
4715   for (i = 0; i < (int) sizeof (notend_table); i++)
4716     {
4717       notend_table[i] = 0;
4718       alt_notend_table[i] = 0;
4719     }
4720 
4721   notend_table[','] = 1;
4722   notend_table['{'] = 1;
4723   notend_table['}'] = 1;
4724   alt_notend_table['a'] = 1;
4725   alt_notend_table['A'] = 1;
4726   alt_notend_table['d'] = 1;
4727   alt_notend_table['D'] = 1;
4728   alt_notend_table['#'] = 1;
4729   alt_notend_table['&'] = 1;
4730   alt_notend_table['f'] = 1;
4731   alt_notend_table['F'] = 1;
4732 #ifdef REGISTER_PREFIX
4733   alt_notend_table[REGISTER_PREFIX] = 1;
4734 #endif
4735 
4736   /* We need to put '(' in alt_notend_table to handle
4737        cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)  */
4738   alt_notend_table['('] = 1;
4739 
4740   /* We need to put '@' in alt_notend_table to handle
4741        cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)  */
4742   alt_notend_table['@'] = 1;
4743 
4744   /* We need to put digits in alt_notend_table to handle
4745        bfextu %d0{24:1},%d0  */
4746   alt_notend_table['0'] = 1;
4747   alt_notend_table['1'] = 1;
4748   alt_notend_table['2'] = 1;
4749   alt_notend_table['3'] = 1;
4750   alt_notend_table['4'] = 1;
4751   alt_notend_table['5'] = 1;
4752   alt_notend_table['6'] = 1;
4753   alt_notend_table['7'] = 1;
4754   alt_notend_table['8'] = 1;
4755   alt_notend_table['9'] = 1;
4756 
4757 #ifndef MIT_SYNTAX_ONLY
4758   /* Insert pseudo ops, these have to go into the opcode table since
4759      gas expects pseudo ops to start with a dot.  */
4760   {
4761     int n = 0;
4762 
4763     while (mote_pseudo_table[n].poc_name)
4764       {
4765 	hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
4766 	hash_insert (op_hash,
4767 		     mote_pseudo_table[n].poc_name, (char *) hack);
4768 	hack->m_operands = 0;
4769 	hack->m_opnum = n;
4770 	n++;
4771       }
4772   }
4773 #endif
4774 
4775   init_regtable ();
4776 
4777 #ifdef OBJ_ELF
4778   record_alignment (text_section, 2);
4779   record_alignment (data_section, 2);
4780   record_alignment (bss_section, 2);
4781 #endif
4782 }
4783 
4784 
4785 /* This is called when a label is defined.  */
4786 
4787 void
m68k_frob_label(symbolS * sym)4788 m68k_frob_label (symbolS *sym)
4789 {
4790   struct label_line *n;
4791 
4792   n = (struct label_line *) xmalloc (sizeof *n);
4793   n->next = labels;
4794   n->label = sym;
4795   as_where (&n->file, &n->line);
4796   n->text = 0;
4797   labels = n;
4798   current_label = n;
4799 
4800 #ifdef OBJ_ELF
4801   dwarf2_emit_label (sym);
4802 #endif
4803 }
4804 
4805 /* This is called when a value that is not an instruction is emitted.  */
4806 
4807 void
m68k_flush_pending_output(void)4808 m68k_flush_pending_output (void)
4809 {
4810   current_label = NULL;
4811 }
4812 
4813 /* This is called at the end of the assembly, when the final value of
4814    the label is known.  We warn if this is a text symbol aligned at an
4815    odd location.  */
4816 
4817 void
m68k_frob_symbol(symbolS * sym)4818 m68k_frob_symbol (symbolS *sym)
4819 {
4820   if (S_GET_SEGMENT (sym) == reg_section
4821       && (int) S_GET_VALUE (sym) < 0)
4822     {
4823       S_SET_SEGMENT (sym, absolute_section);
4824       S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4825     }
4826   else if ((S_GET_VALUE (sym) & 1) != 0)
4827     {
4828       struct label_line *l;
4829 
4830       for (l = labels; l != NULL; l = l->next)
4831 	{
4832 	  if (l->label == sym)
4833 	    {
4834 	      if (l->text)
4835 		as_warn_where (l->file, l->line,
4836 			       _("text label `%s' aligned to odd boundary"),
4837 			       S_GET_NAME (sym));
4838 	      break;
4839 	    }
4840 	}
4841     }
4842 }
4843 
4844 /* This is called if we go in or out of MRI mode because of the .mri
4845    pseudo-op.  */
4846 
4847 void
m68k_mri_mode_change(int on)4848 m68k_mri_mode_change (int on)
4849 {
4850   if (on)
4851     {
4852       if (! flag_reg_prefix_optional)
4853 	{
4854 	  flag_reg_prefix_optional = 1;
4855 #ifdef REGISTER_PREFIX
4856 	  init_regtable ();
4857 #endif
4858 	}
4859       m68k_abspcadd = 1;
4860       if (! m68k_rel32_from_cmdline)
4861 	m68k_rel32 = 0;
4862     }
4863   else
4864     {
4865       if (! reg_prefix_optional_seen)
4866 	{
4867 #ifdef REGISTER_PREFIX_OPTIONAL
4868 	  flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4869 #else
4870 	  flag_reg_prefix_optional = 0;
4871 #endif
4872 #ifdef REGISTER_PREFIX
4873 	  init_regtable ();
4874 #endif
4875 	}
4876       m68k_abspcadd = 0;
4877       if (! m68k_rel32_from_cmdline)
4878 	m68k_rel32 = 1;
4879     }
4880 }
4881 
4882 char *
md_atof(int type,char * litP,int * sizeP)4883 md_atof (int type, char *litP, int *sizeP)
4884 {
4885   return ieee_md_atof (type, litP, sizeP, TRUE);
4886 }
4887 
4888 void
md_number_to_chars(char * buf,valueT val,int n)4889 md_number_to_chars (char *buf, valueT val, int n)
4890 {
4891   number_to_chars_bigendian (buf, val, n);
4892 }
4893 
4894 void
md_apply_fix(fixS * fixP,valueT * valP,segT seg ATTRIBUTE_UNUSED)4895 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
4896 {
4897   offsetT val = *valP;
4898   addressT upper_limit;
4899   offsetT lower_limit;
4900 
4901   /* This is unnecessary but it convinces the native rs6000 compiler
4902      to generate the code we want.  */
4903   char *buf = fixP->fx_frag->fr_literal;
4904   buf += fixP->fx_where;
4905   /* End ibm compiler workaround.  */
4906 
4907   val = SEXT (val);
4908 
4909   if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4910     fixP->fx_done = 1;
4911 
4912 #ifdef OBJ_ELF
4913   if (fixP->fx_addsy)
4914     {
4915       memset (buf, 0, fixP->fx_size);
4916       fixP->fx_addnumber = val;	/* Remember value for emit_reloc.  */
4917 
4918       if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4919 	  && !S_IS_DEFINED (fixP->fx_addsy)
4920 	  && !S_IS_WEAK (fixP->fx_addsy))
4921 	S_SET_WEAK (fixP->fx_addsy);
4922 
4923       switch (fixP->fx_r_type)
4924 	{
4925 	case BFD_RELOC_68K_TLS_GD32:
4926 	case BFD_RELOC_68K_TLS_GD16:
4927 	case BFD_RELOC_68K_TLS_GD8:
4928 	case BFD_RELOC_68K_TLS_LDM32:
4929 	case BFD_RELOC_68K_TLS_LDM16:
4930 	case BFD_RELOC_68K_TLS_LDM8:
4931 	case BFD_RELOC_68K_TLS_LDO32:
4932 	case BFD_RELOC_68K_TLS_LDO16:
4933 	case BFD_RELOC_68K_TLS_LDO8:
4934 	case BFD_RELOC_68K_TLS_IE32:
4935 	case BFD_RELOC_68K_TLS_IE16:
4936 	case BFD_RELOC_68K_TLS_IE8:
4937 	case BFD_RELOC_68K_TLS_LE32:
4938 	case BFD_RELOC_68K_TLS_LE16:
4939 	case BFD_RELOC_68K_TLS_LE8:
4940 	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
4941 	  break;
4942 
4943 	default:
4944 	  break;
4945 	}
4946 
4947       return;
4948     }
4949 #elif defined(OBJ_AOUT)
4950   /* PR gas/3041 Do not fix frags referencing a weak symbol.  */
4951   if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4952     {
4953       memset (buf, 0, fixP->fx_size);
4954       fixP->fx_addnumber = val;	/* Remember value for emit_reloc.  */
4955       return;
4956     }
4957 #endif
4958 
4959   if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4960       || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4961     return;
4962 
4963   switch (fixP->fx_size)
4964     {
4965       /* The cast to offsetT below are necessary to make code
4966 	 correct for machines where ints are smaller than offsetT.  */
4967     case 1:
4968       *buf++ = val;
4969       upper_limit = 0x7f;
4970       lower_limit = - (offsetT) 0x80;
4971       break;
4972     case 2:
4973       *buf++ = (val >> 8);
4974       *buf++ = val;
4975       upper_limit = 0x7fff;
4976       lower_limit = - (offsetT) 0x8000;
4977       break;
4978     case 4:
4979       *buf++ = (val >> 24);
4980       *buf++ = (val >> 16);
4981       *buf++ = (val >> 8);
4982       *buf++ = val;
4983       upper_limit = 0x7fffffff;
4984       lower_limit = - (offsetT) 0x7fffffff - 1;	/* Avoid constant overflow.  */
4985       break;
4986     default:
4987       BAD_CASE (fixP->fx_size);
4988     }
4989 
4990   /* Fix up a negative reloc.  */
4991   if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4992     {
4993       fixP->fx_addsy = fixP->fx_subsy;
4994       fixP->fx_subsy = NULL;
4995       fixP->fx_tcbit = 1;
4996     }
4997 
4998   /* For non-pc-relative values, it's conceivable we might get something
4999      like "0xff" for a byte field.  So extend the upper part of the range
5000      to accept such numbers.  We arbitrarily disallow "-0xff" or "0xff+0xff",
5001      so that we can do any range checking at all.  */
5002   if (! fixP->fx_pcrel && ! fixP->fx_signed)
5003     upper_limit = upper_limit * 2 + 1;
5004 
5005   if ((addressT) val > upper_limit
5006       && (val > 0 || val < lower_limit))
5007     as_bad_where (fixP->fx_file, fixP->fx_line,
5008 		  _("value %ld out of range"), (long)val);
5009 
5010   /* A one byte PC-relative reloc means a short branch.  We can't use
5011      a short branch with a value of 0 or -1, because those indicate
5012      different opcodes (branches with longer offsets).  fixup_segment
5013      in write.c may have clobbered fx_pcrel, so we need to examine the
5014      reloc type.  */
5015   if ((fixP->fx_pcrel
5016        || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5017       && fixP->fx_size == 1
5018       && (fixP->fx_addsy == NULL
5019 	  || S_IS_DEFINED (fixP->fx_addsy))
5020       && (val == 0 || val == -1))
5021     as_bad_where (fixP->fx_file, fixP->fx_line,
5022 		  _("invalid byte branch offset"));
5023 }
5024 
5025 /* *fragP has been relaxed to its final size, and now needs to have
5026    the bytes inside it modified to conform to the new size  There is UGLY
5027    MAGIC here. ..
5028    */
5029 static void
md_convert_frag_1(fragS * fragP)5030 md_convert_frag_1 (fragS *fragP)
5031 {
5032   long disp;
5033   fixS *fixP = NULL;
5034 
5035   /* Address in object code of the displacement.  */
5036   int object_address = fragP->fr_fix + fragP->fr_address;
5037 
5038   /* Address in gas core of the place to store the displacement.  */
5039   /* This convinces the native rs6000 compiler to generate the code we
5040      want.  */
5041   char *buffer_address = fragP->fr_literal;
5042   buffer_address += fragP->fr_fix;
5043   /* End ibm compiler workaround.  */
5044 
5045   /* The displacement of the address, from current location.  */
5046   disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
5047   disp = (disp + fragP->fr_offset) - object_address;
5048 
5049   switch (fragP->fr_subtype)
5050     {
5051     case TAB (BRANCHBWL, BYTE):
5052     case TAB (BRABSJUNC, BYTE):
5053     case TAB (BRABSJCOND, BYTE):
5054     case TAB (BRANCHBW, BYTE):
5055     case TAB (BRANCHBWPL, BYTE):
5056       know (issbyte (disp));
5057       if (disp == 0)
5058 	as_bad_where (fragP->fr_file, fragP->fr_line,
5059 		      _("short branch with zero offset: use :w"));
5060       fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5061 		      fragP->fr_offset, 1, RELAX_RELOC_PC8);
5062       fixP->fx_pcrel_adjust = -1;
5063       break;
5064     case TAB (BRANCHBWL, SHORT):
5065     case TAB (BRABSJUNC, SHORT):
5066     case TAB (BRABSJCOND, SHORT):
5067     case TAB (BRANCHBW, SHORT):
5068     case TAB (BRANCHBWPL, SHORT):
5069       fragP->fr_opcode[1] = 0x00;
5070       fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5071 		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5072       fragP->fr_fix += 2;
5073       break;
5074     case TAB (BRANCHBWL, LONG):
5075       fragP->fr_opcode[1] = (char) 0xFF;
5076       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5077 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5078       fragP->fr_fix += 4;
5079       break;
5080     case TAB (BRANCHBWPL, LONG):
5081       /* Here we are converting an unconditional branch into a pair of
5082 	 conditional branches, in order to get the range.  */
5083       fragP->fr_opcode[0] = 0x66; /* bne */
5084       fragP->fr_opcode[1] = 0xFF;
5085       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5086 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5087       fixP->fx_file = fragP->fr_file;
5088       fixP->fx_line = fragP->fr_line;
5089       fragP->fr_fix += 4;  /* Skip first offset */
5090       buffer_address += 4;
5091       *buffer_address++ = 0x67; /* beq */
5092       *buffer_address++ = 0xff;
5093       fragP->fr_fix += 2;  /* Skip second branch opcode */
5094       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5095 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5096       fragP->fr_fix += 4;
5097       break;
5098     case TAB (BRABSJUNC, LONG):
5099       if (fragP->fr_opcode[0] == 0x61)		/* jbsr */
5100 	{
5101 	  if (flag_keep_pcrel)
5102     	    as_bad_where (fragP->fr_file, fragP->fr_line,
5103 			  _("Conversion of PC relative BSR to absolute JSR"));
5104 	  fragP->fr_opcode[0] = 0x4E;
5105 	  fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand.  */
5106 	  fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5107 			  fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5108 	  fragP->fr_fix += 4;
5109 	}
5110       else if (fragP->fr_opcode[0] == 0x60)	/* jbra */
5111 	{
5112 	  if (flag_keep_pcrel)
5113 	    as_bad_where (fragP->fr_file, fragP->fr_line,
5114 		      _("Conversion of PC relative branch to absolute jump"));
5115 	  fragP->fr_opcode[0] = 0x4E;
5116 	  fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand.  */
5117 	  fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5118 			  fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5119 	  fragP->fr_fix += 4;
5120 	}
5121       else
5122 	{
5123 	  /* This cannot happen, because jbsr and jbra are the only two
5124 	     unconditional branches.  */
5125 	  abort ();
5126 	}
5127       break;
5128     case TAB (BRABSJCOND, LONG):
5129       if (flag_keep_pcrel)
5130     	as_bad_where (fragP->fr_file, fragP->fr_line,
5131 		  _("Conversion of PC relative conditional branch to absolute jump"));
5132 
5133       /* Only Bcc 68000 instructions can come here
5134 	 Change bcc into b!cc/jmp absl long.  */
5135       fragP->fr_opcode[0] ^= 0x01;	/* Invert bcc.  */
5136       fragP->fr_opcode[1]  = 0x06;	/* Branch offset = 6.  */
5137 
5138       /* JF: these used to be fr_opcode[2,3], but they may be in a
5139 	   different frag, in which case referring to them is a no-no.
5140 	   Only fr_opcode[0,1] are guaranteed to work.  */
5141       *buffer_address++ = 0x4e;	/* put in jmp long (0x4ef9) */
5142       *buffer_address++ = (char) 0xf9;
5143       fragP->fr_fix += 2;	/* Account for jmp instruction.  */
5144       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5145 		      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5146       fragP->fr_fix += 4;
5147       break;
5148     case TAB (FBRANCH, SHORT):
5149       know ((fragP->fr_opcode[1] & 0x40) == 0);
5150       fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5151 		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5152       fragP->fr_fix += 2;
5153       break;
5154     case TAB (FBRANCH, LONG):
5155       fragP->fr_opcode[1] |= 0x40;	/* Turn on LONG bit.  */
5156       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5157 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5158       fragP->fr_fix += 4;
5159       break;
5160     case TAB (DBCCLBR, SHORT):
5161     case TAB (DBCCABSJ, SHORT):
5162       fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5163 		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5164       fragP->fr_fix += 2;
5165       break;
5166     case TAB (DBCCLBR, LONG):
5167       /* Only DBcc instructions can come here.
5168 	 Change dbcc into dbcc/bral.
5169 	 JF: these used to be fr_opcode[2-7], but that's wrong.  */
5170       *buffer_address++ = 0x00;	/* Branch offset = 4.  */
5171       *buffer_address++ = 0x04;
5172       *buffer_address++ = 0x60;	/* Put in bra pc+6.  */
5173       *buffer_address++ = 0x06;
5174       *buffer_address++ = 0x60;     /* Put in bral (0x60ff).  */
5175       *buffer_address++ = (char) 0xff;
5176 
5177       fragP->fr_fix += 6;	/* Account for bra/jmp instructions.  */
5178       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5179 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5180       fragP->fr_fix += 4;
5181       break;
5182     case TAB (DBCCABSJ, LONG):
5183       /* Only DBcc instructions can come here.
5184 	 Change dbcc into dbcc/jmp.
5185 	 JF: these used to be fr_opcode[2-7], but that's wrong.  */
5186       if (flag_keep_pcrel)
5187     	as_bad_where (fragP->fr_file, fragP->fr_line,
5188 		      _("Conversion of PC relative conditional branch to absolute jump"));
5189 
5190       *buffer_address++ = 0x00;		/* Branch offset = 4.  */
5191       *buffer_address++ = 0x04;
5192       *buffer_address++ = 0x60;		/* Put in bra pc + 6.  */
5193       *buffer_address++ = 0x06;
5194       *buffer_address++ = 0x4e;		/* Put in jmp long (0x4ef9).  */
5195       *buffer_address++ = (char) 0xf9;
5196 
5197       fragP->fr_fix += 6;		/* Account for bra/jmp instructions.  */
5198       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5199 		      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5200       fragP->fr_fix += 4;
5201       break;
5202     case TAB (PCREL1632, SHORT):
5203       fragP->fr_opcode[1] &= ~0x3F;
5204       fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
5205       fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5206 		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5207       fragP->fr_fix += 2;
5208       break;
5209     case TAB (PCREL1632, LONG):
5210       /* Already set to mode 7.3; this indicates: PC indirect with
5211 	 suppressed index, 32-bit displacement.  */
5212       *buffer_address++ = 0x01;
5213       *buffer_address++ = 0x70;
5214       fragP->fr_fix += 2;
5215       fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5216 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5217       fixP->fx_pcrel_adjust = 2;
5218       fragP->fr_fix += 4;
5219       break;
5220     case TAB (PCINDEX, BYTE):
5221       gas_assert (fragP->fr_fix >= 2);
5222       buffer_address[-2] &= ~1;
5223       fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5224 		      fragP->fr_offset, 1, RELAX_RELOC_PC8);
5225       fixP->fx_pcrel_adjust = 1;
5226       break;
5227     case TAB (PCINDEX, SHORT):
5228       gas_assert (fragP->fr_fix >= 2);
5229       buffer_address[-2] |= 0x1;
5230       buffer_address[-1] = 0x20;
5231       fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5232 		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5233       fixP->fx_pcrel_adjust = 2;
5234       fragP->fr_fix += 2;
5235       break;
5236     case TAB (PCINDEX, LONG):
5237       gas_assert (fragP->fr_fix >= 2);
5238       buffer_address[-2] |= 0x1;
5239       buffer_address[-1] = 0x30;
5240       fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5241 		      fragP->fr_offset, 1, RELAX_RELOC_PC32);
5242       fixP->fx_pcrel_adjust = 2;
5243       fragP->fr_fix += 4;
5244       break;
5245     case TAB (ABSTOPCREL, SHORT):
5246       fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5247 		      fragP->fr_offset, 1, RELAX_RELOC_PC16);
5248       fragP->fr_fix += 2;
5249       break;
5250     case TAB (ABSTOPCREL, LONG):
5251       if (flag_keep_pcrel)
5252 	as_bad_where (fragP->fr_file, fragP->fr_line,
5253 		      _("Conversion of PC relative displacement to absolute"));
5254       /* The thing to do here is force it to ABSOLUTE LONG, since
5255 	 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway.  */
5256       if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5257 	abort ();
5258       fragP->fr_opcode[1] &= ~0x3F;
5259       fragP->fr_opcode[1] |= 0x39;	/* Mode 7.1 */
5260       fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5261 		      fragP->fr_offset, 0, RELAX_RELOC_ABS32);
5262       fragP->fr_fix += 4;
5263       break;
5264     }
5265   if (fixP)
5266     {
5267       fixP->fx_file = fragP->fr_file;
5268       fixP->fx_line = fragP->fr_line;
5269     }
5270 }
5271 
5272 void
md_convert_frag(bfd * abfd ATTRIBUTE_UNUSED,segT sec ATTRIBUTE_UNUSED,fragS * fragP)5273 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5274 		 segT sec ATTRIBUTE_UNUSED,
5275 		 fragS *fragP)
5276 {
5277   md_convert_frag_1 (fragP);
5278 }
5279 
5280 /* Force truly undefined symbols to their maximum size, and generally set up
5281    the frag list to be relaxed
5282    */
5283 int
md_estimate_size_before_relax(fragS * fragP,segT segment)5284 md_estimate_size_before_relax (fragS *fragP, segT segment)
5285 {
5286   /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT.  */
5287   switch (fragP->fr_subtype)
5288     {
5289     case TAB (BRANCHBWL, SZ_UNDEF):
5290     case TAB (BRANCHBWPL, SZ_UNDEF):
5291     case TAB (BRABSJUNC, SZ_UNDEF):
5292     case TAB (BRABSJCOND, SZ_UNDEF):
5293       {
5294 	if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5295 	    && relaxable_symbol (fragP->fr_symbol))
5296 	  {
5297 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5298 	  }
5299 	else if (flag_short_refs)
5300 	  {
5301 	    /* Symbol is undefined and we want short ref.  */
5302 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5303 	  }
5304 	else
5305 	  {
5306 	    /* Symbol is still undefined.  Make it LONG.  */
5307 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5308 	  }
5309 	break;
5310       }
5311 
5312     case TAB (BRANCHBW, SZ_UNDEF):
5313       {
5314 	if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5315 	    && relaxable_symbol (fragP->fr_symbol))
5316 	  {
5317 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5318 	  }
5319 	else
5320 	  {
5321 	    /* Symbol is undefined and we don't have long branches.  */
5322 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5323 	  }
5324 	break;
5325       }
5326 
5327     case TAB (FBRANCH, SZ_UNDEF):
5328     case TAB (DBCCLBR, SZ_UNDEF):
5329     case TAB (DBCCABSJ, SZ_UNDEF):
5330     case TAB (PCREL1632, SZ_UNDEF):
5331       {
5332 	if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5333 	     && relaxable_symbol (fragP->fr_symbol))
5334 	    || flag_short_refs)
5335 	  {
5336 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5337 	  }
5338 	else
5339 	  {
5340 	    fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
5341 	  }
5342 	break;
5343       }
5344 
5345     case TAB (PCINDEX, SZ_UNDEF):
5346       if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5347 	   && relaxable_symbol (fragP->fr_symbol)))
5348 	{
5349 	  fragP->fr_subtype = TAB (PCINDEX, BYTE);
5350 	}
5351       else
5352 	{
5353 	  fragP->fr_subtype = TAB (PCINDEX, LONG);
5354 	}
5355       break;
5356 
5357     case TAB (ABSTOPCREL, SZ_UNDEF):
5358       {
5359 	if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5360 	     && relaxable_symbol (fragP->fr_symbol)))
5361 	  {
5362 	    fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
5363 	  }
5364 	else
5365 	  {
5366 	    fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
5367 	  }
5368 	break;
5369       }
5370 
5371     default:
5372       break;
5373     }
5374 
5375   /* Now that SZ_UNDEF are taken care of, check others.  */
5376   switch (fragP->fr_subtype)
5377     {
5378     case TAB (BRANCHBWL, BYTE):
5379     case TAB (BRABSJUNC, BYTE):
5380     case TAB (BRABSJCOND, BYTE):
5381     case TAB (BRANCHBW, BYTE):
5382       /* We can't do a short jump to the next instruction, so in that
5383 	 case we force word mode.  If the symbol is at the start of a
5384 	 frag, and it is the next frag with any data in it (usually
5385 	 this is just the next frag, but assembler listings may
5386 	 introduce empty frags), we must use word mode.  */
5387       if (fragP->fr_symbol)
5388 	{
5389 	  fragS *sym_frag;
5390 
5391 	  sym_frag = symbol_get_frag (fragP->fr_symbol);
5392 	  if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
5393 	    {
5394 	      fragS *l;
5395 
5396 	      for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
5397 		if (l->fr_fix != 0)
5398 		  break;
5399 	      if (l == sym_frag)
5400 		fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
5401 	    }
5402 	}
5403       break;
5404     default:
5405       break;
5406     }
5407   return md_relax_table[fragP->fr_subtype].rlx_length;
5408 }
5409 
5410 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5411 /* the bit-field entries in the relocation_info struct plays hell
5412    with the byte-order problems of cross-assembly.  So as a hack,
5413    I added this mach. dependent ri twiddler.  Ugly, but it gets
5414    you there. -KWK  */
5415 /* on m68k: first 4 bytes are normal unsigned long, next three bytes
5416    are symbolnum, most sig. byte first.  Last byte is broken up with
5417    bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5418    nibble as nuthin. (on Sun 3 at least) */
5419 /* Translate the internal relocation information into target-specific
5420    format.  */
5421 #ifdef comment
5422 void
md_ri_to_chars(char * the_bytes,struct reloc_info_generic * ri)5423 md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
5424 {
5425   /* This is easy.  */
5426   md_number_to_chars (the_bytes, ri->r_address, 4);
5427   /* Now the fun stuff.  */
5428   the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
5429   the_bytes[5] = (ri->r_symbolnum >>  8) & 0x0ff;
5430   the_bytes[6] =  ri->r_symbolnum        & 0x0ff;
5431   the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5432 		  | ((ri->r_length << 5) & 0x60)
5433 		  | ((ri->r_extern << 4) & 0x10));
5434 }
5435 
5436 #endif
5437 
5438 #endif /* OBJ_AOUT or OBJ_BOUT */
5439 
5440 #ifndef WORKING_DOT_WORD
5441 int md_short_jump_size = 4;
5442 int md_long_jump_size = 6;
5443 
5444 void
md_create_short_jump(char * ptr,addressT from_addr,addressT to_addr,fragS * frag ATTRIBUTE_UNUSED,symbolS * to_symbol ATTRIBUTE_UNUSED)5445 md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5446 		      fragS *frag ATTRIBUTE_UNUSED,
5447 		      symbolS *to_symbol ATTRIBUTE_UNUSED)
5448 {
5449   valueT offset;
5450 
5451   offset = to_addr - (from_addr + 2);
5452 
5453   md_number_to_chars (ptr, (valueT) 0x6000, 2);
5454   md_number_to_chars (ptr + 2, (valueT) offset, 2);
5455 }
5456 
5457 void
md_create_long_jump(char * ptr,addressT from_addr,addressT to_addr,fragS * frag,symbolS * to_symbol)5458 md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5459 		     fragS *frag, symbolS *to_symbol)
5460 {
5461   valueT offset;
5462 
5463   if (!HAVE_LONG_BRANCH (current_architecture))
5464     {
5465       if (flag_keep_pcrel)
5466     	as_fatal (_("Tried to convert PC relative branch to absolute jump"));
5467       offset = to_addr - S_GET_VALUE (to_symbol);
5468       md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5469       md_number_to_chars (ptr + 2, (valueT) offset, 4);
5470       fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5471 	       0, NO_RELOC);
5472     }
5473   else
5474     {
5475       offset = to_addr - (from_addr + 2);
5476       md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5477       md_number_to_chars (ptr + 2, (valueT) offset, 4);
5478     }
5479 }
5480 
5481 #endif
5482 
5483 /* Different values of OK tell what its OK to return.  Things that
5484    aren't OK are an error (what a shock, no?)
5485 
5486    0:  Everything is OK
5487    10:  Absolute 1:8	   only
5488    20:  Absolute 0:7	   only
5489    30:  absolute 0:15	   only
5490    40:  Absolute 0:31	   only
5491    50:  absolute 0:127	   only
5492    55:  absolute -64:63    only
5493    60:  absolute -128:127  only
5494    65:  absolute 0:511     only
5495    70:  absolute 0:4095	   only
5496    80:  absolute -1, 1:7   only
5497    90:  No bignums.          */
5498 
5499 static int
get_num(struct m68k_exp * exp,int ok)5500 get_num (struct m68k_exp *exp, int ok)
5501 {
5502   if (exp->exp.X_op == O_absent)
5503     {
5504       /* Do the same thing the VAX asm does.  */
5505       op (exp) = O_constant;
5506       adds (exp) = 0;
5507       subs (exp) = 0;
5508       offs (exp) = 0;
5509       if (ok == 10)
5510 	{
5511 	  as_warn (_("expression out of range: defaulting to 1"));
5512 	  offs (exp) = 1;
5513 	}
5514     }
5515   else if (exp->exp.X_op == O_constant)
5516     {
5517       switch (ok)
5518 	{
5519 	case 10:
5520 	  if ((valueT) TRUNC (offs (exp)) - 1 > 7)
5521 	    {
5522 	      as_warn (_("expression out of range: defaulting to 1"));
5523 	      offs (exp) = 1;
5524 	    }
5525 	  break;
5526 	case 20:
5527 	  if ((valueT) TRUNC (offs (exp)) > 7)
5528 	    goto outrange;
5529 	  break;
5530 	case 30:
5531 	  if ((valueT) TRUNC (offs (exp)) > 15)
5532 	    goto outrange;
5533 	  break;
5534 	case 40:
5535 	  if ((valueT) TRUNC (offs (exp)) > 32)
5536 	    goto outrange;
5537 	  break;
5538 	case 50:
5539 	  if ((valueT) TRUNC (offs (exp)) > 127)
5540 	    goto outrange;
5541 	  break;
5542 	case 55:
5543 	  if ((valueT) SEXT (offs (exp)) + 64 > 127)
5544 	    goto outrange;
5545 	  break;
5546 	case 60:
5547 	  if ((valueT) SEXT (offs (exp)) + 128 > 255)
5548 	    goto outrange;
5549 	  break;
5550 	case 65:
5551 	  if ((valueT) TRUNC (offs (exp)) > 511)
5552 	    goto outrange;
5553 	  break;
5554 	case 70:
5555 	  if ((valueT) TRUNC (offs (exp)) > 4095)
5556 	    {
5557 	    outrange:
5558 	      as_warn (_("expression out of range: defaulting to 0"));
5559 	      offs (exp) = 0;
5560 	    }
5561 	  break;
5562 	case 80:
5563 	  if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5564               && (valueT) TRUNC (offs (exp)) - 1 > 6)
5565 	    {
5566 	      as_warn (_("expression out of range: defaulting to 1"));
5567 	      offs (exp) = 1;
5568 	    }
5569 	  break;
5570 	default:
5571 	  break;
5572 	}
5573     }
5574   else if (exp->exp.X_op == O_big)
5575     {
5576       if (offs (exp) <= 0	/* flonum.  */
5577 	  && (ok == 90		/* no bignums */
5578 	      || (ok > 10	/* Small-int ranges including 0 ok.  */
5579 		  /* If we have a flonum zero, a zero integer should
5580 		     do as well (e.g., in moveq).  */
5581 		  && generic_floating_point_number.exponent == 0
5582 		  && generic_floating_point_number.low[0] == 0)))
5583 	{
5584 	  /* HACK! Turn it into a long.  */
5585 	  LITTLENUM_TYPE words[6];
5586 
5587 	  gen_to_words (words, 2, 8L);	/* These numbers are magic!  */
5588 	  op (exp) = O_constant;
5589 	  adds (exp) = 0;
5590 	  subs (exp) = 0;
5591 	  offs (exp) = words[1] | (words[0] << 16);
5592 	}
5593       else if (ok != 0)
5594 	{
5595 	  op (exp) = O_constant;
5596 	  adds (exp) = 0;
5597 	  subs (exp) = 0;
5598 	  offs (exp) = (ok == 10) ? 1 : 0;
5599 	  as_warn (_("Can't deal with expression; defaulting to %ld"),
5600 		   (long) offs (exp));
5601 	}
5602     }
5603   else
5604     {
5605       if (ok >= 10 && ok <= 80)
5606 	{
5607 	  op (exp) = O_constant;
5608 	  adds (exp) = 0;
5609 	  subs (exp) = 0;
5610 	  offs (exp) = (ok == 10) ? 1 : 0;
5611 	  as_warn (_("Can't deal with expression; defaulting to %ld"),
5612 		   (long) offs (exp));
5613 	}
5614     }
5615 
5616   if (exp->size != SIZE_UNSPEC)
5617     {
5618       switch (exp->size)
5619 	{
5620 	case SIZE_UNSPEC:
5621 	case SIZE_LONG:
5622 	  break;
5623 	case SIZE_BYTE:
5624 	  if (!isbyte (offs (exp)))
5625 	    as_warn (_("expression doesn't fit in BYTE"));
5626 	  break;
5627 	case SIZE_WORD:
5628 	  if (!isword (offs (exp)))
5629 	    as_warn (_("expression doesn't fit in WORD"));
5630 	  break;
5631 	}
5632     }
5633 
5634   return offs (exp);
5635 }
5636 
5637 /* These are the back-ends for the various machine dependent pseudo-ops.  */
5638 
5639 static void
s_data1(int ignore ATTRIBUTE_UNUSED)5640 s_data1 (int ignore ATTRIBUTE_UNUSED)
5641 {
5642   subseg_set (data_section, 1);
5643   demand_empty_rest_of_line ();
5644 }
5645 
5646 static void
s_data2(int ignore ATTRIBUTE_UNUSED)5647 s_data2 (int ignore ATTRIBUTE_UNUSED)
5648 {
5649   subseg_set (data_section, 2);
5650   demand_empty_rest_of_line ();
5651 }
5652 
5653 static void
s_bss(int ignore ATTRIBUTE_UNUSED)5654 s_bss (int ignore ATTRIBUTE_UNUSED)
5655 {
5656   /* We don't support putting frags in the BSS segment, we fake it
5657      by marking in_bss, then looking at s_skip for clues.  */
5658 
5659   subseg_set (bss_section, 0);
5660   demand_empty_rest_of_line ();
5661 }
5662 
5663 static void
s_even(int ignore ATTRIBUTE_UNUSED)5664 s_even (int ignore ATTRIBUTE_UNUSED)
5665 {
5666   int temp;
5667   long temp_fill;
5668 
5669   temp = 1;			/* JF should be 2? */
5670   temp_fill = get_absolute_expression ();
5671   if (!need_pass_2)		/* Never make frag if expect extra pass.  */
5672     frag_align (temp, (int) temp_fill, 0);
5673   demand_empty_rest_of_line ();
5674   record_alignment (now_seg, temp);
5675 }
5676 
5677 static void
s_proc(int ignore ATTRIBUTE_UNUSED)5678 s_proc (int ignore ATTRIBUTE_UNUSED)
5679 {
5680   demand_empty_rest_of_line ();
5681 }
5682 
5683 /* Pseudo-ops handled for MRI compatibility.  */
5684 
5685 /* This function returns non-zero if the argument is a conditional
5686    pseudo-op.  This is called when checking whether a pending
5687    alignment is needed.  */
5688 
5689 int
m68k_conditional_pseudoop(pseudo_typeS * pop)5690 m68k_conditional_pseudoop (pseudo_typeS *pop)
5691 {
5692   return (pop->poc_handler == s_mri_if
5693 	  || pop->poc_handler == s_mri_else);
5694 }
5695 
5696 /* Handle an MRI style chip specification.  */
5697 
5698 static void
mri_chip(void)5699 mri_chip (void)
5700 {
5701   char *s;
5702   char c;
5703   int i;
5704 
5705   s = input_line_pointer;
5706   /* We can't use get_symbol_end since the processor names are not proper
5707      symbols.  */
5708   while (is_part_of_name (c = *input_line_pointer++))
5709     ;
5710   *--input_line_pointer = 0;
5711   for (i = 0; m68k_cpus[i].name; i++)
5712     if (strcasecmp (s, m68k_cpus[i].name) == 0)
5713       break;
5714   if (!m68k_cpus[i].name)
5715     {
5716       as_bad (_("%s: unrecognized processor name"), s);
5717       *input_line_pointer = c;
5718       ignore_rest_of_line ();
5719       return;
5720     }
5721   *input_line_pointer = c;
5722 
5723   if (*input_line_pointer == '/')
5724     current_architecture = 0;
5725   else
5726     current_architecture &= m68881 | m68851;
5727   current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
5728   control_regs = m68k_cpus[i].control_regs;
5729 
5730   while (*input_line_pointer == '/')
5731     {
5732       ++input_line_pointer;
5733       s = input_line_pointer;
5734       /* We can't use get_symbol_end since the processor names are not
5735 	 proper symbols.  */
5736       while (is_part_of_name (c = *input_line_pointer++))
5737 	;
5738       *--input_line_pointer = 0;
5739       if (strcmp (s, "68881") == 0)
5740 	current_architecture |= m68881;
5741       else if (strcmp (s, "68851") == 0)
5742 	current_architecture |= m68851;
5743       *input_line_pointer = c;
5744     }
5745 }
5746 
5747 /* The MRI CHIP pseudo-op.  */
5748 
5749 static void
s_chip(int ignore ATTRIBUTE_UNUSED)5750 s_chip (int ignore ATTRIBUTE_UNUSED)
5751 {
5752   char *stop = NULL;
5753   char stopc;
5754 
5755   if (flag_mri)
5756     stop = mri_comment_field (&stopc);
5757   mri_chip ();
5758   if (flag_mri)
5759     mri_comment_end (stop, stopc);
5760   demand_empty_rest_of_line ();
5761 }
5762 
5763 /* The MRI FOPT pseudo-op.  */
5764 
5765 static void
s_fopt(int ignore ATTRIBUTE_UNUSED)5766 s_fopt (int ignore ATTRIBUTE_UNUSED)
5767 {
5768   SKIP_WHITESPACE ();
5769 
5770   if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5771     {
5772       int temp;
5773 
5774       input_line_pointer += 3;
5775       temp = get_absolute_expression ();
5776       if (temp < 0 || temp > 7)
5777 	as_bad (_("bad coprocessor id"));
5778       else
5779 	m68k_float_copnum = COP0 + temp;
5780     }
5781   else
5782     {
5783       as_bad (_("unrecognized fopt option"));
5784       ignore_rest_of_line ();
5785       return;
5786     }
5787 
5788   demand_empty_rest_of_line ();
5789 }
5790 
5791 /* The structure used to handle the MRI OPT pseudo-op.  */
5792 
5793 struct opt_action
5794 {
5795   /* The name of the option.  */
5796   const char *name;
5797 
5798   /* If this is not NULL, just call this function.  The first argument
5799      is the ARG field of this structure, the second argument is
5800      whether the option was negated.  */
5801   void (*pfn) (int arg, int on);
5802 
5803   /* If this is not NULL, and the PFN field is NULL, set the variable
5804      this points to.  Set it to the ARG field if the option was not
5805      negated, and the NOTARG field otherwise.  */
5806   int *pvar;
5807 
5808   /* The value to pass to PFN or to assign to *PVAR.  */
5809   int arg;
5810 
5811   /* The value to assign to *PVAR if the option is negated.  If PFN is
5812      NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5813      the option may not be negated.  */
5814   int notarg;
5815 };
5816 
5817 /* The table used to handle the MRI OPT pseudo-op.  */
5818 
5819 static void skip_to_comma (int, int);
5820 static void opt_nest (int, int);
5821 static void opt_chip (int, int);
5822 static void opt_list (int, int);
5823 static void opt_list_symbols (int, int);
5824 
5825 static const struct opt_action opt_table[] =
5826 {
5827   { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5828 
5829   /* We do relaxing, so there is little use for these options.  */
5830   { "b", 0, 0, 0, 0 },
5831   { "brs", 0, 0, 0, 0 },
5832   { "brb", 0, 0, 0, 0 },
5833   { "brl", 0, 0, 0, 0 },
5834   { "brw", 0, 0, 0, 0 },
5835 
5836   { "c", 0, 0, 0, 0 },
5837   { "cex", 0, 0, 0, 0 },
5838   { "case", 0, &symbols_case_sensitive, 1, 0 },
5839   { "cl", 0, 0, 0, 0 },
5840   { "cre", 0, 0, 0, 0 },
5841   { "d", 0, &flag_keep_locals, 1, 0 },
5842   { "e", 0, 0, 0, 0 },
5843   { "f", 0, &flag_short_refs, 1, 0 },
5844   { "frs", 0, &flag_short_refs, 1, 0 },
5845   { "frl", 0, &flag_short_refs, 0, 1 },
5846   { "g", 0, 0, 0, 0 },
5847   { "i", 0, 0, 0, 0 },
5848   { "m", 0, 0, 0, 0 },
5849   { "mex", 0, 0, 0, 0 },
5850   { "mc", 0, 0, 0, 0 },
5851   { "md", 0, 0, 0, 0 },
5852   { "nest", opt_nest, 0, 0, 0 },
5853   { "next", skip_to_comma, 0, 0, 0 },
5854   { "o", 0, 0, 0, 0 },
5855   { "old", 0, 0, 0, 0 },
5856   { "op", skip_to_comma, 0, 0, 0 },
5857   { "pco", 0, 0, 0, 0 },
5858   { "p", opt_chip, 0, 0, 0 },
5859   { "pcr", 0, 0, 0, 0 },
5860   { "pcs", 0, 0, 0, 0 },
5861   { "r", 0, 0, 0, 0 },
5862   { "quick", 0, &m68k_quick, 1, 0 },
5863   { "rel32", 0, &m68k_rel32, 1, 0 },
5864   { "s", opt_list, 0, 0, 0 },
5865   { "t", opt_list_symbols, 0, 0, 0 },
5866   { "w", 0, &flag_no_warnings, 0, 1 },
5867   { "x", 0, 0, 0, 0 }
5868 };
5869 
5870 #define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
5871 
5872 /* The MRI OPT pseudo-op.  */
5873 
5874 static void
s_opt(int ignore ATTRIBUTE_UNUSED)5875 s_opt (int ignore ATTRIBUTE_UNUSED)
5876 {
5877   do
5878     {
5879       int t;
5880       char *s;
5881       char c;
5882       int i;
5883       const struct opt_action *o;
5884 
5885       SKIP_WHITESPACE ();
5886 
5887       t = 1;
5888       if (*input_line_pointer == '-')
5889 	{
5890 	  ++input_line_pointer;
5891 	  t = 0;
5892 	}
5893       else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5894 	{
5895 	  input_line_pointer += 2;
5896 	  t = 0;
5897 	}
5898 
5899       s = input_line_pointer;
5900       c = get_symbol_end ();
5901 
5902       for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5903 	{
5904 	  if (strcasecmp (s, o->name) == 0)
5905 	    {
5906 	      if (o->pfn)
5907 		{
5908 		  /* Restore input_line_pointer now in case the option
5909 		     takes arguments.  */
5910 		  *input_line_pointer = c;
5911 		  (*o->pfn) (o->arg, t);
5912 		}
5913 	      else if (o->pvar != NULL)
5914 		{
5915 		  if (! t && o->arg == o->notarg)
5916 		    as_bad (_("option `%s' may not be negated"), s);
5917 		  *input_line_pointer = c;
5918 		  *o->pvar = t ? o->arg : o->notarg;
5919 		}
5920 	      else
5921 		*input_line_pointer = c;
5922 	      break;
5923 	    }
5924 	}
5925       if (i >= OPTCOUNT)
5926 	{
5927 	  as_bad (_("option `%s' not recognized"), s);
5928 	  *input_line_pointer = c;
5929 	}
5930     }
5931   while (*input_line_pointer++ == ',');
5932 
5933   /* Move back to terminating character.  */
5934   --input_line_pointer;
5935   demand_empty_rest_of_line ();
5936 }
5937 
5938 /* Skip ahead to a comma.  This is used for OPT options which we do
5939    not support and which take arguments.  */
5940 
5941 static void
skip_to_comma(int arg ATTRIBUTE_UNUSED,int on ATTRIBUTE_UNUSED)5942 skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5943 {
5944   while (*input_line_pointer != ','
5945 	 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5946     ++input_line_pointer;
5947 }
5948 
5949 /* Handle the OPT NEST=depth option.  */
5950 
5951 static void
opt_nest(int arg ATTRIBUTE_UNUSED,int on ATTRIBUTE_UNUSED)5952 opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5953 {
5954   if (*input_line_pointer != '=')
5955     {
5956       as_bad (_("bad format of OPT NEST=depth"));
5957       return;
5958     }
5959 
5960   ++input_line_pointer;
5961   max_macro_nest = get_absolute_expression ();
5962 }
5963 
5964 /* Handle the OPT P=chip option.  */
5965 
5966 static void
opt_chip(int arg ATTRIBUTE_UNUSED,int on ATTRIBUTE_UNUSED)5967 opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
5968 {
5969   if (*input_line_pointer != '=')
5970     {
5971       /* This is just OPT P, which we do not support.  */
5972       return;
5973     }
5974 
5975   ++input_line_pointer;
5976   mri_chip ();
5977 }
5978 
5979 /* Handle the OPT S option.  */
5980 
5981 static void
opt_list(int arg ATTRIBUTE_UNUSED,int on)5982 opt_list (int arg ATTRIBUTE_UNUSED, int on)
5983 {
5984   listing_list (on);
5985 }
5986 
5987 /* Handle the OPT T option.  */
5988 
5989 static void
opt_list_symbols(int arg ATTRIBUTE_UNUSED,int on)5990 opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
5991 {
5992   if (on)
5993     listing |= LISTING_SYMBOLS;
5994   else
5995     listing &= ~LISTING_SYMBOLS;
5996 }
5997 
5998 /* Handle the MRI REG pseudo-op.  */
5999 
6000 static void
s_reg(int ignore ATTRIBUTE_UNUSED)6001 s_reg (int ignore ATTRIBUTE_UNUSED)
6002 {
6003   char *s;
6004   int c;
6005   struct m68k_op rop;
6006   int mask;
6007   char *stop = NULL;
6008   char stopc;
6009 
6010   if (line_label == NULL)
6011     {
6012       as_bad (_("missing label"));
6013       ignore_rest_of_line ();
6014       return;
6015     }
6016 
6017   if (flag_mri)
6018     stop = mri_comment_field (&stopc);
6019 
6020   SKIP_WHITESPACE ();
6021 
6022   s = input_line_pointer;
6023   while (ISALNUM (*input_line_pointer)
6024 #ifdef REGISTER_PREFIX
6025 	 || *input_line_pointer == REGISTER_PREFIX
6026 #endif
6027 	 || *input_line_pointer == '/'
6028 	 || *input_line_pointer == '-')
6029     ++input_line_pointer;
6030   c = *input_line_pointer;
6031   *input_line_pointer = '\0';
6032 
6033   if (m68k_ip_op (s, &rop) != 0)
6034     {
6035       if (rop.error == NULL)
6036 	as_bad (_("bad register list"));
6037       else
6038 	as_bad (_("bad register list: %s"), rop.error);
6039       *input_line_pointer = c;
6040       ignore_rest_of_line ();
6041       return;
6042     }
6043 
6044   *input_line_pointer = c;
6045 
6046   if (rop.mode == REGLST)
6047     mask = rop.mask;
6048   else if (rop.mode == DREG)
6049     mask = 1 << (rop.reg - DATA0);
6050   else if (rop.mode == AREG)
6051     mask = 1 << (rop.reg - ADDR0 + 8);
6052   else if (rop.mode == FPREG)
6053     mask = 1 << (rop.reg - FP0 + 16);
6054   else if (rop.mode == CONTROL
6055 	   && rop.reg == FPI)
6056     mask = 1 << 24;
6057   else if (rop.mode == CONTROL
6058 	   && rop.reg == FPS)
6059     mask = 1 << 25;
6060   else if (rop.mode == CONTROL
6061 	   && rop.reg == FPC)
6062     mask = 1 << 26;
6063   else
6064     {
6065       as_bad (_("bad register list"));
6066       ignore_rest_of_line ();
6067       return;
6068     }
6069 
6070   S_SET_SEGMENT (line_label, reg_section);
6071   S_SET_VALUE (line_label, ~mask);
6072   symbol_set_frag (line_label, &zero_address_frag);
6073 
6074   if (flag_mri)
6075     mri_comment_end (stop, stopc);
6076 
6077   demand_empty_rest_of_line ();
6078 }
6079 
6080 /* This structure is used for the MRI SAVE and RESTORE pseudo-ops.  */
6081 
6082 struct save_opts
6083 {
6084   struct save_opts *next;
6085   int abspcadd;
6086   int symbols_case_sensitive;
6087   int keep_locals;
6088   int short_refs;
6089   int architecture;
6090   const enum m68k_register *control_regs;
6091   int quick;
6092   int rel32;
6093   int listing;
6094   int no_warnings;
6095   /* FIXME: We don't save OPT S.  */
6096 };
6097 
6098 /* This variable holds the stack of saved options.  */
6099 
6100 static struct save_opts *save_stack;
6101 
6102 /* The MRI SAVE pseudo-op.  */
6103 
6104 static void
s_save(int ignore ATTRIBUTE_UNUSED)6105 s_save (int ignore ATTRIBUTE_UNUSED)
6106 {
6107   struct save_opts *s;
6108 
6109   s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6110   s->abspcadd = m68k_abspcadd;
6111   s->symbols_case_sensitive = symbols_case_sensitive;
6112   s->keep_locals = flag_keep_locals;
6113   s->short_refs = flag_short_refs;
6114   s->architecture = current_architecture;
6115   s->control_regs = control_regs;
6116   s->quick = m68k_quick;
6117   s->rel32 = m68k_rel32;
6118   s->listing = listing;
6119   s->no_warnings = flag_no_warnings;
6120 
6121   s->next = save_stack;
6122   save_stack = s;
6123 
6124   demand_empty_rest_of_line ();
6125 }
6126 
6127 /* The MRI RESTORE pseudo-op.  */
6128 
6129 static void
s_restore(int ignore ATTRIBUTE_UNUSED)6130 s_restore (int ignore ATTRIBUTE_UNUSED)
6131 {
6132   struct save_opts *s;
6133 
6134   if (save_stack == NULL)
6135     {
6136       as_bad (_("restore without save"));
6137       ignore_rest_of_line ();
6138       return;
6139     }
6140 
6141   s = save_stack;
6142   save_stack = s->next;
6143 
6144   m68k_abspcadd = s->abspcadd;
6145   symbols_case_sensitive = s->symbols_case_sensitive;
6146   flag_keep_locals = s->keep_locals;
6147   flag_short_refs = s->short_refs;
6148   current_architecture = s->architecture;
6149   control_regs = s->control_regs;
6150   m68k_quick = s->quick;
6151   m68k_rel32 = s->rel32;
6152   listing = s->listing;
6153   flag_no_warnings = s->no_warnings;
6154 
6155   free (s);
6156 
6157   demand_empty_rest_of_line ();
6158 }
6159 
6160 /* Types of MRI structured control directives.  */
6161 
6162 enum mri_control_type
6163 {
6164   mri_for,
6165   mri_if,
6166   mri_repeat,
6167   mri_while
6168 };
6169 
6170 /* This structure is used to stack the MRI structured control
6171    directives.  */
6172 
6173 struct mri_control_info
6174 {
6175   /* The directive within which this one is enclosed.  */
6176   struct mri_control_info *outer;
6177 
6178   /* The type of directive.  */
6179   enum mri_control_type type;
6180 
6181   /* Whether an ELSE has been in an IF.  */
6182   int else_seen;
6183 
6184   /* The add or sub statement at the end of a FOR.  */
6185   char *incr;
6186 
6187   /* The label of the top of a FOR or REPEAT loop.  */
6188   char *top;
6189 
6190   /* The label to jump to for the next iteration, or the else
6191      expression of a conditional.  */
6192   char *next;
6193 
6194   /* The label to jump to to break out of the loop, or the label past
6195      the end of a conditional.  */
6196   char *bottom;
6197 };
6198 
6199 /* The stack of MRI structured control directives.  */
6200 
6201 static struct mri_control_info *mri_control_stack;
6202 
6203 /* The current MRI structured control directive index number, used to
6204    generate label names.  */
6205 
6206 static int mri_control_index;
6207 
6208 /* Assemble an instruction for an MRI structured control directive.  */
6209 
6210 static void
mri_assemble(char * str)6211 mri_assemble (char *str)
6212 {
6213   char *s;
6214 
6215   /* md_assemble expects the opcode to be in lower case.  */
6216   for (s = str; *s != ' ' && *s != '\0'; s++)
6217     *s = TOLOWER (*s);
6218 
6219   md_assemble (str);
6220 }
6221 
6222 /* Generate a new MRI label structured control directive label name.  */
6223 
6224 static char *
mri_control_label(void)6225 mri_control_label (void)
6226 {
6227   char *n;
6228 
6229   n = (char *) xmalloc (20);
6230   sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6231   ++mri_control_index;
6232   return n;
6233 }
6234 
6235 /* Create a new MRI structured control directive.  */
6236 
6237 static struct mri_control_info *
push_mri_control(enum mri_control_type type)6238 push_mri_control (enum mri_control_type type)
6239 {
6240   struct mri_control_info *n;
6241 
6242   n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6243 
6244   n->type = type;
6245   n->else_seen = 0;
6246   if (type == mri_if || type == mri_while)
6247     n->top = NULL;
6248   else
6249     n->top = mri_control_label ();
6250   n->next = mri_control_label ();
6251   n->bottom = mri_control_label ();
6252 
6253   n->outer = mri_control_stack;
6254   mri_control_stack = n;
6255 
6256   return n;
6257 }
6258 
6259 /* Pop off the stack of MRI structured control directives.  */
6260 
6261 static void
pop_mri_control(void)6262 pop_mri_control (void)
6263 {
6264   struct mri_control_info *n;
6265 
6266   n = mri_control_stack;
6267   mri_control_stack = n->outer;
6268   if (n->top != NULL)
6269     free (n->top);
6270   free (n->next);
6271   free (n->bottom);
6272   free (n);
6273 }
6274 
6275 /* Recognize a condition code in an MRI structured control expression.  */
6276 
6277 static int
parse_mri_condition(int * pcc)6278 parse_mri_condition (int *pcc)
6279 {
6280   char c1, c2;
6281 
6282   know (*input_line_pointer == '<');
6283 
6284   ++input_line_pointer;
6285   c1 = *input_line_pointer++;
6286   c2 = *input_line_pointer++;
6287 
6288   if (*input_line_pointer != '>')
6289     {
6290       as_bad (_("syntax error in structured control directive"));
6291       return 0;
6292     }
6293 
6294   ++input_line_pointer;
6295   SKIP_WHITESPACE ();
6296 
6297   c1 = TOLOWER (c1);
6298   c2 = TOLOWER (c2);
6299 
6300   *pcc = (c1 << 8) | c2;
6301 
6302   return 1;
6303 }
6304 
6305 /* Parse a single operand in an MRI structured control expression.  */
6306 
6307 static int
parse_mri_control_operand(int * pcc,char ** leftstart,char ** leftstop,char ** rightstart,char ** rightstop)6308 parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6309 			   char **rightstart, char **rightstop)
6310 {
6311   char *s;
6312 
6313   SKIP_WHITESPACE ();
6314 
6315   *pcc = -1;
6316   *leftstart = NULL;
6317   *leftstop = NULL;
6318   *rightstart = NULL;
6319   *rightstop = NULL;
6320 
6321   if (*input_line_pointer == '<')
6322     {
6323       /* It's just a condition code.  */
6324       return parse_mri_condition (pcc);
6325     }
6326 
6327   /* Look ahead for the condition code.  */
6328   for (s = input_line_pointer; *s != '\0'; ++s)
6329     {
6330       if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6331 	break;
6332     }
6333   if (*s == '\0')
6334     {
6335       as_bad (_("missing condition code in structured control directive"));
6336       return 0;
6337     }
6338 
6339   *leftstart = input_line_pointer;
6340   *leftstop = s;
6341   if (*leftstop > *leftstart
6342       && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6343     --*leftstop;
6344 
6345   input_line_pointer = s;
6346   if (! parse_mri_condition (pcc))
6347     return 0;
6348 
6349   /* Look ahead for AND or OR or end of line.  */
6350   for (s = input_line_pointer; *s != '\0'; ++s)
6351     {
6352       /* We must make sure we don't misinterpret AND/OR at the end of labels!
6353          if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6354                         ^^^                 ^^ */
6355       if ((s == input_line_pointer
6356 	   || *(s-1) == ' '
6357 	   || *(s-1) == '\t')
6358 	  && ((strncasecmp (s, "AND", 3) == 0
6359 	       && (s[3] == '.' || ! is_part_of_name (s[3])))
6360 	      || (strncasecmp (s, "OR", 2) == 0
6361 		  && (s[2] == '.' || ! is_part_of_name (s[2])))))
6362 	break;
6363     }
6364 
6365   *rightstart = input_line_pointer;
6366   *rightstop = s;
6367   if (*rightstop > *rightstart
6368       && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6369     --*rightstop;
6370 
6371   input_line_pointer = s;
6372 
6373   return 1;
6374 }
6375 
6376 #define MCC(b1, b2) (((b1) << 8) | (b2))
6377 
6378 /* Swap the sense of a condition.  This changes the condition so that
6379    it generates the same result when the operands are swapped.  */
6380 
6381 static int
swap_mri_condition(int cc)6382 swap_mri_condition (int cc)
6383 {
6384   switch (cc)
6385     {
6386     case MCC ('h', 'i'): return MCC ('c', 's');
6387     case MCC ('l', 's'): return MCC ('c', 'c');
6388     /* <HS> is an alias for <CC>.  */
6389     case MCC ('h', 's'):
6390     case MCC ('c', 'c'): return MCC ('l', 's');
6391     /* <LO> is an alias for <CS>.  */
6392     case MCC ('l', 'o'):
6393     case MCC ('c', 's'): return MCC ('h', 'i');
6394     case MCC ('p', 'l'): return MCC ('m', 'i');
6395     case MCC ('m', 'i'): return MCC ('p', 'l');
6396     case MCC ('g', 'e'): return MCC ('l', 'e');
6397     case MCC ('l', 't'): return MCC ('g', 't');
6398     case MCC ('g', 't'): return MCC ('l', 't');
6399     case MCC ('l', 'e'): return MCC ('g', 'e');
6400     /* Issue a warning for conditions we can not swap.  */
6401     case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6402     case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
6403     case MCC ('v', 'c'):
6404     case MCC ('v', 's'):
6405     default :
6406 	   as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6407 		         (char) (cc >> 8), (char) (cc));
6408       break;
6409     }
6410   return cc;
6411 }
6412 
6413 /* Reverse the sense of a condition.  */
6414 
6415 static int
reverse_mri_condition(int cc)6416 reverse_mri_condition (int cc)
6417 {
6418   switch (cc)
6419     {
6420     case MCC ('h', 'i'): return MCC ('l', 's');
6421     case MCC ('l', 's'): return MCC ('h', 'i');
6422     /* <HS> is an alias for <CC> */
6423     case MCC ('h', 's'): return MCC ('l', 'o');
6424     case MCC ('c', 'c'): return MCC ('c', 's');
6425     /* <LO> is an alias for <CS> */
6426     case MCC ('l', 'o'): return MCC ('h', 's');
6427     case MCC ('c', 's'): return MCC ('c', 'c');
6428     case MCC ('n', 'e'): return MCC ('e', 'q');
6429     case MCC ('e', 'q'): return MCC ('n', 'e');
6430     case MCC ('v', 'c'): return MCC ('v', 's');
6431     case MCC ('v', 's'): return MCC ('v', 'c');
6432     case MCC ('p', 'l'): return MCC ('m', 'i');
6433     case MCC ('m', 'i'): return MCC ('p', 'l');
6434     case MCC ('g', 'e'): return MCC ('l', 't');
6435     case MCC ('l', 't'): return MCC ('g', 'e');
6436     case MCC ('g', 't'): return MCC ('l', 'e');
6437     case MCC ('l', 'e'): return MCC ('g', 't');
6438     }
6439   return cc;
6440 }
6441 
6442 /* Build an MRI structured control expression.  This generates test
6443    and branch instructions.  It goes to TRUELAB if the condition is
6444    true, and to FALSELAB if the condition is false.  Exactly one of
6445    TRUELAB and FALSELAB will be NULL, meaning to fall through.  QUAL
6446    is the size qualifier for the expression.  EXTENT is the size to
6447    use for the branch.  */
6448 
6449 static void
build_mri_control_operand(int qual,int cc,char * leftstart,char * leftstop,char * rightstart,char * rightstop,const char * truelab,const char * falselab,int extent)6450 build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6451 			   char *rightstart, char *rightstop,
6452 			   const char *truelab, const char *falselab,
6453 			   int extent)
6454 {
6455   char *buf;
6456   char *s;
6457 
6458   if (leftstart != NULL)
6459     {
6460       struct m68k_op leftop, rightop;
6461       char c;
6462 
6463       /* Swap the compare operands, if necessary, to produce a legal
6464 	 m68k compare instruction.  Comparing a register operand with
6465 	 a non-register operand requires the register to be on the
6466 	 right (cmp, cmpa).  Comparing an immediate value with
6467 	 anything requires the immediate value to be on the left
6468 	 (cmpi).  */
6469 
6470       c = *leftstop;
6471       *leftstop = '\0';
6472       (void) m68k_ip_op (leftstart, &leftop);
6473       *leftstop = c;
6474 
6475       c = *rightstop;
6476       *rightstop = '\0';
6477       (void) m68k_ip_op (rightstart, &rightop);
6478       *rightstop = c;
6479 
6480       if (rightop.mode == IMMED
6481 	  || ((leftop.mode == DREG || leftop.mode == AREG)
6482 	      && (rightop.mode != DREG && rightop.mode != AREG)))
6483 	{
6484 	  char *temp;
6485 
6486 	  /* Correct conditional handling:
6487 	     if #1 <lt> d0 then  ;means if (1 < d0)
6488 		...
6489 	     endi
6490 
6491 	     should assemble to:
6492 
6493 		cmp #1,d0        if we do *not* swap the operands
6494 		bgt true         we need the swapped condition!
6495 		ble false
6496 	     true:
6497 		...
6498 	     false:
6499 	  */
6500 	  temp = leftstart;
6501 	  leftstart = rightstart;
6502 	  rightstart = temp;
6503 	  temp = leftstop;
6504 	  leftstop = rightstop;
6505 	  rightstop = temp;
6506 	}
6507       else
6508 	{
6509 	  cc = swap_mri_condition (cc);
6510 	}
6511     }
6512 
6513   if (truelab == NULL)
6514     {
6515       cc = reverse_mri_condition (cc);
6516       truelab = falselab;
6517     }
6518 
6519   if (leftstart != NULL)
6520     {
6521       buf = (char *) xmalloc (20
6522 			      + (leftstop - leftstart)
6523 			      + (rightstop - rightstart));
6524       s = buf;
6525       *s++ = 'c';
6526       *s++ = 'm';
6527       *s++ = 'p';
6528       if (qual != '\0')
6529 	*s++ = TOLOWER (qual);
6530       *s++ = ' ';
6531       memcpy (s, leftstart, leftstop - leftstart);
6532       s += leftstop - leftstart;
6533       *s++ = ',';
6534       memcpy (s, rightstart, rightstop - rightstart);
6535       s += rightstop - rightstart;
6536       *s = '\0';
6537       mri_assemble (buf);
6538       free (buf);
6539     }
6540 
6541   buf = (char *) xmalloc (20 + strlen (truelab));
6542   s = buf;
6543   *s++ = 'b';
6544   *s++ = cc >> 8;
6545   *s++ = cc & 0xff;
6546   if (extent != '\0')
6547     *s++ = TOLOWER (extent);
6548   *s++ = ' ';
6549   strcpy (s, truelab);
6550   mri_assemble (buf);
6551   free (buf);
6552 }
6553 
6554 /* Parse an MRI structured control expression.  This generates test
6555    and branch instructions.  STOP is where the expression ends.  It
6556    goes to TRUELAB if the condition is true, and to FALSELAB if the
6557    condition is false.  Exactly one of TRUELAB and FALSELAB will be
6558    NULL, meaning to fall through.  QUAL is the size qualifier for the
6559    expression.  EXTENT is the size to use for the branch.  */
6560 
6561 static void
parse_mri_control_expression(char * stop,int qual,const char * truelab,const char * falselab,int extent)6562 parse_mri_control_expression (char *stop, int qual, const char *truelab,
6563 			      const char *falselab, int extent)
6564 {
6565   int c;
6566   int cc;
6567   char *leftstart;
6568   char *leftstop;
6569   char *rightstart;
6570   char *rightstop;
6571 
6572   c = *stop;
6573   *stop = '\0';
6574 
6575   if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6576 				   &rightstart, &rightstop))
6577     {
6578       *stop = c;
6579       return;
6580     }
6581 
6582   if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6583     {
6584       const char *flab;
6585 
6586       if (falselab != NULL)
6587 	flab = falselab;
6588       else
6589 	flab = mri_control_label ();
6590 
6591       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6592 				 rightstop, (const char *) NULL, flab, extent);
6593 
6594       input_line_pointer += 3;
6595       if (*input_line_pointer != '.'
6596 	  || input_line_pointer[1] == '\0')
6597 	qual = '\0';
6598       else
6599 	{
6600 	  qual = input_line_pointer[1];
6601 	  input_line_pointer += 2;
6602 	}
6603 
6604       if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6605 				       &rightstart, &rightstop))
6606 	{
6607 	  *stop = c;
6608 	  return;
6609 	}
6610 
6611       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6612 				 rightstop, truelab, falselab, extent);
6613 
6614       if (falselab == NULL)
6615 	colon (flab);
6616     }
6617   else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6618     {
6619       const char *tlab;
6620 
6621       if (truelab != NULL)
6622 	tlab = truelab;
6623       else
6624 	tlab = mri_control_label ();
6625 
6626       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6627 				 rightstop, tlab, (const char *) NULL, extent);
6628 
6629       input_line_pointer += 2;
6630       if (*input_line_pointer != '.'
6631 	  || input_line_pointer[1] == '\0')
6632 	qual = '\0';
6633       else
6634 	{
6635 	  qual = input_line_pointer[1];
6636 	  input_line_pointer += 2;
6637 	}
6638 
6639       if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6640 				       &rightstart, &rightstop))
6641 	{
6642 	  *stop = c;
6643 	  return;
6644 	}
6645 
6646       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6647 				 rightstop, truelab, falselab, extent);
6648 
6649       if (truelab == NULL)
6650 	colon (tlab);
6651     }
6652   else
6653     {
6654       build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6655 				 rightstop, truelab, falselab, extent);
6656     }
6657 
6658   *stop = c;
6659   if (input_line_pointer != stop)
6660     as_bad (_("syntax error in structured control directive"));
6661 }
6662 
6663 /* Handle the MRI IF pseudo-op.  This may be a structured control
6664    directive, or it may be a regular assembler conditional, depending
6665    on its operands.  */
6666 
6667 static void
s_mri_if(int qual)6668 s_mri_if (int qual)
6669 {
6670   char *s;
6671   int c;
6672   struct mri_control_info *n;
6673 
6674   /* A structured control directive must end with THEN with an
6675      optional qualifier.  */
6676   s = input_line_pointer;
6677   /* We only accept '*' as introduction of comments if preceded by white space
6678      or at first column of a line (I think this can't actually happen here?)
6679      This is important when assembling:
6680        if d0 <ne> 12(a0,d0*2) then
6681        if d0 <ne> #CONST*20   then.  */
6682   while (! (is_end_of_line[(unsigned char) *s]
6683             || (flag_mri
6684                 && *s == '*'
6685                 && (s == input_line_pointer
6686                     || *(s-1) == ' '
6687                     || *(s-1) == '\t'))))
6688     ++s;
6689   --s;
6690   while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6691     --s;
6692 
6693   if (s - input_line_pointer > 1
6694       && s[-1] == '.')
6695     s -= 2;
6696 
6697   if (s - input_line_pointer < 3
6698       || strncasecmp (s - 3, "THEN", 4) != 0)
6699     {
6700       if (qual != '\0')
6701 	{
6702 	  as_bad (_("missing then"));
6703 	  ignore_rest_of_line ();
6704 	  return;
6705 	}
6706 
6707       /* It's a conditional.  */
6708       s_if (O_ne);
6709       return;
6710     }
6711 
6712   /* Since this might be a conditional if, this pseudo-op will be
6713      called even if we are supported to be ignoring input.  Double
6714      check now.  Clobber *input_line_pointer so that ignore_input
6715      thinks that this is not a special pseudo-op.  */
6716   c = *input_line_pointer;
6717   *input_line_pointer = 0;
6718   if (ignore_input ())
6719     {
6720       *input_line_pointer = c;
6721       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6722 	++input_line_pointer;
6723       demand_empty_rest_of_line ();
6724       return;
6725     }
6726   *input_line_pointer = c;
6727 
6728   n = push_mri_control (mri_if);
6729 
6730   parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6731 				n->next, s[1] == '.' ? s[2] : '\0');
6732 
6733   if (s[1] == '.')
6734     input_line_pointer = s + 3;
6735   else
6736     input_line_pointer = s + 1;
6737 
6738   if (flag_mri)
6739     {
6740       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6741 	++input_line_pointer;
6742     }
6743 
6744   demand_empty_rest_of_line ();
6745 }
6746 
6747 /* Handle the MRI else pseudo-op.  If we are currently doing an MRI
6748    structured IF, associate the ELSE with the IF.  Otherwise, assume
6749    it is a conditional else.  */
6750 
6751 static void
s_mri_else(int qual)6752 s_mri_else (int qual)
6753 {
6754   int c;
6755   char *buf;
6756   char q[2];
6757 
6758   if (qual == '\0'
6759       && (mri_control_stack == NULL
6760 	  || mri_control_stack->type != mri_if
6761 	  || mri_control_stack->else_seen))
6762     {
6763       s_else (0);
6764       return;
6765     }
6766 
6767   c = *input_line_pointer;
6768   *input_line_pointer = 0;
6769   if (ignore_input ())
6770     {
6771       *input_line_pointer = c;
6772       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6773 	++input_line_pointer;
6774       demand_empty_rest_of_line ();
6775       return;
6776     }
6777   *input_line_pointer = c;
6778 
6779   if (mri_control_stack == NULL
6780       || mri_control_stack->type != mri_if
6781       || mri_control_stack->else_seen)
6782     {
6783       as_bad (_("else without matching if"));
6784       ignore_rest_of_line ();
6785       return;
6786     }
6787 
6788   mri_control_stack->else_seen = 1;
6789 
6790   buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6791   q[0] = TOLOWER (qual);
6792   q[1] = '\0';
6793   sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6794   mri_assemble (buf);
6795   free (buf);
6796 
6797   colon (mri_control_stack->next);
6798 
6799   if (flag_mri)
6800     {
6801       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6802 	++input_line_pointer;
6803     }
6804 
6805   demand_empty_rest_of_line ();
6806 }
6807 
6808 /* Handle the MRI ENDI pseudo-op.  */
6809 
6810 static void
s_mri_endi(int ignore ATTRIBUTE_UNUSED)6811 s_mri_endi (int ignore ATTRIBUTE_UNUSED)
6812 {
6813   if (mri_control_stack == NULL
6814       || mri_control_stack->type != mri_if)
6815     {
6816       as_bad (_("endi without matching if"));
6817       ignore_rest_of_line ();
6818       return;
6819     }
6820 
6821   /* ignore_input will not return true for ENDI, so we don't need to
6822      worry about checking it again here.  */
6823 
6824   if (! mri_control_stack->else_seen)
6825     colon (mri_control_stack->next);
6826   colon (mri_control_stack->bottom);
6827 
6828   pop_mri_control ();
6829 
6830   if (flag_mri)
6831     {
6832       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6833 	++input_line_pointer;
6834     }
6835 
6836   demand_empty_rest_of_line ();
6837 }
6838 
6839 /* Handle the MRI BREAK pseudo-op.  */
6840 
6841 static void
s_mri_break(int extent)6842 s_mri_break (int extent)
6843 {
6844   struct mri_control_info *n;
6845   char *buf;
6846   char ex[2];
6847 
6848   n = mri_control_stack;
6849   while (n != NULL
6850 	 && n->type != mri_for
6851 	 && n->type != mri_repeat
6852 	 && n->type != mri_while)
6853     n = n->outer;
6854   if (n == NULL)
6855     {
6856       as_bad (_("break outside of structured loop"));
6857       ignore_rest_of_line ();
6858       return;
6859     }
6860 
6861   buf = (char *) xmalloc (20 + strlen (n->bottom));
6862   ex[0] = TOLOWER (extent);
6863   ex[1] = '\0';
6864   sprintf (buf, "bra%s %s", ex, n->bottom);
6865   mri_assemble (buf);
6866   free (buf);
6867 
6868   if (flag_mri)
6869     {
6870       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6871 	++input_line_pointer;
6872     }
6873 
6874   demand_empty_rest_of_line ();
6875 }
6876 
6877 /* Handle the MRI NEXT pseudo-op.  */
6878 
6879 static void
s_mri_next(int extent)6880 s_mri_next (int extent)
6881 {
6882   struct mri_control_info *n;
6883   char *buf;
6884   char ex[2];
6885 
6886   n = mri_control_stack;
6887   while (n != NULL
6888 	 && n->type != mri_for
6889 	 && n->type != mri_repeat
6890 	 && n->type != mri_while)
6891     n = n->outer;
6892   if (n == NULL)
6893     {
6894       as_bad (_("next outside of structured loop"));
6895       ignore_rest_of_line ();
6896       return;
6897     }
6898 
6899   buf = (char *) xmalloc (20 + strlen (n->next));
6900   ex[0] = TOLOWER (extent);
6901   ex[1] = '\0';
6902   sprintf (buf, "bra%s %s", ex, n->next);
6903   mri_assemble (buf);
6904   free (buf);
6905 
6906   if (flag_mri)
6907     {
6908       while (! is_end_of_line[(unsigned char) *input_line_pointer])
6909 	++input_line_pointer;
6910     }
6911 
6912   demand_empty_rest_of_line ();
6913 }
6914 
6915 /* Handle the MRI FOR pseudo-op.  */
6916 
6917 static void
s_mri_for(int qual)6918 s_mri_for (int qual)
6919 {
6920   const char *varstart, *varstop;
6921   const char *initstart, *initstop;
6922   const char *endstart, *endstop;
6923   const char *bystart, *bystop;
6924   int up;
6925   int by;
6926   int extent;
6927   struct mri_control_info *n;
6928   char *buf;
6929   char *s;
6930   char ex[2];
6931 
6932   /* The syntax is
6933        FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6934      */
6935 
6936   SKIP_WHITESPACE ();
6937   varstart = input_line_pointer;
6938 
6939   /* Look for the '='.  */
6940   while (! is_end_of_line[(unsigned char) *input_line_pointer]
6941 	 && *input_line_pointer != '=')
6942     ++input_line_pointer;
6943   if (*input_line_pointer != '=')
6944     {
6945       as_bad (_("missing ="));
6946       ignore_rest_of_line ();
6947       return;
6948     }
6949 
6950   varstop = input_line_pointer;
6951   if (varstop > varstart
6952       && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6953     --varstop;
6954 
6955   ++input_line_pointer;
6956 
6957   initstart = input_line_pointer;
6958 
6959   /* Look for TO or DOWNTO.  */
6960   up = 1;
6961   initstop = NULL;
6962   while (! is_end_of_line[(unsigned char) *input_line_pointer])
6963     {
6964       if (strncasecmp (input_line_pointer, "TO", 2) == 0
6965 	  && ! is_part_of_name (input_line_pointer[2]))
6966 	{
6967 	  initstop = input_line_pointer;
6968 	  input_line_pointer += 2;
6969 	  break;
6970 	}
6971       if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6972 	  && ! is_part_of_name (input_line_pointer[6]))
6973 	{
6974 	  initstop = input_line_pointer;
6975 	  up = 0;
6976 	  input_line_pointer += 6;
6977 	  break;
6978 	}
6979       ++input_line_pointer;
6980     }
6981   if (initstop == NULL)
6982     {
6983       as_bad (_("missing to or downto"));
6984       ignore_rest_of_line ();
6985       return;
6986     }
6987   if (initstop > initstart
6988       && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6989     --initstop;
6990 
6991   SKIP_WHITESPACE ();
6992   endstart = input_line_pointer;
6993 
6994   /* Look for BY or DO.  */
6995   by = 0;
6996   endstop = NULL;
6997   while (! is_end_of_line[(unsigned char) *input_line_pointer])
6998     {
6999       if (strncasecmp (input_line_pointer, "BY", 2) == 0
7000 	  && ! is_part_of_name (input_line_pointer[2]))
7001 	{
7002 	  endstop = input_line_pointer;
7003 	  by = 1;
7004 	  input_line_pointer += 2;
7005 	  break;
7006 	}
7007       if (strncasecmp (input_line_pointer, "DO", 2) == 0
7008 	  && (input_line_pointer[2] == '.'
7009 	      || ! is_part_of_name (input_line_pointer[2])))
7010 	{
7011 	  endstop = input_line_pointer;
7012 	  input_line_pointer += 2;
7013 	  break;
7014 	}
7015       ++input_line_pointer;
7016     }
7017   if (endstop == NULL)
7018     {
7019       as_bad (_("missing do"));
7020       ignore_rest_of_line ();
7021       return;
7022     }
7023   if (endstop > endstart
7024       && (endstop[-1] == ' ' || endstop[-1] == '\t'))
7025     --endstop;
7026 
7027   if (! by)
7028     {
7029       bystart = "#1";
7030       bystop = bystart + 2;
7031     }
7032   else
7033     {
7034       SKIP_WHITESPACE ();
7035       bystart = input_line_pointer;
7036 
7037       /* Look for DO.  */
7038       bystop = NULL;
7039       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7040 	{
7041 	  if (strncasecmp (input_line_pointer, "DO", 2) == 0
7042 	      && (input_line_pointer[2] == '.'
7043 		  || ! is_part_of_name (input_line_pointer[2])))
7044 	    {
7045 	      bystop = input_line_pointer;
7046 	      input_line_pointer += 2;
7047 	      break;
7048 	    }
7049 	  ++input_line_pointer;
7050 	}
7051       if (bystop == NULL)
7052 	{
7053 	  as_bad (_("missing do"));
7054 	  ignore_rest_of_line ();
7055 	  return;
7056 	}
7057       if (bystop > bystart
7058 	  && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7059 	--bystop;
7060     }
7061 
7062   if (*input_line_pointer != '.')
7063     extent = '\0';
7064   else
7065     {
7066       extent = input_line_pointer[1];
7067       input_line_pointer += 2;
7068     }
7069 
7070   /* We have fully parsed the FOR operands.  Now build the loop.  */
7071   n = push_mri_control (mri_for);
7072 
7073   buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7074 
7075   /* Move init,var.  */
7076   s = buf;
7077   *s++ = 'm';
7078   *s++ = 'o';
7079   *s++ = 'v';
7080   *s++ = 'e';
7081   if (qual != '\0')
7082     *s++ = TOLOWER (qual);
7083   *s++ = ' ';
7084   memcpy (s, initstart, initstop - initstart);
7085   s += initstop - initstart;
7086   *s++ = ',';
7087   memcpy (s, varstart, varstop - varstart);
7088   s += varstop - varstart;
7089   *s = '\0';
7090   mri_assemble (buf);
7091 
7092   colon (n->top);
7093 
7094   /* cmp end,var.  */
7095   s = buf;
7096   *s++ = 'c';
7097   *s++ = 'm';
7098   *s++ = 'p';
7099   if (qual != '\0')
7100     *s++ = TOLOWER (qual);
7101   *s++ = ' ';
7102   memcpy (s, endstart, endstop - endstart);
7103   s += endstop - endstart;
7104   *s++ = ',';
7105   memcpy (s, varstart, varstop - varstart);
7106   s += varstop - varstart;
7107   *s = '\0';
7108   mri_assemble (buf);
7109 
7110   /* bcc bottom.  */
7111   ex[0] = TOLOWER (extent);
7112   ex[1] = '\0';
7113   if (up)
7114     sprintf (buf, "blt%s %s", ex, n->bottom);
7115   else
7116     sprintf (buf, "bgt%s %s", ex, n->bottom);
7117   mri_assemble (buf);
7118 
7119   /* Put together the add or sub instruction used by ENDF.  */
7120   s = buf;
7121   if (up)
7122     strcpy (s, "add");
7123   else
7124     strcpy (s, "sub");
7125   s += 3;
7126   if (qual != '\0')
7127     *s++ = TOLOWER (qual);
7128   *s++ = ' ';
7129   memcpy (s, bystart, bystop - bystart);
7130   s += bystop - bystart;
7131   *s++ = ',';
7132   memcpy (s, varstart, varstop - varstart);
7133   s += varstop - varstart;
7134   *s = '\0';
7135   n->incr = buf;
7136 
7137   if (flag_mri)
7138     {
7139       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7140 	++input_line_pointer;
7141     }
7142 
7143   demand_empty_rest_of_line ();
7144 }
7145 
7146 /* Handle the MRI ENDF pseudo-op.  */
7147 
7148 static void
s_mri_endf(int ignore ATTRIBUTE_UNUSED)7149 s_mri_endf (int ignore ATTRIBUTE_UNUSED)
7150 {
7151   if (mri_control_stack == NULL
7152       || mri_control_stack->type != mri_for)
7153     {
7154       as_bad (_("endf without for"));
7155       ignore_rest_of_line ();
7156       return;
7157     }
7158 
7159   colon (mri_control_stack->next);
7160 
7161   mri_assemble (mri_control_stack->incr);
7162 
7163   sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7164   mri_assemble (mri_control_stack->incr);
7165 
7166   free (mri_control_stack->incr);
7167 
7168   colon (mri_control_stack->bottom);
7169 
7170   pop_mri_control ();
7171 
7172   if (flag_mri)
7173     {
7174       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7175 	++input_line_pointer;
7176     }
7177 
7178   demand_empty_rest_of_line ();
7179 }
7180 
7181 /* Handle the MRI REPEAT pseudo-op.  */
7182 
7183 static void
s_mri_repeat(int ignore ATTRIBUTE_UNUSED)7184 s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
7185 {
7186   struct mri_control_info *n;
7187 
7188   n = push_mri_control (mri_repeat);
7189   colon (n->top);
7190   if (flag_mri)
7191     {
7192       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7193 	++input_line_pointer;
7194     }
7195   demand_empty_rest_of_line ();
7196 }
7197 
7198 /* Handle the MRI UNTIL pseudo-op.  */
7199 
7200 static void
s_mri_until(int qual)7201 s_mri_until (int qual)
7202 {
7203   char *s;
7204 
7205   if (mri_control_stack == NULL
7206       || mri_control_stack->type != mri_repeat)
7207     {
7208       as_bad (_("until without repeat"));
7209       ignore_rest_of_line ();
7210       return;
7211     }
7212 
7213   colon (mri_control_stack->next);
7214 
7215   for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7216     ;
7217 
7218   parse_mri_control_expression (s, qual, (const char *) NULL,
7219 				mri_control_stack->top, '\0');
7220 
7221   colon (mri_control_stack->bottom);
7222 
7223   input_line_pointer = s;
7224 
7225   pop_mri_control ();
7226 
7227   if (flag_mri)
7228     {
7229       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7230 	++input_line_pointer;
7231     }
7232 
7233   demand_empty_rest_of_line ();
7234 }
7235 
7236 /* Handle the MRI WHILE pseudo-op.  */
7237 
7238 static void
s_mri_while(int qual)7239 s_mri_while (int qual)
7240 {
7241   char *s;
7242 
7243   struct mri_control_info *n;
7244 
7245   s = input_line_pointer;
7246   /* We only accept '*' as introduction of comments if preceded by white space
7247      or at first column of a line (I think this can't actually happen here?)
7248      This is important when assembling:
7249        while d0 <ne> 12(a0,d0*2) do
7250        while d0 <ne> #CONST*20   do.  */
7251   while (! (is_end_of_line[(unsigned char) *s]
7252 	    || (flag_mri
7253 		&& *s == '*'
7254 		&& (s == input_line_pointer
7255 		    || *(s-1) == ' '
7256 		    || *(s-1) == '\t'))))
7257     s++;
7258   --s;
7259   while (*s == ' ' || *s == '\t')
7260     --s;
7261   if (s - input_line_pointer > 1
7262       && s[-1] == '.')
7263     s -= 2;
7264   if (s - input_line_pointer < 2
7265       || strncasecmp (s - 1, "DO", 2) != 0)
7266     {
7267       as_bad (_("missing do"));
7268       ignore_rest_of_line ();
7269       return;
7270     }
7271 
7272   n = push_mri_control (mri_while);
7273 
7274   colon (n->next);
7275 
7276   parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7277 				s[1] == '.' ? s[2] : '\0');
7278 
7279   input_line_pointer = s + 1;
7280   if (*input_line_pointer == '.')
7281     input_line_pointer += 2;
7282 
7283   if (flag_mri)
7284     {
7285       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7286 	++input_line_pointer;
7287     }
7288 
7289   demand_empty_rest_of_line ();
7290 }
7291 
7292 /* Handle the MRI ENDW pseudo-op.  */
7293 
7294 static void
s_mri_endw(int ignore ATTRIBUTE_UNUSED)7295 s_mri_endw (int ignore ATTRIBUTE_UNUSED)
7296 {
7297   char *buf;
7298 
7299   if (mri_control_stack == NULL
7300       || mri_control_stack->type != mri_while)
7301     {
7302       as_bad (_("endw without while"));
7303       ignore_rest_of_line ();
7304       return;
7305     }
7306 
7307   buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7308   sprintf (buf, "bra %s", mri_control_stack->next);
7309   mri_assemble (buf);
7310   free (buf);
7311 
7312   colon (mri_control_stack->bottom);
7313 
7314   pop_mri_control ();
7315 
7316   if (flag_mri)
7317     {
7318       while (! is_end_of_line[(unsigned char) *input_line_pointer])
7319 	++input_line_pointer;
7320     }
7321 
7322   demand_empty_rest_of_line ();
7323 }
7324 
7325 /* Parse a .cpu directive.  */
7326 
7327 static void
s_m68k_cpu(int ignored ATTRIBUTE_UNUSED)7328 s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7329 {
7330   char saved_char;
7331   char *name;
7332 
7333   if (initialized)
7334     {
7335       as_bad (_("already assembled instructions"));
7336       ignore_rest_of_line ();
7337       return;
7338     }
7339 
7340   name = input_line_pointer;
7341   while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7342     input_line_pointer++;
7343   saved_char = *input_line_pointer;
7344   *input_line_pointer = 0;
7345 
7346   m68k_set_cpu (name, 1, 0);
7347 
7348   *input_line_pointer = saved_char;
7349   demand_empty_rest_of_line ();
7350   return;
7351 }
7352 
7353 /* Parse a .arch directive.  */
7354 
7355 static void
s_m68k_arch(int ignored ATTRIBUTE_UNUSED)7356 s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7357 {
7358   char saved_char;
7359   char *name;
7360 
7361   if (initialized)
7362     {
7363       as_bad (_("already assembled instructions"));
7364       ignore_rest_of_line ();
7365       return;
7366     }
7367 
7368   name = input_line_pointer;
7369   while (*input_line_pointer && *input_line_pointer != ','
7370 	 && !ISSPACE (*input_line_pointer))
7371     input_line_pointer++;
7372   saved_char = *input_line_pointer;
7373   *input_line_pointer = 0;
7374 
7375   if (m68k_set_arch (name, 1, 0))
7376     {
7377       /* Scan extensions. */
7378       do
7379 	{
7380 	  *input_line_pointer++ = saved_char;
7381 	  if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7382 	    break;
7383 	  name = input_line_pointer;
7384 	  while (*input_line_pointer && *input_line_pointer != ','
7385 		 && !ISSPACE (*input_line_pointer))
7386 	    input_line_pointer++;
7387 	  saved_char = *input_line_pointer;
7388 	  *input_line_pointer = 0;
7389 	}
7390       while (m68k_set_extension (name, 1, 0));
7391     }
7392 
7393   *input_line_pointer = saved_char;
7394   demand_empty_rest_of_line ();
7395   return;
7396 }
7397 
7398 /* Lookup a cpu name in TABLE and return the slot found.  Return NULL
7399    if none is found, the caller is responsible for emitting an error
7400    message.  If ALLOW_M is non-zero, we allow an initial 'm' on the
7401    cpu name, if it begins with a '6' (possibly skipping an intervening
7402    'c'.  We also allow a 'c' in the same place.  if NEGATED is
7403    non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7404    the option is indeed negated.  */
7405 
7406 static const struct m68k_cpu *
m68k_lookup_cpu(const char * arg,const struct m68k_cpu * table,int allow_m,int * negated)7407 m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7408 		 int allow_m, int *negated)
7409 {
7410   /* allow negated value? */
7411   if (negated)
7412     {
7413       *negated = 0;
7414 
7415       if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7416 	{
7417 	  arg += 3;
7418 	  *negated = 1;
7419 	}
7420     }
7421 
7422   /* Remove 'm' or 'mc' prefix from 68k variants.  */
7423   if (allow_m)
7424     {
7425       if (arg[0] == 'm')
7426 	{
7427 	  if (arg[1] == '6')
7428 	    arg += 1;
7429 	  else if (arg[1] == 'c'  && arg[2] == '6')
7430 	    arg += 2;
7431 	}
7432     }
7433   else if (arg[0] == 'c' && arg[1] == '6')
7434     arg += 1;
7435 
7436   for (; table->name; table++)
7437     if (!strcmp (arg, table->name))
7438       {
7439 	if (table->alias < -1 || table->alias > 1)
7440 	  as_bad (_("`%s' is deprecated, use `%s'"),
7441 		  table->name, table[table->alias < 0 ? 1 : -1].name);
7442 	return table;
7443       }
7444   return 0;
7445 }
7446 
7447 /* Set the cpu, issuing errors if it is unrecognized.  */
7448 
7449 static int
m68k_set_cpu(char const * name,int allow_m,int silent)7450 m68k_set_cpu (char const *name, int allow_m, int silent)
7451 {
7452   const struct m68k_cpu *cpu;
7453 
7454   cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7455 
7456   if (!cpu)
7457     {
7458       if (!silent)
7459 	as_bad (_("cpu `%s' unrecognized"), name);
7460       return 0;
7461     }
7462   selected_cpu = cpu;
7463   return 1;
7464 }
7465 
7466 /* Set the architecture, issuing errors if it is unrecognized.  */
7467 
7468 static int
m68k_set_arch(char const * name,int allow_m,int silent)7469 m68k_set_arch (char const *name, int allow_m, int silent)
7470 {
7471   const struct m68k_cpu *arch;
7472 
7473   arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7474 
7475   if (!arch)
7476     {
7477       if (!silent)
7478 	as_bad (_("architecture `%s' unrecognized"), name);
7479       return 0;
7480     }
7481   selected_arch = arch;
7482   return 1;
7483 }
7484 
7485 /* Set the architecture extension, issuing errors if it is
7486    unrecognized, or invalid */
7487 
7488 static int
m68k_set_extension(char const * name,int allow_m,int silent)7489 m68k_set_extension (char const *name, int allow_m, int silent)
7490 {
7491   int negated;
7492   const struct m68k_cpu *ext;
7493 
7494   ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7495 
7496   if (!ext)
7497     {
7498       if (!silent)
7499 	as_bad (_("extension `%s' unrecognized"), name);
7500       return 0;
7501     }
7502 
7503   if (negated)
7504     not_current_architecture |= (ext->control_regs
7505 				 ? *(unsigned *)ext->control_regs: ext->arch);
7506   else
7507     current_architecture |= ext->arch;
7508   return 1;
7509 }
7510 
7511 /* md_parse_option
7512    Invocation line includes a switch not recognized by the base assembler.
7513  */
7514 
7515 #ifdef OBJ_ELF
7516 const char *md_shortopts = "lSA:m:kQ:V";
7517 #else
7518 const char *md_shortopts = "lSA:m:k";
7519 #endif
7520 
7521 struct option md_longopts[] = {
7522 #define OPTION_PIC (OPTION_MD_BASE)
7523   {"pic", no_argument, NULL, OPTION_PIC},
7524 #define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7525   {"register-prefix-optional", no_argument, NULL,
7526      OPTION_REGISTER_PREFIX_OPTIONAL},
7527 #define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7528   {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7529 #define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7530   {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7531 #define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7532   {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7533 #define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7534   {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7535 #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7536   {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
7537 #define OPTION_PCREL (OPTION_MD_BASE + 7)
7538   {"pcrel", no_argument, NULL, OPTION_PCREL},
7539   {NULL, no_argument, NULL, 0}
7540 };
7541 size_t md_longopts_size = sizeof (md_longopts);
7542 
7543 int
md_parse_option(int c,char * arg)7544 md_parse_option (int c, char *arg)
7545 {
7546   switch (c)
7547     {
7548     case 'l':			/* -l means keep external to 2 bit offset
7549 				   rather than 16 bit one.  */
7550       flag_short_refs = 1;
7551       break;
7552 
7553     case 'S':			/* -S means that jbsr's always turn into
7554 				   jsr's.  */
7555       flag_long_jumps = 1;
7556       break;
7557 
7558     case OPTION_PCREL:		/* --pcrel means never turn PC-relative
7559 				   branches into absolute jumps.  */
7560       flag_keep_pcrel = 1;
7561       break;
7562 
7563     case OPTION_PIC:
7564     case 'k':
7565       flag_want_pic = 1;
7566       break;			/* -pic, Position Independent Code.  */
7567 
7568     case OPTION_REGISTER_PREFIX_OPTIONAL:
7569       flag_reg_prefix_optional = 1;
7570       reg_prefix_optional_seen = 1;
7571       break;
7572 
7573       /* -V: SVR4 argument to print version ID.  */
7574     case 'V':
7575       print_version_id ();
7576       break;
7577 
7578       /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7579 	 should be emitted or not.  FIXME: Not implemented.  */
7580     case 'Q':
7581       break;
7582 
7583     case OPTION_BITWISE_OR:
7584       {
7585 	char *n, *t;
7586 	const char *s;
7587 
7588 	n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7589 	t = n;
7590 	for (s = m68k_comment_chars; *s != '\0'; s++)
7591 	  if (*s != '|')
7592 	    *t++ = *s;
7593 	*t = '\0';
7594 	m68k_comment_chars = n;
7595       }
7596       break;
7597 
7598     case OPTION_BASE_SIZE_DEFAULT_16:
7599       m68k_index_width_default = SIZE_WORD;
7600       break;
7601 
7602     case OPTION_BASE_SIZE_DEFAULT_32:
7603       m68k_index_width_default = SIZE_LONG;
7604       break;
7605 
7606     case OPTION_DISP_SIZE_DEFAULT_16:
7607       m68k_rel32 = 0;
7608       m68k_rel32_from_cmdline = 1;
7609       break;
7610 
7611     case OPTION_DISP_SIZE_DEFAULT_32:
7612       m68k_rel32 = 1;
7613       m68k_rel32_from_cmdline = 1;
7614       break;
7615 
7616     case 'A':
7617 #if WARN_DEPRECATED
7618       as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7619 		    arg, arg));
7620 #endif
7621       /* Intentional fall-through.  */
7622     case 'm':
7623       if (!strncmp (arg, "arch=", 5))
7624 	m68k_set_arch (arg + 5, 1, 0);
7625       else if (!strncmp (arg, "cpu=", 4))
7626 	m68k_set_cpu (arg + 4, 1, 0);
7627       else if (m68k_set_extension (arg, 0, 1))
7628 	;
7629       else if (m68k_set_arch (arg, 0, 1))
7630 	;
7631       else if (m68k_set_cpu (arg, 0, 1))
7632 	;
7633       else
7634 	return 0;
7635       break;
7636 
7637     default:
7638       return 0;
7639     }
7640 
7641   return 1;
7642 }
7643 
7644 /* Setup tables from the selected arch and/or cpu */
7645 
7646 static void
m68k_init_arch(void)7647 m68k_init_arch (void)
7648 {
7649   if (not_current_architecture & current_architecture)
7650     {
7651       as_bad (_("architecture features both enabled and disabled"));
7652       not_current_architecture &= ~current_architecture;
7653     }
7654   if (selected_arch)
7655     {
7656       current_architecture |= selected_arch->arch;
7657       control_regs = selected_arch->control_regs;
7658     }
7659   else
7660     current_architecture |= selected_cpu->arch;
7661 
7662   current_architecture &= ~not_current_architecture;
7663 
7664   if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7665     {
7666       /* Determine which float is really meant.  */
7667       if (current_architecture & (m68k_mask & ~m68881))
7668 	current_architecture ^= cfloat;
7669       else
7670 	current_architecture ^= m68881;
7671     }
7672 
7673   if (selected_cpu)
7674     {
7675       control_regs = selected_cpu->control_regs;
7676       if (current_architecture & ~selected_cpu->arch)
7677 	{
7678 	  as_bad (_("selected processor does not have all features of selected architecture"));
7679 	  current_architecture
7680 	    = selected_cpu->arch & ~not_current_architecture;
7681 	}
7682     }
7683 
7684   if ((current_architecture & m68k_mask)
7685       && (current_architecture & ~m68k_mask))
7686     {
7687       as_bad (_ ("m68k and cf features both selected"));
7688       if (current_architecture & m68k_mask)
7689 	current_architecture &= m68k_mask;
7690       else
7691 	current_architecture &= ~m68k_mask;
7692     }
7693 
7694   /* Permit m68881 specification with all cpus; those that can't work
7695      with a coprocessor could be doing emulation.  */
7696   if (current_architecture & m68851)
7697     {
7698       if (current_architecture & m68040)
7699 	as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7700     }
7701   /* What other incompatibilities could we check for?  */
7702 
7703   if (cpu_of_arch (current_architecture) < m68020
7704       || arch_coldfire_p (current_architecture))
7705     md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7706 
7707   initialized = 1;
7708 }
7709 
7710 void
md_show_usage(FILE * stream)7711 md_show_usage (FILE *stream)
7712 {
7713   const char *default_cpu = TARGET_CPU;
7714   int i;
7715 
7716   /* Get the canonical name for the default target CPU.  */
7717   if (*default_cpu == 'm')
7718     default_cpu++;
7719   for (i = 0; m68k_cpus[i].name; i++)
7720     {
7721       if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
7722 	{
7723 	  while (m68k_cpus[i].alias > 0)
7724 	    i--;
7725 	  while (m68k_cpus[i].alias < 0)
7726 	    i++;
7727 	  default_cpu = m68k_cpus[i].name;
7728 	}
7729     }
7730 
7731   fprintf (stream, _("\
7732 -march=<arch>		set architecture\n\
7733 -mcpu=<cpu>		set cpu [default %s]\n\
7734 "), default_cpu);
7735   for (i = 0; m68k_extensions[i].name; i++)
7736     fprintf (stream, _("\
7737 -m[no-]%-16s enable/disable%s architecture extension\n\
7738 "), m68k_extensions[i].name,
7739 	     m68k_extensions[i].alias > 0 ? " ColdFire"
7740 	     : m68k_extensions[i].alias < 0 ? " m68k" : "");
7741 
7742   fprintf (stream, _("\
7743 -l			use 1 word for refs to undefined symbols [default 2]\n\
7744 -pic, -k		generate position independent code\n\
7745 -S			turn jbsr into jsr\n\
7746 --pcrel                 never turn PC-relative branches into absolute jumps\n\
7747 --register-prefix-optional\n\
7748 			recognize register names without prefix character\n\
7749 --bitwise-or		do not treat `|' as a comment character\n\
7750 --base-size-default-16	base reg without size is 16 bits\n\
7751 --base-size-default-32	base reg without size is 32 bits (default)\n\
7752 --disp-size-default-16	displacement with unknown size is 16 bits\n\
7753 --disp-size-default-32	displacement with unknown size is 32 bits (default)\n\
7754 "));
7755 
7756   fprintf (stream, _("Architecture variants are: "));
7757   for (i = 0; m68k_archs[i].name; i++)
7758     {
7759       if (i)
7760 	fprintf (stream, " | ");
7761       fprintf (stream, "%s", m68k_archs[i].name);
7762     }
7763   fprintf (stream, "\n");
7764 
7765   fprintf (stream, _("Processor variants are: "));
7766   for (i = 0; m68k_cpus[i].name; i++)
7767     {
7768       if (i)
7769 	fprintf (stream, " | ");
7770       fprintf (stream, "%s", m68k_cpus[i].name);
7771     }
7772   fprintf (stream, _("\n"));
7773 }
7774 
7775 #ifdef TEST2
7776 
7777 /* TEST2:  Test md_assemble() */
7778 /* Warning, this routine probably doesn't work anymore.  */
7779 int
main(void)7780 main (void)
7781 {
7782   struct m68k_it the_ins;
7783   char buf[120];
7784   char *cp;
7785   int n;
7786 
7787   m68k_ip_begin ();
7788   for (;;)
7789     {
7790       if (!gets (buf) || !*buf)
7791 	break;
7792       if (buf[0] == '|' || buf[1] == '.')
7793 	continue;
7794       for (cp = buf; *cp; cp++)
7795 	if (*cp == '\t')
7796 	  *cp = ' ';
7797       if (is_label (buf))
7798 	continue;
7799       memset (&the_ins, '\0', sizeof (the_ins));
7800       m68k_ip (&the_ins, buf);
7801       if (the_ins.error)
7802 	{
7803 	  printf (_("Error %s in %s\n"), the_ins.error, buf);
7804 	}
7805       else
7806 	{
7807 	  printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7808 	  for (n = 0; n < the_ins.numo; n++)
7809 	    printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7810 	  printf ("    ");
7811 	  print_the_insn (&the_ins.opcode[0], stdout);
7812 	  (void) putchar ('\n');
7813 	}
7814       for (n = 0; n < strlen (the_ins.args) / 2; n++)
7815 	{
7816 	  if (the_ins.operands[n].error)
7817 	    {
7818 	      printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7819 	      continue;
7820 	    }
7821 	  printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7822 		  the_ins.operands[n].reg);
7823 	  if (the_ins.operands[n].b_const)
7824 	    printf ("Constant: '%.*s', ",
7825 		    1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7826 		    the_ins.operands[n].b_const);
7827 	  printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7828 		  the_ins.operands[n].isiz, the_ins.operands[n].imul);
7829 	  if (the_ins.operands[n].b_iadd)
7830 	    printf ("Iadd: '%.*s',",
7831 		    1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7832 		    the_ins.operands[n].b_iadd);
7833 	  putchar ('\n');
7834 	}
7835     }
7836   m68k_ip_end ();
7837   return 0;
7838 }
7839 
7840 int
is_label(char * str)7841 is_label (char *str)
7842 {
7843   while (*str == ' ')
7844     str++;
7845   while (*str && *str != ' ')
7846     str++;
7847   if (str[-1] == ':' || str[1] == '=')
7848     return 1;
7849   return 0;
7850 }
7851 
7852 #endif
7853 
7854 /* Possible states for relaxation:
7855 
7856    0 0	branch offset	byte	(bra, etc)
7857    0 1			word
7858    0 2			long
7859 
7860    1 0	indexed offsets	byte	a0@(32,d4:w:1) etc
7861    1 1			word
7862    1 2			long
7863 
7864    2 0	two-offset index word-word a0@(32,d4)@(45) etc
7865    2 1			word-long
7866    2 2			long-word
7867    2 3			long-long
7868 
7869    */
7870 
7871 /* We have no need to default values of symbols.  */
7872 
7873 symbolS *
md_undefined_symbol(char * name ATTRIBUTE_UNUSED)7874 md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
7875 {
7876   return 0;
7877 }
7878 
7879 /* Round up a section size to the appropriate boundary.  */
7880 valueT
md_section_align(segT segment ATTRIBUTE_UNUSED,valueT size)7881 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
7882 {
7883 #ifdef OBJ_AOUT
7884   /* For a.out, force the section size to be aligned.  If we don't do
7885      this, BFD will align it for us, but it will not write out the
7886      final bytes of the section.  This may be a bug in BFD, but it is
7887      easier to fix it here since that is how the other a.out targets
7888      work.  */
7889   int align;
7890 
7891   align = bfd_get_section_alignment (stdoutput, segment);
7892   size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7893 #endif
7894 
7895   return size;
7896 }
7897 
7898 /* Exactly what point is a PC-relative offset relative TO?
7899    On the 68k, it is relative to the address of the first extension
7900    word.  The difference between the addresses of the offset and the
7901    first extension word is stored in fx_pcrel_adjust.  */
7902 long
md_pcrel_from(fixS * fixP)7903 md_pcrel_from (fixS *fixP)
7904 {
7905   int adjust;
7906 
7907   adjust = fixP->fx_pcrel_adjust;
7908   if (adjust == 64)
7909     adjust = -1;
7910   return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7911 }
7912 
7913 #ifdef OBJ_ELF
7914 void
m68k_elf_final_processing(void)7915 m68k_elf_final_processing (void)
7916 {
7917   unsigned flags = 0;
7918 
7919   if (arch_coldfire_fpu (current_architecture))
7920     flags |= EF_M68K_CFV4E;
7921   /* Set file-specific flags if this is a cpu32 processor.  */
7922   if (cpu_of_arch (current_architecture) & cpu32)
7923     flags |= EF_M68K_CPU32;
7924   else if (cpu_of_arch (current_architecture) & fido_a)
7925     flags |= EF_M68K_FIDO;
7926   else if ((cpu_of_arch (current_architecture) & m68000up)
7927 	   && !(cpu_of_arch (current_architecture) & m68020up))
7928     flags |= EF_M68K_M68000;
7929 
7930   if (current_architecture & mcfisa_a)
7931     {
7932       static const unsigned isa_features[][2] =
7933       {
7934 	{EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
7935 	{EF_M68K_CF_ISA_A,	mcfisa_a|mcfhwdiv},
7936 	{EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7937 	{EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7938 	{EF_M68K_CF_ISA_B,	mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
7939 	{EF_M68K_CF_ISA_C,	mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
7940 	{EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
7941 	{0,0},
7942       };
7943       static const unsigned mac_features[][2] =
7944       {
7945 	{EF_M68K_CF_MAC, mcfmac},
7946 	{EF_M68K_CF_EMAC, mcfemac},
7947 	{0,0},
7948       };
7949       unsigned ix;
7950       unsigned pattern;
7951 
7952       pattern = (current_architecture
7953 		 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
7954       for (ix = 0; isa_features[ix][1]; ix++)
7955 	{
7956 	  if (pattern == isa_features[ix][1])
7957 	    {
7958 	      flags |= isa_features[ix][0];
7959 	      break;
7960 	    }
7961 	}
7962       if (!isa_features[ix][1])
7963 	{
7964 	cf_bad:
7965 	  as_warn (_("Not a defined coldfire architecture"));
7966 	}
7967       else
7968 	{
7969 	  if (current_architecture & cfloat)
7970 	    flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
7971 
7972 	  pattern = current_architecture & (mcfmac|mcfemac);
7973 	  if (pattern)
7974 	    {
7975 	      for (ix = 0; mac_features[ix][1]; ix++)
7976 		{
7977 		  if (pattern == mac_features[ix][1])
7978 		    {
7979 		      flags |= mac_features[ix][0];
7980 		      break;
7981 		    }
7982 		}
7983 	      if (!mac_features[ix][1])
7984 		goto cf_bad;
7985 	    }
7986 	}
7987     }
7988   elf_elfheader (stdoutput)->e_flags |= flags;
7989 }
7990 
7991 /* Parse @TLSLDO and return the desired relocation.  */
7992 static bfd_reloc_code_real_type
m68k_elf_suffix(char ** str_p,expressionS * exp_p)7993 m68k_elf_suffix (char **str_p, expressionS *exp_p)
7994 {
7995   char ident[20];
7996   char *str = *str_p;
7997   char *str2;
7998   int ch;
7999   int len;
8000 
8001   if (*str++ != '@')
8002     return BFD_RELOC_UNUSED;
8003 
8004   for (ch = *str, str2 = ident;
8005        (str2 < ident + sizeof (ident) - 1
8006 	&& (ISALNUM (ch) || ch == '@'));
8007        ch = *++str)
8008     {
8009       *str2++ = ch;
8010     }
8011 
8012   *str2 = '\0';
8013   len = str2 - ident;
8014 
8015   if (strncmp (ident, "TLSLDO", 6) == 0
8016       && len == 6)
8017     {
8018       /* Now check for identifier@suffix+constant.  */
8019       if (*str == '-' || *str == '+')
8020 	{
8021 	  char *orig_line = input_line_pointer;
8022 	  expressionS new_exp;
8023 
8024 	  input_line_pointer = str;
8025 	  expression (&new_exp);
8026 	  if (new_exp.X_op == O_constant)
8027 	    {
8028 	      exp_p->X_add_number += new_exp.X_add_number;
8029 	      str = input_line_pointer;
8030 	    }
8031 
8032 	  if (&input_line_pointer != str_p)
8033 	    input_line_pointer = orig_line;
8034 	}
8035       *str_p = str;
8036 
8037       return BFD_RELOC_68K_TLS_LDO32;
8038       }
8039 
8040   return BFD_RELOC_UNUSED;
8041 }
8042 
8043 /* Handles .long <tls_symbol>+0x8000 debug info.
8044    Clobbers input_line_pointer, checks end-of-line.
8045    Adapted from tc-ppc.c:ppc_elf_cons.  */
8046 static void
m68k_elf_cons(int nbytes)8047 m68k_elf_cons (int nbytes /* 4=.long */)
8048 {
8049   if (is_it_end_of_statement ())
8050     {
8051       demand_empty_rest_of_line ();
8052       return;
8053     }
8054 
8055   do
8056     {
8057       expressionS exp;
8058       bfd_reloc_code_real_type reloc;
8059 
8060       expression (&exp);
8061       if (exp.X_op == O_symbol
8062 	  && *input_line_pointer == '@'
8063 	  && (reloc = m68k_elf_suffix (&input_line_pointer,
8064 				      &exp)) != BFD_RELOC_UNUSED)
8065 	{
8066 	  reloc_howto_type *reloc_howto;
8067 	  int size;
8068 
8069 	  reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8070 	  size = bfd_get_reloc_size (reloc_howto);
8071 
8072 	  if (size > nbytes)
8073 	    {
8074 	      as_bad (_("%s relocations do not fit in %d bytes\n"),
8075 		      reloc_howto->name, nbytes);
8076 	    }
8077 	  else
8078 	    {
8079 	      char *p;
8080 	      int offset;
8081 
8082 	      p = frag_more (nbytes);
8083 	      offset = 0;
8084 	      if (target_big_endian)
8085 		offset = nbytes - size;
8086 	      fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8087 			   &exp, 0, reloc);
8088 	    }
8089 	}
8090       else
8091 	emit_expr (&exp, (unsigned int) nbytes);
8092     }
8093   while (*input_line_pointer++ == ',');
8094 
8095   /* Put terminator back into stream.  */
8096   input_line_pointer--;
8097   demand_empty_rest_of_line ();
8098 }
8099 #endif
8100 
8101 int
tc_m68k_regname_to_dw2regnum(char * regname)8102 tc_m68k_regname_to_dw2regnum (char *regname)
8103 {
8104   unsigned int regnum;
8105   static const char *const regnames[] =
8106     {
8107       "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8108       "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8109       "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8110       "pc"
8111     };
8112 
8113   for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8114     if (strcmp (regname, regnames[regnum]) == 0)
8115       return regnum;
8116 
8117   return -1;
8118 }
8119 
8120 void
tc_m68k_frame_initial_instructions(void)8121 tc_m68k_frame_initial_instructions (void)
8122 {
8123   static int sp_regno = -1;
8124 
8125   if (sp_regno < 0)
8126     sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8127 
8128   cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8129   cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8130 }
8131 
8132 /* Check and emit error if broken-word handling has failed to fix up a
8133    case-table.	This is called from write.c, after doing everything it
8134    knows about how to handle broken words.  */
8135 
8136 void
tc_m68k_check_adjusted_broken_word(offsetT new_offset,struct broken_word * brokwP)8137 tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
8138 {
8139   if (new_offset > 32767 || new_offset < -32768)
8140     as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
8141 		  _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
8142 		  (long) new_offset);
8143 }
8144 
8145