1 /* 2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. 3 4 The Weather Channel (TM) funded Tungsten Graphics to develop the 5 initial release of the Radeon 8500 driver under the XFree86 license. 6 This notice must be preserved. 7 8 Permission is hereby granted, free of charge, to any person obtaining 9 a copy of this software and associated documentation files (the 10 "Software"), to deal in the Software without restriction, including 11 without limitation the rights to use, copy, modify, merge, publish, 12 distribute, sublicense, and/or sell copies of the Software, and to 13 permit persons to whom the Software is furnished to do so, subject to 14 the following conditions: 15 16 The above copyright notice and this permission notice (including the 17 next paragraph) shall be included in all copies or substantial 18 portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 27 28 **************************************************************************/ 29 30 /* 31 * Authors: 32 * Keith Whitwell <keith@tungstengraphics.com> 33 */ 34 35 #ifndef __R200_CONTEXT_H__ 36 #define __R200_CONTEXT_H__ 37 38 #include "tnl/t_vertex.h" 39 #include "drm.h" 40 #include "radeon_drm.h" 41 #include "dri_util.h" 42 43 #include "main/macros.h" 44 #include "main/mtypes.h" 45 #include "main/colormac.h" 46 #include "r200_reg.h" 47 #include "r200_vertprog.h" 48 49 #ifndef R200_EMIT_VAP_PVS_CNTL 50 #error This driver requires a newer libdrm to compile 51 #endif 52 53 #include "radeon_screen.h" 54 #include "radeon_common.h" 55 56 struct r200_context; 57 typedef struct r200_context r200ContextRec; 58 typedef struct r200_context *r200ContextPtr; 59 60 #include "main/mm.h" 61 62 struct r200_vertex_program { 63 struct gl_vertex_program mesa_program; /* Must be first */ 64 int translated; 65 /* need excess instr: 1 for late loop checking, 2 for 66 additional instr due to instr/attr, 3 for fog */ 67 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6]; 68 int pos_end; 69 int inputs[VERT_ATTRIB_MAX]; 70 GLubyte inputmap_rev[16]; 71 int native; 72 int fogpidx; 73 int fogmode; 74 }; 75 76 #define R200_TEX_ALL 0x3f 77 78 79 struct r200_texture_env_state { 80 radeonTexObjPtr texobj; 81 GLuint outputreg; 82 GLuint unitneeded; 83 }; 84 85 #define R200_MAX_TEXTURE_UNITS 6 86 87 struct r200_texture_state { 88 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS]; 89 }; 90 91 92 /* Trying to keep these relatively short as the variables are becoming 93 * extravagently long. Drop the driver name prefix off the front of 94 * everything - I think we know which driver we're in by now, and keep the 95 * prefix to 3 letters unless absolutely impossible. 96 */ 97 98 #define CTX_CMD_0 0 99 #define CTX_PP_MISC 1 100 #define CTX_PP_FOG_COLOR 2 101 #define CTX_RE_SOLID_COLOR 3 102 #define CTX_RB3D_BLENDCNTL 4 103 #define CTX_RB3D_DEPTHOFFSET 5 104 #define CTX_RB3D_DEPTHPITCH 6 105 #define CTX_RB3D_ZSTENCILCNTL 7 106 #define CTX_CMD_1 8 107 #define CTX_PP_CNTL 9 108 #define CTX_RB3D_CNTL 10 109 #define CTX_RB3D_COLOROFFSET 11 110 #define CTX_CMD_2 12 /* why */ 111 #define CTX_RB3D_COLORPITCH 13 /* why */ 112 #define CTX_STATE_SIZE_OLDDRM 14 113 #define CTX_CMD_3 14 114 #define CTX_RB3D_BLENDCOLOR 15 115 #define CTX_RB3D_ABLENDCNTL 16 116 #define CTX_RB3D_CBLENDCNTL 17 117 #define CTX_STATE_SIZE_NEWDRM 18 118 119 #define SET_CMD_0 0 120 #define SET_SE_CNTL 1 121 #define SET_RE_CNTL 2 /* replace se_coord_fmt */ 122 #define SET_STATE_SIZE 3 123 124 #define VTE_CMD_0 0 125 #define VTE_SE_VTE_CNTL 1 126 #define VTE_STATE_SIZE 2 127 128 #define LIN_CMD_0 0 129 #define LIN_RE_LINE_PATTERN 1 130 #define LIN_RE_LINE_STATE 2 131 #define LIN_CMD_1 3 132 #define LIN_SE_LINE_WIDTH 4 133 #define LIN_STATE_SIZE 5 134 135 #define MSK_CMD_0 0 136 #define MSK_RB3D_STENCILREFMASK 1 137 #define MSK_RB3D_ROPCNTL 2 138 #define MSK_RB3D_PLANEMASK 3 139 #define MSK_STATE_SIZE 4 140 141 #define VPT_CMD_0 0 142 #define VPT_SE_VPORT_XSCALE 1 143 #define VPT_SE_VPORT_XOFFSET 2 144 #define VPT_SE_VPORT_YSCALE 3 145 #define VPT_SE_VPORT_YOFFSET 4 146 #define VPT_SE_VPORT_ZSCALE 5 147 #define VPT_SE_VPORT_ZOFFSET 6 148 #define VPT_STATE_SIZE 7 149 150 #define ZBS_CMD_0 0 151 #define ZBS_SE_ZBIAS_FACTOR 1 152 #define ZBS_SE_ZBIAS_CONSTANT 2 153 #define ZBS_STATE_SIZE 3 154 155 #define MSC_CMD_0 0 156 #define MSC_RE_MISC 1 157 #define MSC_STATE_SIZE 2 158 159 #define TAM_CMD_0 0 160 #define TAM_DEBUG3 1 161 #define TAM_STATE_SIZE 2 162 163 #define TEX_CMD_0 0 164 #define TEX_PP_TXFILTER 1 /*2c00*/ 165 #define TEX_PP_TXFORMAT 2 /*2c04*/ 166 #define TEX_PP_TXFORMAT_X 3 /*2c08*/ 167 #define TEX_PP_TXSIZE 4 /*2c0c*/ 168 #define TEX_PP_TXPITCH 5 /*2c10*/ 169 #define TEX_PP_BORDER_COLOR 6 /*2c14*/ 170 #define TEX_CMD_1_OLDDRM 7 171 #define TEX_PP_TXOFFSET_OLDDRM 8 /*2d00 */ 172 #define TEX_STATE_SIZE_OLDDRM 9 173 #define TEX_PP_CUBIC_FACES 7 174 #define TEX_PP_TXMULTI_CTL 8 175 #define TEX_CMD_1_NEWDRM 9 176 #define TEX_PP_TXOFFSET_NEWDRM 10 177 #define TEX_STATE_SIZE_NEWDRM 11 178 179 #define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */ 180 #define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */ 181 #define CUBE_CMD_1 2 /* 5 registers follow */ 182 #define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */ 183 #define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */ 184 #define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */ 185 #define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */ 186 #define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */ 187 #define CUBE_STATE_SIZE 8 188 189 #define PIX_CMD_0 0 190 #define PIX_PP_TXCBLEND 1 191 #define PIX_PP_TXCBLEND2 2 192 #define PIX_PP_TXABLEND 3 193 #define PIX_PP_TXABLEND2 4 194 #define PIX_STATE_SIZE 5 195 196 #define TF_CMD_0 0 197 #define TF_TFACTOR_0 1 198 #define TF_TFACTOR_1 2 199 #define TF_TFACTOR_2 3 200 #define TF_TFACTOR_3 4 201 #define TF_TFACTOR_4 5 202 #define TF_TFACTOR_5 6 203 #define TF_STATE_SIZE 7 204 205 #define ATF_CMD_0 0 206 #define ATF_TFACTOR_0 1 207 #define ATF_TFACTOR_1 2 208 #define ATF_TFACTOR_2 3 209 #define ATF_TFACTOR_3 4 210 #define ATF_TFACTOR_4 5 211 #define ATF_TFACTOR_5 6 212 #define ATF_TFACTOR_6 7 213 #define ATF_TFACTOR_7 8 214 #define ATF_STATE_SIZE 9 215 216 /* ATI_FRAGMENT_SHADER */ 217 #define AFS_CMD_0 0 218 #define AFS_IC0 1 /* 2f00 */ 219 #define AFS_IC1 2 /* 2f04 */ 220 #define AFS_IA0 3 /* 2f08 */ 221 #define AFS_IA1 4 /* 2f0c */ 222 #define AFS_STATE_SIZE 33 223 224 #define PVS_CMD_0 0 225 #define PVS_CNTL_1 1 226 #define PVS_CNTL_2 2 227 #define PVS_STATE_SIZE 3 228 229 /* those are quite big... */ 230 #define VPI_CMD_0 0 231 #define VPI_OPDST_0 1 232 #define VPI_SRC0_0 2 233 #define VPI_SRC1_0 3 234 #define VPI_SRC2_0 4 235 #define VPI_OPDST_63 253 236 #define VPI_SRC0_63 254 237 #define VPI_SRC1_63 255 238 #define VPI_SRC2_63 256 239 #define VPI_STATE_SIZE 257 240 241 #define VPP_CMD_0 0 242 #define VPP_PARAM0_0 1 243 #define VPP_PARAM1_0 2 244 #define VPP_PARAM2_0 3 245 #define VPP_PARAM3_0 4 246 #define VPP_PARAM0_95 381 247 #define VPP_PARAM1_95 382 248 #define VPP_PARAM2_95 383 249 #define VPP_PARAM3_95 384 250 #define VPP_STATE_SIZE 385 251 252 #define TCL_CMD_0 0 253 #define TCL_LIGHT_MODEL_CTL_0 1 254 #define TCL_LIGHT_MODEL_CTL_1 2 255 #define TCL_PER_LIGHT_CTL_0 3 256 #define TCL_PER_LIGHT_CTL_1 4 257 #define TCL_PER_LIGHT_CTL_2 5 258 #define TCL_PER_LIGHT_CTL_3 6 259 #define TCL_CMD_1 7 260 #define TCL_UCP_VERT_BLEND_CTL 8 261 #define TCL_STATE_SIZE 9 262 263 #define MSL_CMD_0 0 264 #define MSL_MATRIX_SELECT_0 1 265 #define MSL_MATRIX_SELECT_1 2 266 #define MSL_MATRIX_SELECT_2 3 267 #define MSL_MATRIX_SELECT_3 4 268 #define MSL_MATRIX_SELECT_4 5 269 #define MSL_STATE_SIZE 6 270 271 #define TCG_CMD_0 0 272 #define TCG_TEX_PROC_CTL_2 1 273 #define TCG_TEX_PROC_CTL_3 2 274 #define TCG_TEX_PROC_CTL_0 3 275 #define TCG_TEX_PROC_CTL_1 4 276 #define TCG_TEX_CYL_WRAP_CTL 5 277 #define TCG_STATE_SIZE 6 278 279 #define MTL_CMD_0 0 280 #define MTL_EMMISSIVE_RED 1 281 #define MTL_EMMISSIVE_GREEN 2 282 #define MTL_EMMISSIVE_BLUE 3 283 #define MTL_EMMISSIVE_ALPHA 4 284 #define MTL_AMBIENT_RED 5 285 #define MTL_AMBIENT_GREEN 6 286 #define MTL_AMBIENT_BLUE 7 287 #define MTL_AMBIENT_ALPHA 8 288 #define MTL_DIFFUSE_RED 9 289 #define MTL_DIFFUSE_GREEN 10 290 #define MTL_DIFFUSE_BLUE 11 291 #define MTL_DIFFUSE_ALPHA 12 292 #define MTL_SPECULAR_RED 13 293 #define MTL_SPECULAR_GREEN 14 294 #define MTL_SPECULAR_BLUE 15 295 #define MTL_SPECULAR_ALPHA 16 296 #define MTL_CMD_1 17 297 #define MTL_SHININESS 18 298 #define MTL_STATE_SIZE 19 299 300 #define VAP_CMD_0 0 301 #define VAP_SE_VAP_CNTL 1 302 #define VAP_STATE_SIZE 2 303 304 /* Replaces a lot of packet info from radeon 305 */ 306 #define VTX_CMD_0 0 307 #define VTX_VTXFMT_0 1 308 #define VTX_VTXFMT_1 2 309 #define VTX_TCL_OUTPUT_VTXFMT_0 3 310 #define VTX_TCL_OUTPUT_VTXFMT_1 4 311 #define VTX_CMD_1 5 312 #define VTX_TCL_OUTPUT_COMPSEL 6 313 #define VTX_CMD_2 7 314 #define VTX_STATE_CNTL 8 315 #define VTX_STATE_SIZE 9 316 317 /* SPR - point sprite state 318 */ 319 #define SPR_CMD_0 0 320 #define SPR_POINT_SPRITE_CNTL 1 321 #define SPR_STATE_SIZE 2 322 323 #define PTP_CMD_0 0 324 #define PTP_VPORT_SCALE_0 1 325 #define PTP_VPORT_SCALE_1 2 326 #define PTP_VPORT_SCALE_PTSIZE 3 327 #define PTP_VPORT_SCALE_3 4 328 #define PTP_CMD_1 5 329 #define PTP_ATT_CONST_QUAD 6 330 #define PTP_ATT_CONST_LIN 7 331 #define PTP_ATT_CONST_CON 8 332 #define PTP_ATT_CONST_3 9 333 #define PTP_EYE_X 10 334 #define PTP_EYE_Y 11 335 #define PTP_EYE_Z 12 336 #define PTP_EYE_3 13 337 #define PTP_CLAMP_MIN 14 338 #define PTP_CLAMP_MAX 15 339 #define PTP_CLAMP_2 16 340 #define PTP_CLAMP_3 17 341 #define PTP_STATE_SIZE 18 342 343 #define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\ 344 R200_VTX_COLOR_MASK) 345 346 /** 347 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine 348 * how many components are in texture coordinate \c n. 349 */ 350 #define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07) 351 352 #define MAT_CMD_0 0 353 #define MAT_ELT_0 1 354 #define MAT_STATE_SIZE 17 355 356 #define GRD_CMD_0 0 357 #define GRD_VERT_GUARD_CLIP_ADJ 1 358 #define GRD_VERT_GUARD_DISCARD_ADJ 2 359 #define GRD_HORZ_GUARD_CLIP_ADJ 3 360 #define GRD_HORZ_GUARD_DISCARD_ADJ 4 361 #define GRD_STATE_SIZE 5 362 363 /* position changes frequently when lighting in modelpos - separate 364 * out to new state item? 365 */ 366 #define LIT_CMD_0 0 367 #define LIT_AMBIENT_RED 1 368 #define LIT_AMBIENT_GREEN 2 369 #define LIT_AMBIENT_BLUE 3 370 #define LIT_AMBIENT_ALPHA 4 371 #define LIT_DIFFUSE_RED 5 372 #define LIT_DIFFUSE_GREEN 6 373 #define LIT_DIFFUSE_BLUE 7 374 #define LIT_DIFFUSE_ALPHA 8 375 #define LIT_SPECULAR_RED 9 376 #define LIT_SPECULAR_GREEN 10 377 #define LIT_SPECULAR_BLUE 11 378 #define LIT_SPECULAR_ALPHA 12 379 #define LIT_POSITION_X 13 380 #define LIT_POSITION_Y 14 381 #define LIT_POSITION_Z 15 382 #define LIT_POSITION_W 16 383 #define LIT_DIRECTION_X 17 384 #define LIT_DIRECTION_Y 18 385 #define LIT_DIRECTION_Z 19 386 #define LIT_DIRECTION_W 20 387 #define LIT_ATTEN_QUADRATIC 21 388 #define LIT_ATTEN_LINEAR 22 389 #define LIT_ATTEN_CONST 23 390 #define LIT_ATTEN_XXX 24 391 #define LIT_CMD_1 25 392 #define LIT_SPOT_DCD 26 393 #define LIT_SPOT_DCM 27 394 #define LIT_SPOT_EXPONENT 28 395 #define LIT_SPOT_CUTOFF 29 396 #define LIT_SPECULAR_THRESH 30 397 #define LIT_RANGE_CUTOFF 31 /* ? */ 398 #define LIT_ATTEN_CONST_INV 32 399 #define LIT_STATE_SIZE 33 400 401 /* Fog 402 */ 403 #define FOG_CMD_0 0 404 #define FOG_R 1 405 #define FOG_C 2 406 #define FOG_D 3 407 #define FOG_PAD 4 408 #define FOG_STATE_SIZE 5 409 410 /* UCP 411 */ 412 #define UCP_CMD_0 0 413 #define UCP_X 1 414 #define UCP_Y 2 415 #define UCP_Z 3 416 #define UCP_W 4 417 #define UCP_STATE_SIZE 5 418 419 /* GLT - Global ambient 420 */ 421 #define GLT_CMD_0 0 422 #define GLT_RED 1 423 #define GLT_GREEN 2 424 #define GLT_BLUE 3 425 #define GLT_ALPHA 4 426 #define GLT_STATE_SIZE 5 427 428 /* EYE 429 */ 430 #define EYE_CMD_0 0 431 #define EYE_X 1 432 #define EYE_Y 2 433 #define EYE_Z 3 434 #define EYE_RESCALE_FACTOR 4 435 #define EYE_STATE_SIZE 5 436 437 /* CST - constant state 438 */ 439 #define CST_CMD_0 0 440 #define CST_PP_CNTL_X 1 441 #define CST_CMD_1 2 442 #define CST_RB3D_DEPTHXY_OFFSET 3 443 #define CST_CMD_2 4 444 #define CST_RE_AUX_SCISSOR_CNTL 5 445 #define CST_CMD_4 6 446 #define CST_SE_VAP_CNTL_STATUS 7 447 #define CST_CMD_5 8 448 #define CST_RE_POINTSIZE 9 449 #define CST_CMD_6 10 450 #define CST_SE_TCL_INPUT_VTX_0 11 451 #define CST_SE_TCL_INPUT_VTX_1 12 452 #define CST_SE_TCL_INPUT_VTX_2 13 453 #define CST_SE_TCL_INPUT_VTX_3 14 454 #define CST_STATE_SIZE 15 455 456 #define PRF_CMD_0 0 457 #define PRF_PP_TRI_PERF 1 458 #define PRF_PP_PERF_CNTL 2 459 #define PRF_STATE_SIZE 3 460 461 462 #define SCI_CMD_1 0 463 #define SCI_XY_1 1 464 #define SCI_CMD_2 2 465 #define SCI_XY_2 3 466 #define SCI_STATE_SIZE 4 467 468 #define R200_QUERYOBJ_CMD_0 0 469 #define R200_QUERYOBJ_DATA_0 1 470 #define R200_QUERYOBJ_CMDSIZE 2 471 472 #define STP_CMD_0 0 473 #define STP_DATA_0 1 474 #define STP_CMD_1 2 475 #define STP_STATE_SIZE 35 476 477 struct r200_hw_state { 478 /* Hardware state, stored as cmdbuf commands: 479 * -- Need to doublebuffer for 480 * - reviving state after loss of context 481 * - eliding noop statechange loops? (except line stipple count) 482 */ 483 struct radeon_state_atom ctx; 484 struct radeon_state_atom set; 485 struct radeon_state_atom sci; 486 struct radeon_state_atom vte; 487 struct radeon_state_atom lin; 488 struct radeon_state_atom msk; 489 struct radeon_state_atom vpt; 490 struct radeon_state_atom vap; 491 struct radeon_state_atom vtx; 492 struct radeon_state_atom tcl; 493 struct radeon_state_atom msl; 494 struct radeon_state_atom tcg; 495 struct radeon_state_atom msc; 496 struct radeon_state_atom cst; 497 struct radeon_state_atom tam; 498 struct radeon_state_atom tf; 499 struct radeon_state_atom tex[6]; 500 struct radeon_state_atom cube[6]; 501 struct radeon_state_atom zbs; 502 struct radeon_state_atom mtl[2]; 503 struct radeon_state_atom mat[9]; 504 struct radeon_state_atom lit[8]; /* includes vec, scl commands */ 505 struct radeon_state_atom ucp[6]; 506 struct radeon_state_atom pix[6]; /* pixshader stages */ 507 struct radeon_state_atom eye; /* eye pos */ 508 struct radeon_state_atom grd; /* guard band clipping */ 509 struct radeon_state_atom fog; 510 struct radeon_state_atom glt; 511 struct radeon_state_atom prf; 512 struct radeon_state_atom afs[2]; 513 struct radeon_state_atom pvs; 514 struct radeon_state_atom vpi[2]; 515 struct radeon_state_atom vpp[2]; 516 struct radeon_state_atom atf; 517 struct radeon_state_atom spr; 518 struct radeon_state_atom ptp; 519 struct radeon_state_atom stp; 520 }; 521 522 struct r200_state { 523 /* Derived state for internal purposes: 524 */ 525 struct r200_texture_state texture; 526 GLuint envneeded; 527 }; 528 529 #define R200_CMD_BUF_SZ (16*1024) 530 531 #define R200_ELT_BUF_SZ (16*1024) 532 /* r200_tcl.c 533 */ 534 struct r200_tcl_info { 535 GLuint hw_primitive; 536 537 int elt_used; 538 539 }; 540 541 542 /* r200_swtcl.c 543 */ 544 struct r200_swtcl_info { 545 546 547 radeon_point_func draw_point; 548 radeon_line_func draw_line; 549 radeon_tri_func draw_tri; 550 551 /** 552 * Offset of the 4UB color data within a hardware (swtcl) vertex. 553 */ 554 GLuint coloroffset; 555 556 /** 557 * Offset of the 3UB specular color data within a hardware (swtcl) vertex. 558 */ 559 GLuint specoffset; 560 561 /** 562 * Should Mesa project vertex data or will the hardware do it? 563 */ 564 GLboolean needproj; 565 }; 566 567 568 569 570 /* A maximum total of 29 elements per vertex: 3 floats for position, 3 571 * floats for normal, 4 floats for color, 4 bytes for secondary color, 572 * 3 floats for each texture unit (18 floats total). 573 * 574 * we maybe need add. 4 to prevent segfault if someone specifies 575 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: ) 576 * 577 * The position data is never actually stored here, so 3 elements could be 578 * trimmed out of the buffer. 579 */ 580 581 #define R200_MAX_VERTEX_SIZE ((3*6)+11) 582 583 struct r200_context { 584 struct radeon_context radeon; 585 586 /* Driver and hardware state management 587 */ 588 struct r200_hw_state hw; 589 struct r200_state state; 590 struct r200_vertex_program *curr_vp_hw; 591 592 /* Vertex buffers 593 */ 594 struct radeon_ioctl ioctl; 595 struct radeon_store store; 596 597 /* Clientdata textures; 598 */ 599 GLuint prefer_gart_client_texturing; 600 601 /* TCL stuff 602 */ 603 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS]; 604 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS]; 605 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS]; 606 GLuint TexMatEnabled; 607 GLuint TexMatCompSel; 608 GLuint TexGenEnabled; 609 GLuint TexGenCompSel; 610 GLmatrix tmpmat; 611 612 /* r200_tcl.c 613 */ 614 struct r200_tcl_info tcl; 615 616 /* r200_swtcl.c 617 */ 618 struct r200_swtcl_info swtcl; 619 620 GLboolean using_hyperz; 621 GLboolean texmicrotile; 622 623 struct ati_fragment_shader *afs_loaded; 624 }; 625 626 #define R200_CONTEXT(ctx) ((r200ContextPtr)(ctx->DriverCtx)) 627 628 629 extern void r200DestroyContext( __DRIcontext *driContextPriv ); 630 extern GLboolean r200CreateContext( gl_api api, 631 const struct gl_config *glVisual, 632 __DRIcontext *driContextPriv, 633 unsigned major_version, 634 unsigned minor_version, 635 uint32_t flags, 636 unsigned *error, 637 void *sharedContextPrivate); 638 extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv, 639 __DRIdrawable *driDrawPriv, 640 __DRIdrawable *driReadPriv ); 641 extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv ); 642 643 extern void r200_init_texcopy_functions(struct dd_function_table *table); 644 645 /* ================================================================ 646 * Debugging: 647 */ 648 649 #define R200_DEBUG RADEON_DEBUG 650 651 652 653 #endif /* __R200_CONTEXT_H__ */ 654