1 /* AArch64-specific support for ELF.
2    Copyright (C) 2009-2014 Free Software Foundation, Inc.
3    Contributed by ARM Ltd.
4 
5    This file is part of BFD, the Binary File Descriptor library.
6 
7    This program is free software; you can redistribute it and/or modify
8    it under the terms of the GNU General Public License as published by
9    the Free Software Foundation; either version 3 of the License, or
10    (at your option) any later version.
11 
12    This program is distributed in the hope that it will be useful,
13    but WITHOUT ANY WARRANTY; without even the implied warranty of
14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15    GNU General Public License for more details.
16 
17    You should have received a copy of the GNU General Public License
18    along with this program; see the file COPYING3. If not,
19    see <http://www.gnu.org/licenses/>.  */
20 
21 #include "sysdep.h"
22 #include "elfxx-aarch64.h"
23 #include <stdarg.h>
24 #include <string.h>
25 
26 #define MASK(n) ((1u << (n)) - 1)
27 
28 /* Sign-extend VALUE, which has the indicated number of BITS.  */
29 
30 bfd_signed_vma
_bfd_aarch64_sign_extend(bfd_vma value,int bits)31 _bfd_aarch64_sign_extend (bfd_vma value, int bits)
32 {
33   if (value & ((bfd_vma) 1 << (bits - 1)))
34     /* VALUE is negative.  */
35     value |= ((bfd_vma) - 1) << bits;
36 
37   return value;
38 }
39 
40 /* Decode the IMM field of ADRP.  */
41 
42 uint32_t
_bfd_aarch64_decode_adrp_imm(uint32_t insn)43 _bfd_aarch64_decode_adrp_imm (uint32_t insn)
44 {
45   return (((insn >> 5) & MASK (19)) << 2) | ((insn >> 29) & MASK (2));
46 }
47 
48 /* Reencode the imm field of add immediate.  */
49 static inline uint32_t
reencode_add_imm(uint32_t insn,uint32_t imm)50 reencode_add_imm (uint32_t insn, uint32_t imm)
51 {
52   return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
53 }
54 
55 /* Reencode the IMM field of ADR.  */
56 
57 uint32_t
_bfd_aarch64_reencode_adr_imm(uint32_t insn,uint32_t imm)58 _bfd_aarch64_reencode_adr_imm (uint32_t insn, uint32_t imm)
59 {
60   return (insn & ~((MASK (2) << 29) | (MASK (19) << 5)))
61     | ((imm & MASK (2)) << 29) | ((imm & (MASK (19) << 2)) << 3);
62 }
63 
64 /* Reencode the imm field of ld/st pos immediate.  */
65 static inline uint32_t
reencode_ldst_pos_imm(uint32_t insn,uint32_t imm)66 reencode_ldst_pos_imm (uint32_t insn, uint32_t imm)
67 {
68   return (insn & ~(MASK (12) << 10)) | ((imm & MASK (12)) << 10);
69 }
70 
71 /* Encode the 26-bit offset of unconditional branch.  */
72 static inline uint32_t
reencode_branch_ofs_26(uint32_t insn,uint32_t ofs)73 reencode_branch_ofs_26 (uint32_t insn, uint32_t ofs)
74 {
75   return (insn & ~MASK (26)) | (ofs & MASK (26));
76 }
77 
78 /* Encode the 19-bit offset of conditional branch and compare & branch.  */
79 static inline uint32_t
reencode_cond_branch_ofs_19(uint32_t insn,uint32_t ofs)80 reencode_cond_branch_ofs_19 (uint32_t insn, uint32_t ofs)
81 {
82   return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
83 }
84 
85 /* Decode the 19-bit offset of load literal.  */
86 static inline uint32_t
reencode_ld_lit_ofs_19(uint32_t insn,uint32_t ofs)87 reencode_ld_lit_ofs_19 (uint32_t insn, uint32_t ofs)
88 {
89   return (insn & ~(MASK (19) << 5)) | ((ofs & MASK (19)) << 5);
90 }
91 
92 /* Encode the 14-bit offset of test & branch.  */
93 static inline uint32_t
reencode_tst_branch_ofs_14(uint32_t insn,uint32_t ofs)94 reencode_tst_branch_ofs_14 (uint32_t insn, uint32_t ofs)
95 {
96   return (insn & ~(MASK (14) << 5)) | ((ofs & MASK (14)) << 5);
97 }
98 
99 /* Reencode the imm field of move wide.  */
100 static inline uint32_t
reencode_movw_imm(uint32_t insn,uint32_t imm)101 reencode_movw_imm (uint32_t insn, uint32_t imm)
102 {
103   return (insn & ~(MASK (16) << 5)) | ((imm & MASK (16)) << 5);
104 }
105 
106 /* Reencode mov[zn] to movz.  */
107 static inline uint32_t
reencode_movzn_to_movz(uint32_t opcode)108 reencode_movzn_to_movz (uint32_t opcode)
109 {
110   return opcode | (1 << 30);
111 }
112 
113 /* Reencode mov[zn] to movn.  */
114 static inline uint32_t
reencode_movzn_to_movn(uint32_t opcode)115 reencode_movzn_to_movn (uint32_t opcode)
116 {
117   return opcode & ~(1 << 30);
118 }
119 
120 /* Return non-zero if the indicated VALUE has overflowed the maximum
121    range expressible by a unsigned number with the indicated number of
122    BITS.  */
123 
124 static bfd_reloc_status_type
aarch64_unsigned_overflow(bfd_vma value,unsigned int bits)125 aarch64_unsigned_overflow (bfd_vma value, unsigned int bits)
126 {
127   bfd_vma lim;
128   if (bits >= sizeof (bfd_vma) * 8)
129     return bfd_reloc_ok;
130   lim = (bfd_vma) 1 << bits;
131   if (value >= lim)
132     return bfd_reloc_overflow;
133   return bfd_reloc_ok;
134 }
135 
136 /* Return non-zero if the indicated VALUE has overflowed the maximum
137    range expressible by an signed number with the indicated number of
138    BITS.  */
139 
140 static bfd_reloc_status_type
aarch64_signed_overflow(bfd_vma value,unsigned int bits)141 aarch64_signed_overflow (bfd_vma value, unsigned int bits)
142 {
143   bfd_signed_vma svalue = (bfd_signed_vma) value;
144   bfd_signed_vma lim;
145 
146   if (bits >= sizeof (bfd_vma) * 8)
147     return bfd_reloc_ok;
148   lim = (bfd_signed_vma) 1 << (bits - 1);
149   if (svalue < -lim || svalue >= lim)
150     return bfd_reloc_overflow;
151   return bfd_reloc_ok;
152 }
153 
154 /* Insert the addend/value into the instruction or data object being
155    relocated.  */
156 bfd_reloc_status_type
_bfd_aarch64_elf_put_addend(bfd * abfd,bfd_byte * address,bfd_reloc_code_real_type r_type,reloc_howto_type * howto,bfd_signed_vma addend)157 _bfd_aarch64_elf_put_addend (bfd *abfd,
158 			     bfd_byte *address, bfd_reloc_code_real_type r_type,
159 			     reloc_howto_type *howto, bfd_signed_vma addend)
160 {
161   bfd_reloc_status_type status = bfd_reloc_ok;
162   bfd_signed_vma old_addend = addend;
163   bfd_vma contents;
164   int size;
165 
166   size = bfd_get_reloc_size (howto);
167   switch (size)
168     {
169     case 2:
170       contents = bfd_get_16 (abfd, address);
171       break;
172     case 4:
173       if (howto->src_mask != 0xffffffff)
174 	/* Must be 32-bit instruction, always little-endian.  */
175 	contents = bfd_getl32 (address);
176       else
177 	/* Must be 32-bit data (endianness dependent).  */
178 	contents = bfd_get_32 (abfd, address);
179       break;
180     case 8:
181       contents = bfd_get_64 (abfd, address);
182       break;
183     default:
184       abort ();
185     }
186 
187   switch (howto->complain_on_overflow)
188     {
189     case complain_overflow_dont:
190       break;
191     case complain_overflow_signed:
192       status = aarch64_signed_overflow (addend,
193 					howto->bitsize + howto->rightshift);
194       break;
195     case complain_overflow_unsigned:
196       status = aarch64_unsigned_overflow (addend,
197 					  howto->bitsize + howto->rightshift);
198       break;
199     case complain_overflow_bitfield:
200     default:
201       abort ();
202     }
203 
204   addend >>= howto->rightshift;
205 
206   switch (r_type)
207     {
208     case BFD_RELOC_AARCH64_JUMP26:
209     case BFD_RELOC_AARCH64_CALL26:
210       contents = reencode_branch_ofs_26 (contents, addend);
211       break;
212 
213     case BFD_RELOC_AARCH64_BRANCH19:
214       contents = reencode_cond_branch_ofs_19 (contents, addend);
215       break;
216 
217     case BFD_RELOC_AARCH64_TSTBR14:
218       contents = reencode_tst_branch_ofs_14 (contents, addend);
219       break;
220 
221     case BFD_RELOC_AARCH64_LD_LO19_PCREL:
222     case BFD_RELOC_AARCH64_GOT_LD_PREL19:
223       if (old_addend & ((1 << howto->rightshift) - 1))
224 	return bfd_reloc_overflow;
225       contents = reencode_ld_lit_ofs_19 (contents, addend);
226       break;
227 
228     case BFD_RELOC_AARCH64_TLSDESC_CALL:
229       break;
230 
231     case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
232     case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
233     case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
234     case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
235     case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
236     case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
237     case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
238       contents = _bfd_aarch64_reencode_adr_imm (contents, addend);
239       break;
240 
241     case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
242     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
243     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
244     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
245     case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
246     case BFD_RELOC_AARCH64_ADD_LO12:
247       /* Corresponds to: add rd, rn, #uimm12 to provide the low order
248          12 bits of the page offset following
249          BFD_RELOC_AARCH64_ADR_HI21_PCREL which computes the
250          (pc-relative) page base.  */
251       contents = reencode_add_imm (contents, addend);
252       break;
253 
254     case BFD_RELOC_AARCH64_LDST8_LO12:
255     case BFD_RELOC_AARCH64_LDST16_LO12:
256     case BFD_RELOC_AARCH64_LDST32_LO12:
257     case BFD_RELOC_AARCH64_LDST64_LO12:
258     case BFD_RELOC_AARCH64_LDST128_LO12:
259     case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
260     case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
261     case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
262     case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
263     case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
264     case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
265       if (old_addend & ((1 << howto->rightshift) - 1))
266 	return bfd_reloc_overflow;
267       /* Used for ldr*|str* rt, [rn, #uimm12] to provide the low order
268          12 bits of the page offset following BFD_RELOC_AARCH64_ADR_HI21_PCREL
269          which computes the (pc-relative) page base.  */
270       contents = reencode_ldst_pos_imm (contents, addend);
271       break;
272 
273       /* Group relocations to create high bits of a 16, 32, 48 or 64
274          bit signed data or abs address inline. Will change
275          instruction to MOVN or MOVZ depending on sign of calculated
276          value.  */
277 
278     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
279     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
280     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
281     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
282     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
283     case BFD_RELOC_AARCH64_MOVW_G0_S:
284     case BFD_RELOC_AARCH64_MOVW_G1_S:
285     case BFD_RELOC_AARCH64_MOVW_G2_S:
286       /* NOTE: We can only come here with movz or movn.  */
287       if (addend < 0)
288 	{
289 	  /* Force use of MOVN.  */
290 	  addend = ~addend;
291 	  contents = reencode_movzn_to_movn (contents);
292 	}
293       else
294 	{
295 	  /* Force use of MOVZ.  */
296 	  contents = reencode_movzn_to_movz (contents);
297 	}
298       /* fall through */
299 
300       /* Group relocations to create a 16, 32, 48 or 64 bit unsigned
301          data or abs address inline.  */
302 
303     case BFD_RELOC_AARCH64_MOVW_G0:
304     case BFD_RELOC_AARCH64_MOVW_G0_NC:
305     case BFD_RELOC_AARCH64_MOVW_G1:
306     case BFD_RELOC_AARCH64_MOVW_G1_NC:
307     case BFD_RELOC_AARCH64_MOVW_G2:
308     case BFD_RELOC_AARCH64_MOVW_G2_NC:
309     case BFD_RELOC_AARCH64_MOVW_G3:
310       contents = reencode_movw_imm (contents, addend);
311       break;
312 
313     default:
314       /* Repack simple data */
315       if (howto->dst_mask & (howto->dst_mask + 1))
316 	return bfd_reloc_notsupported;
317 
318       contents = ((contents & ~howto->dst_mask) | (addend & howto->dst_mask));
319       break;
320     }
321 
322   switch (size)
323     {
324     case 2:
325       bfd_put_16 (abfd, contents, address);
326       break;
327     case 4:
328       if (howto->dst_mask != 0xffffffff)
329 	/* must be 32-bit instruction, always little-endian */
330 	bfd_putl32 (contents, address);
331       else
332 	/* must be 32-bit data (endianness dependent) */
333 	bfd_put_32 (abfd, contents, address);
334       break;
335     case 8:
336       bfd_put_64 (abfd, contents, address);
337       break;
338     default:
339       abort ();
340     }
341 
342   return status;
343 }
344 
345 bfd_vma
_bfd_aarch64_elf_resolve_relocation(bfd_reloc_code_real_type r_type,bfd_vma place,bfd_vma value,bfd_vma addend,bfd_boolean weak_undef_p)346 _bfd_aarch64_elf_resolve_relocation (bfd_reloc_code_real_type r_type,
347 				     bfd_vma place, bfd_vma value,
348 				     bfd_vma addend, bfd_boolean weak_undef_p)
349 {
350   switch (r_type)
351     {
352     case BFD_RELOC_AARCH64_TLSDESC_CALL:
353     case BFD_RELOC_AARCH64_NONE:
354       break;
355 
356     case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
357     case BFD_RELOC_AARCH64_BRANCH19:
358     case BFD_RELOC_AARCH64_LD_LO19_PCREL:
359     case BFD_RELOC_AARCH64_16_PCREL:
360     case BFD_RELOC_AARCH64_32_PCREL:
361     case BFD_RELOC_AARCH64_64_PCREL:
362     case BFD_RELOC_AARCH64_TSTBR14:
363       if (weak_undef_p)
364 	value = place;
365       value = value + addend - place;
366       break;
367 
368     case BFD_RELOC_AARCH64_CALL26:
369     case BFD_RELOC_AARCH64_JUMP26:
370       value = value + addend - place;
371       break;
372 
373     case BFD_RELOC_AARCH64_16:
374     case BFD_RELOC_AARCH64_32:
375     case BFD_RELOC_AARCH64_MOVW_G0_S:
376     case BFD_RELOC_AARCH64_MOVW_G1_S:
377     case BFD_RELOC_AARCH64_MOVW_G2_S:
378     case BFD_RELOC_AARCH64_MOVW_G0:
379     case BFD_RELOC_AARCH64_MOVW_G0_NC:
380     case BFD_RELOC_AARCH64_MOVW_G1:
381     case BFD_RELOC_AARCH64_MOVW_G1_NC:
382     case BFD_RELOC_AARCH64_MOVW_G2:
383     case BFD_RELOC_AARCH64_MOVW_G2_NC:
384     case BFD_RELOC_AARCH64_MOVW_G3:
385       value = value + addend;
386       break;
387 
388     case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
389     case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
390       if (weak_undef_p)
391 	value = PG (place);
392       value = PG (value + addend) - PG (place);
393       break;
394 
395     case BFD_RELOC_AARCH64_GOT_LD_PREL19:
396       value = value + addend - place;
397       break;
398 
399     case BFD_RELOC_AARCH64_ADR_GOT_PAGE:
400     case BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21:
401     case BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21:
402     case BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
403       value = PG (value + addend) - PG (place);
404       break;
405 
406     case BFD_RELOC_AARCH64_ADD_LO12:
407     case BFD_RELOC_AARCH64_LD64_GOT_LO12_NC:
408     case BFD_RELOC_AARCH64_LD32_GOT_LO12_NC:
409     case BFD_RELOC_AARCH64_LDST8_LO12:
410     case BFD_RELOC_AARCH64_LDST16_LO12:
411     case BFD_RELOC_AARCH64_LDST32_LO12:
412     case BFD_RELOC_AARCH64_LDST64_LO12:
413     case BFD_RELOC_AARCH64_LDST128_LO12:
414     case BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC:
415     case BFD_RELOC_AARCH64_TLSDESC_ADD:
416     case BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC:
417     case BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC:
418     case BFD_RELOC_AARCH64_TLSDESC_LDR:
419     case BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC:
420     case BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
421     case BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC:
422     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
423     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
424       value = PG_OFFSET (value + addend);
425       break;
426 
427     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
428     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
429       value = (value + addend) & (bfd_vma) 0xffff0000;
430       break;
431     case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
432       value = (value + addend) & (bfd_vma) 0xfff000;
433       break;
434 
435     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
436     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
437       value = (value + addend) & (bfd_vma) 0xffff;
438       break;
439 
440     case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
441       value = (value + addend) & ~(bfd_vma) 0xffffffff;
442       value -= place & ~(bfd_vma) 0xffffffff;
443       break;
444 
445     default:
446       break;
447     }
448 
449   return value;
450 }
451 
452 /* Hook called by the linker routine which adds symbols from an object
453    file.  */
454 
455 bfd_boolean
_bfd_aarch64_elf_add_symbol_hook(bfd * abfd,struct bfd_link_info * info,Elf_Internal_Sym * sym,const char ** namep ATTRIBUTE_UNUSED,flagword * flagsp ATTRIBUTE_UNUSED,asection ** secp ATTRIBUTE_UNUSED,bfd_vma * valp ATTRIBUTE_UNUSED)456 _bfd_aarch64_elf_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
457 				  Elf_Internal_Sym *sym,
458 				  const char **namep ATTRIBUTE_UNUSED,
459 				  flagword *flagsp ATTRIBUTE_UNUSED,
460 				  asection **secp ATTRIBUTE_UNUSED,
461 				  bfd_vma *valp ATTRIBUTE_UNUSED)
462 {
463   if ((ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC
464        || ELF_ST_BIND (sym->st_info) == STB_GNU_UNIQUE)
465       && (abfd->flags & DYNAMIC) == 0
466       && bfd_get_flavour (info->output_bfd) == bfd_target_elf_flavour)
467     elf_tdata (info->output_bfd)->has_gnu_symbols = TRUE;
468 
469   return TRUE;
470 }
471 
472 /* Support for core dump NOTE sections.  */
473 
474 bfd_boolean
_bfd_aarch64_elf_grok_prstatus(bfd * abfd,Elf_Internal_Note * note)475 _bfd_aarch64_elf_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
476 {
477   int offset;
478   size_t size;
479 
480   switch (note->descsz)
481     {
482       default:
483 	return FALSE;
484 
485       case 392:		/* sizeof(struct elf_prstatus) on Linux/arm64.  */
486 	/* pr_cursig */
487 	elf_tdata (abfd)->core->signal
488 	  = bfd_get_16 (abfd, note->descdata + 12);
489 
490 	/* pr_pid */
491 	elf_tdata (abfd)->core->lwpid
492 	  = bfd_get_32 (abfd, note->descdata + 32);
493 
494 	/* pr_reg */
495 	offset = 112;
496 	size = 272;
497 
498 	break;
499     }
500 
501   /* Make a ".reg/999" section.  */
502   return _bfd_elfcore_make_pseudosection (abfd, ".reg",
503 					  size, note->descpos + offset);
504 }
505 
506 bfd_boolean
_bfd_aarch64_elf_grok_psinfo(bfd * abfd,Elf_Internal_Note * note)507 _bfd_aarch64_elf_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
508 {
509   switch (note->descsz)
510     {
511     default:
512       return FALSE;
513 
514     case 136:        /* This is sizeof(struct elf_prpsinfo) on Linux/aarch64.  */
515       elf_tdata (abfd)->core->pid = bfd_get_32 (abfd, note->descdata + 24);
516       elf_tdata (abfd)->core->program
517 	= _bfd_elfcore_strndup (abfd, note->descdata + 40, 16);
518       elf_tdata (abfd)->core->command
519 	= _bfd_elfcore_strndup (abfd, note->descdata + 56, 80);
520     }
521 
522   /* Note that for some reason, a spurious space is tacked
523      onto the end of the args in some (at least one anyway)
524      implementations, so strip it off if it exists.  */
525 
526   {
527     char *command = elf_tdata (abfd)->core->command;
528     int n = strlen (command);
529 
530     if (0 < n && command[n - 1] == ' ')
531       command[n - 1] = '\0';
532   }
533 
534   return TRUE;
535 }
536 
537 char *
_bfd_aarch64_elf_write_core_note(bfd * abfd,char * buf,int * bufsiz,int note_type,...)538 _bfd_aarch64_elf_write_core_note (bfd *abfd, char *buf, int *bufsiz, int note_type,
539 				  ...)
540 {
541   switch (note_type)
542     {
543     default:
544       return NULL;
545 
546     case NT_PRPSINFO:
547       {
548         char data[136];
549         va_list ap;
550 
551         va_start (ap, note_type);
552         memset (data, 0, sizeof (data));
553         strncpy (data + 40, va_arg (ap, const char *), 16);
554         strncpy (data + 56, va_arg (ap, const char *), 80);
555         va_end (ap);
556 
557         return elfcore_write_note (abfd, buf, bufsiz, "CORE",
558 				   note_type, data, sizeof (data));
559       }
560 
561     case NT_PRSTATUS:
562       {
563         char data[392];
564         va_list ap;
565         long pid;
566         int cursig;
567         const void *greg;
568 
569         va_start (ap, note_type);
570         memset (data, 0, sizeof (data));
571         pid = va_arg (ap, long);
572         bfd_put_32 (abfd, pid, data + 32);
573         cursig = va_arg (ap, int);
574         bfd_put_16 (abfd, cursig, data + 12);
575         greg = va_arg (ap, const void *);
576         memcpy (data + 112, greg, 272);
577         va_end (ap);
578 
579         return elfcore_write_note (abfd, buf, bufsiz, "CORE",
580 				   note_type, data, sizeof (data));
581       }
582     }
583 }
584