1 //===-- LiveStackAnalysis.cpp - Live Stack Slot Analysis ------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the live stack slot analysis pass. It is analogous to
11 // live interval analysis except it's analyzing liveness of stack slots rather
12 // than registers.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/LiveStackAnalysis.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 #include <limits>
25 using namespace llvm;
26 
27 #define DEBUG_TYPE "livestacks"
28 
29 char LiveStacks::ID = 0;
30 INITIALIZE_PASS_BEGIN(LiveStacks, "livestacks",
31                 "Live Stack Slot Analysis", false, false)
32 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
33 INITIALIZE_PASS_END(LiveStacks, "livestacks",
34                 "Live Stack Slot Analysis", false, false)
35 
36 char &llvm::LiveStacksID = LiveStacks::ID;
37 
getAnalysisUsage(AnalysisUsage & AU) const38 void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
39   AU.setPreservesAll();
40   AU.addPreserved<SlotIndexes>();
41   AU.addRequiredTransitive<SlotIndexes>();
42   MachineFunctionPass::getAnalysisUsage(AU);
43 }
44 
releaseMemory()45 void LiveStacks::releaseMemory() {
46   // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
47   VNInfoAllocator.Reset();
48   S2IMap.clear();
49   S2RCMap.clear();
50 }
51 
runOnMachineFunction(MachineFunction & MF)52 bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
53   TRI = MF.getSubtarget().getRegisterInfo();
54   // FIXME: No analysis is being done right now. We are relying on the
55   // register allocators to provide the information.
56   return false;
57 }
58 
59 LiveInterval &
getOrCreateInterval(int Slot,const TargetRegisterClass * RC)60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
61   assert(Slot >= 0 && "Spill slot indice must be >= 0");
62   SS2IntervalMap::iterator I = S2IMap.find(Slot);
63   if (I == S2IMap.end()) {
64     I = S2IMap.emplace(std::piecewise_construct, std::forward_as_tuple(Slot),
65                        std::forward_as_tuple(
66                            TargetRegisterInfo::index2StackSlot(Slot), 0.0F))
67             .first;
68     S2RCMap.insert(std::make_pair(Slot, RC));
69   } else {
70     // Use the largest common subclass register class.
71     const TargetRegisterClass *OldRC = S2RCMap[Slot];
72     S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
73   }
74   return I->second;
75 }
76 
77 /// print - Implement the dump method.
print(raw_ostream & OS,const Module *) const78 void LiveStacks::print(raw_ostream &OS, const Module*) const {
79 
80   OS << "********** INTERVALS **********\n";
81   for (const_iterator I = begin(), E = end(); I != E; ++I) {
82     I->second.print(OS);
83     int Slot = I->first;
84     const TargetRegisterClass *RC = getIntervalRegClass(Slot);
85     if (RC)
86       OS << " [" << TRI->getRegClassName(RC) << "]\n";
87     else
88       OS << " [Unknown]\n";
89   }
90 }
91