1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "AMDGPUSubtarget.h"
16 #include "R600ISelLowering.h"
17 #include "R600InstrInfo.h"
18 #include "R600MachineScheduler.h"
19 #include "SIFrameLowering.h"
20 #include "SIISelLowering.h"
21 #include "SIInstrInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/ADT/SmallString.h"
24 #include "llvm/CodeGen/MachineScheduler.h"
25
26 using namespace llvm;
27
28 #define DEBUG_TYPE "amdgpu-subtarget"
29
30 #define GET_SUBTARGETINFO_ENUM
31 #define GET_SUBTARGETINFO_TARGET_DESC
32 #define GET_SUBTARGETINFO_CTOR
33 #include "AMDGPUGenSubtargetInfo.inc"
34
35 AMDGPUSubtarget &
initializeSubtargetDependencies(const Triple & TT,StringRef GPU,StringRef FS)36 AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
37 StringRef GPU, StringRef FS) {
38 // Determine default and user-specified characteristics
39 // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
40 // enabled, but some instructions do not respect them and they run at the
41 // double precision rate, so don't enable by default.
42 //
43 // We want to be able to turn these off, but making this a subtarget feature
44 // for SI has the unhelpful behavior that it unsets everything else if you
45 // disable it.
46
47 SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
48 FullFS += FS;
49
50 if (GPU == "" && TT.getArch() == Triple::amdgcn)
51 GPU = "SI";
52
53 ParseSubtargetFeatures(GPU, FullFS);
54
55 // FIXME: I don't think think Evergreen has any useful support for
56 // denormals, but should be checked. Should we issue a warning somewhere
57 // if someone tries to enable these?
58 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
59 FP32Denormals = false;
60 FP64Denormals = false;
61 }
62 return *this;
63 }
64
AMDGPUSubtarget(const Triple & TT,StringRef GPU,StringRef FS,TargetMachine & TM)65 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
66 TargetMachine &TM)
67 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
68 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
69 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
70 FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
71 CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
72 EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
73 EnableUnsafeDSOffsetFolding(false),
74 WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
75 EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false),
76 GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0),
77 IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false),
78 FrameLowering(nullptr),
79 InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
80
81 initializeSubtargetDependencies(TT, GPU, FS);
82
83 const unsigned MaxStackAlign = 64 * 16; // Maximum stack alignment (long16)
84
85 if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
86 InstrInfo.reset(new R600InstrInfo(*this));
87 TLInfo.reset(new R600TargetLowering(TM, *this));
88
89 // FIXME: Should have R600 specific FrameLowering
90 FrameLowering.reset(new AMDGPUFrameLowering(
91 TargetFrameLowering::StackGrowsUp,
92 MaxStackAlign,
93 0));
94 } else {
95 InstrInfo.reset(new SIInstrInfo(*this));
96 TLInfo.reset(new SITargetLowering(TM, *this));
97 FrameLowering.reset(new SIFrameLowering(
98 TargetFrameLowering::StackGrowsUp,
99 MaxStackAlign,
100 0));
101 }
102 }
103
getStackEntrySize() const104 unsigned AMDGPUSubtarget::getStackEntrySize() const {
105 assert(getGeneration() <= NORTHERN_ISLANDS);
106 switch(getWavefrontSize()) {
107 case 16:
108 return 8;
109 case 32:
110 return hasCaymanISA() ? 4 : 8;
111 case 64:
112 return 4;
113 default:
114 llvm_unreachable("Illegal wavefront size.");
115 }
116 }
117
getAmdKernelCodeChipID() const118 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
119 switch(getGeneration()) {
120 default: llvm_unreachable("ChipID unknown");
121 case SEA_ISLANDS: return 12;
122 }
123 }
124
getIsaVersion() const125 AMDGPU::IsaVersion AMDGPUSubtarget::getIsaVersion() const {
126 return AMDGPU::getIsaVersion(getFeatureBits());
127 }
128
isVGPRSpillingEnabled(const SIMachineFunctionInfo * MFI) const129 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
130 const SIMachineFunctionInfo *MFI) const {
131 return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
132 }
133
overrideSchedPolicy(MachineSchedPolicy & Policy,MachineInstr * begin,MachineInstr * end,unsigned NumRegionInstrs) const134 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
135 MachineInstr *begin,
136 MachineInstr *end,
137 unsigned NumRegionInstrs) const {
138 if (getGeneration() >= SOUTHERN_ISLANDS) {
139
140 // Track register pressure so the scheduler can try to decrease
141 // pressure once register usage is above the threshold defined by
142 // SIRegisterInfo::getRegPressureSetLimit()
143 Policy.ShouldTrackPressure = true;
144
145 // Enabling both top down and bottom up scheduling seems to give us less
146 // register spills than just using one of these approaches on its own.
147 Policy.OnlyTopDown = false;
148 Policy.OnlyBottomUp = false;
149 }
150 }
151
152