1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 #include "MipsISelLowering.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MCTargetDesc/MipsBaseInfo.h"
17 #include "MipsCCState.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "MipsTargetObjectFile.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/FunctionLoweringInfo.h"
31 #include "llvm/CodeGen/SelectionDAGISel.h"
32 #include "llvm/CodeGen/ValueTypes.h"
33 #include "llvm/IR/CallingConv.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/GlobalVariable.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include <cctype>
41
42 using namespace llvm;
43
44 #define DEBUG_TYPE "mips-lower"
45
46 STATISTIC(NumTailCalls, "Number of tail calls");
47
48 static cl::opt<bool>
49 LargeGOT("mxgot", cl::Hidden,
50 cl::desc("MIPS: Enable GOT larger than 64k."), cl::init(false));
51
52 static cl::opt<bool>
53 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
54 cl::desc("MIPS: Don't trap on integer division by zero."),
55 cl::init(false));
56
57 static const MCPhysReg Mips64DPRegs[8] = {
58 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
59 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
60 };
61
62 // If I is a shifted mask, set the size (Size) and the first bit of the
63 // mask (Pos), and return true.
64 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
isShiftedMask(uint64_t I,uint64_t & Pos,uint64_t & Size)65 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
66 if (!isShiftedMask_64(I))
67 return false;
68
69 Size = countPopulation(I);
70 Pos = countTrailingZeros(I);
71 return true;
72 }
73
getGlobalReg(SelectionDAG & DAG,EVT Ty) const74 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
75 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
76 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
77 }
78
getTargetNode(GlobalAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const79 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
80 SelectionDAG &DAG,
81 unsigned Flag) const {
82 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
83 }
84
getTargetNode(ExternalSymbolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const85 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
86 SelectionDAG &DAG,
87 unsigned Flag) const {
88 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
89 }
90
getTargetNode(BlockAddressSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const91 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
92 SelectionDAG &DAG,
93 unsigned Flag) const {
94 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
95 }
96
getTargetNode(JumpTableSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const97 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
98 SelectionDAG &DAG,
99 unsigned Flag) const {
100 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
101 }
102
getTargetNode(ConstantPoolSDNode * N,EVT Ty,SelectionDAG & DAG,unsigned Flag) const103 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
104 SelectionDAG &DAG,
105 unsigned Flag) const {
106 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
107 N->getOffset(), Flag);
108 }
109
getTargetNodeName(unsigned Opcode) const110 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
111 switch ((MipsISD::NodeType)Opcode) {
112 case MipsISD::FIRST_NUMBER: break;
113 case MipsISD::JmpLink: return "MipsISD::JmpLink";
114 case MipsISD::TailCall: return "MipsISD::TailCall";
115 case MipsISD::Hi: return "MipsISD::Hi";
116 case MipsISD::Lo: return "MipsISD::Lo";
117 case MipsISD::GPRel: return "MipsISD::GPRel";
118 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
119 case MipsISD::Ret: return "MipsISD::Ret";
120 case MipsISD::ERet: return "MipsISD::ERet";
121 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
122 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
123 case MipsISD::FPCmp: return "MipsISD::FPCmp";
124 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
125 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
126 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
127 case MipsISD::MFHI: return "MipsISD::MFHI";
128 case MipsISD::MFLO: return "MipsISD::MFLO";
129 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
130 case MipsISD::Mult: return "MipsISD::Mult";
131 case MipsISD::Multu: return "MipsISD::Multu";
132 case MipsISD::MAdd: return "MipsISD::MAdd";
133 case MipsISD::MAddu: return "MipsISD::MAddu";
134 case MipsISD::MSub: return "MipsISD::MSub";
135 case MipsISD::MSubu: return "MipsISD::MSubu";
136 case MipsISD::DivRem: return "MipsISD::DivRem";
137 case MipsISD::DivRemU: return "MipsISD::DivRemU";
138 case MipsISD::DivRem16: return "MipsISD::DivRem16";
139 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
140 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
141 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
142 case MipsISD::Wrapper: return "MipsISD::Wrapper";
143 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
144 case MipsISD::Sync: return "MipsISD::Sync";
145 case MipsISD::Ext: return "MipsISD::Ext";
146 case MipsISD::Ins: return "MipsISD::Ins";
147 case MipsISD::LWL: return "MipsISD::LWL";
148 case MipsISD::LWR: return "MipsISD::LWR";
149 case MipsISD::SWL: return "MipsISD::SWL";
150 case MipsISD::SWR: return "MipsISD::SWR";
151 case MipsISD::LDL: return "MipsISD::LDL";
152 case MipsISD::LDR: return "MipsISD::LDR";
153 case MipsISD::SDL: return "MipsISD::SDL";
154 case MipsISD::SDR: return "MipsISD::SDR";
155 case MipsISD::EXTP: return "MipsISD::EXTP";
156 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
157 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
158 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
159 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
160 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
161 case MipsISD::SHILO: return "MipsISD::SHILO";
162 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
163 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
164 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
165 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
166 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
167 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
168 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
169 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
170 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
171 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
172 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
173 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
174 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
175 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
176 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
177 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
178 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
179 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
180 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
181 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
182 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
183 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
184 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
185 case MipsISD::MULT: return "MipsISD::MULT";
186 case MipsISD::MULTU: return "MipsISD::MULTU";
187 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
188 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
189 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
190 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
191 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
192 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
193 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
194 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
195 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
196 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
197 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
198 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
199 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
200 case MipsISD::VCEQ: return "MipsISD::VCEQ";
201 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
202 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
203 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
204 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
205 case MipsISD::VSMAX: return "MipsISD::VSMAX";
206 case MipsISD::VSMIN: return "MipsISD::VSMIN";
207 case MipsISD::VUMAX: return "MipsISD::VUMAX";
208 case MipsISD::VUMIN: return "MipsISD::VUMIN";
209 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
210 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
211 case MipsISD::VNOR: return "MipsISD::VNOR";
212 case MipsISD::VSHF: return "MipsISD::VSHF";
213 case MipsISD::SHF: return "MipsISD::SHF";
214 case MipsISD::ILVEV: return "MipsISD::ILVEV";
215 case MipsISD::ILVOD: return "MipsISD::ILVOD";
216 case MipsISD::ILVL: return "MipsISD::ILVL";
217 case MipsISD::ILVR: return "MipsISD::ILVR";
218 case MipsISD::PCKEV: return "MipsISD::PCKEV";
219 case MipsISD::PCKOD: return "MipsISD::PCKOD";
220 case MipsISD::INSVE: return "MipsISD::INSVE";
221 }
222 return nullptr;
223 }
224
MipsTargetLowering(const MipsTargetMachine & TM,const MipsSubtarget & STI)225 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
226 const MipsSubtarget &STI)
227 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
228 // Mips does not have i1 type, so use i32 for
229 // setcc operations results (slt, sgt, ...).
230 setBooleanContents(ZeroOrOneBooleanContent);
231 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
232 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
233 // does. Integer booleans still use 0 and 1.
234 if (Subtarget.hasMips32r6())
235 setBooleanContents(ZeroOrOneBooleanContent,
236 ZeroOrNegativeOneBooleanContent);
237
238 // Load extented operations for i1 types must be promoted
239 for (MVT VT : MVT::integer_valuetypes()) {
240 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
241 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
242 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
243 }
244
245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
246 // for f32, f16
247 for (MVT VT : MVT::fp_valuetypes()) {
248 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
249 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
250 }
251
252 // Set LoadExtAction for f16 vectors to Expand
253 for (MVT VT : MVT::fp_vector_valuetypes()) {
254 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
255 if (F16VT.isValid())
256 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
257 }
258
259 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
260 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
261
262 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
263
264 // Used by legalize types to correctly generate the setcc result.
265 // Without this, every float setcc comes with a AND/OR with the result,
266 // we don't want this, since the fpcmp result goes to a flag register,
267 // which is used implicitly by brcond and select operations.
268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
269
270 // Mips Custom Operations
271 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
272 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
275 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
277 setOperationAction(ISD::SELECT, MVT::f32, Custom);
278 setOperationAction(ISD::SELECT, MVT::f64, Custom);
279 setOperationAction(ISD::SELECT, MVT::i32, Custom);
280 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
281 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
282 setOperationAction(ISD::SETCC, MVT::f32, Custom);
283 setOperationAction(ISD::SETCC, MVT::f64, Custom);
284 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
285 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
286 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
287 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
288
289 if (Subtarget.isGP64bit()) {
290 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
291 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
292 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
293 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
294 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
295 setOperationAction(ISD::SELECT, MVT::i64, Custom);
296 setOperationAction(ISD::LOAD, MVT::i64, Custom);
297 setOperationAction(ISD::STORE, MVT::i64, Custom);
298 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
299 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
300 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
301 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
302 }
303
304 if (!Subtarget.isGP64bit()) {
305 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
306 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
307 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
308 }
309
310 setOperationAction(ISD::ADD, MVT::i32, Custom);
311 if (Subtarget.isGP64bit())
312 setOperationAction(ISD::ADD, MVT::i64, Custom);
313
314 setOperationAction(ISD::SDIV, MVT::i32, Expand);
315 setOperationAction(ISD::SREM, MVT::i32, Expand);
316 setOperationAction(ISD::UDIV, MVT::i32, Expand);
317 setOperationAction(ISD::UREM, MVT::i32, Expand);
318 setOperationAction(ISD::SDIV, MVT::i64, Expand);
319 setOperationAction(ISD::SREM, MVT::i64, Expand);
320 setOperationAction(ISD::UDIV, MVT::i64, Expand);
321 setOperationAction(ISD::UREM, MVT::i64, Expand);
322
323 // Operations not directly supported by Mips.
324 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
325 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
326 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
327 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
328 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
329 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
330 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
332 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
334 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
335 if (Subtarget.hasCnMips()) {
336 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
337 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
338 } else {
339 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
340 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
341 }
342 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
343 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
344 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
345 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
346 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
347 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
348 setOperationAction(ISD::ROTL, MVT::i32, Expand);
349 setOperationAction(ISD::ROTL, MVT::i64, Expand);
350 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
351 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
352
353 if (!Subtarget.hasMips32r2())
354 setOperationAction(ISD::ROTR, MVT::i32, Expand);
355
356 if (!Subtarget.hasMips64r2())
357 setOperationAction(ISD::ROTR, MVT::i64, Expand);
358
359 setOperationAction(ISD::FSIN, MVT::f32, Expand);
360 setOperationAction(ISD::FSIN, MVT::f64, Expand);
361 setOperationAction(ISD::FCOS, MVT::f32, Expand);
362 setOperationAction(ISD::FCOS, MVT::f64, Expand);
363 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
364 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
365 setOperationAction(ISD::FPOWI, MVT::f32, Expand);
366 setOperationAction(ISD::FPOW, MVT::f32, Expand);
367 setOperationAction(ISD::FPOW, MVT::f64, Expand);
368 setOperationAction(ISD::FLOG, MVT::f32, Expand);
369 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
370 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
371 setOperationAction(ISD::FEXP, MVT::f32, Expand);
372 setOperationAction(ISD::FMA, MVT::f32, Expand);
373 setOperationAction(ISD::FMA, MVT::f64, Expand);
374 setOperationAction(ISD::FREM, MVT::f32, Expand);
375 setOperationAction(ISD::FREM, MVT::f64, Expand);
376
377 // Lower f16 conversion operations into library calls
378 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
379 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
380 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
381 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
382
383 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
384
385 setOperationAction(ISD::VASTART, MVT::Other, Custom);
386 setOperationAction(ISD::VAARG, MVT::Other, Custom);
387 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
388 setOperationAction(ISD::VAEND, MVT::Other, Expand);
389
390 // Use the default for now
391 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
392 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
393
394 if (!Subtarget.isGP64bit()) {
395 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
396 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
397 }
398
399 setInsertFencesForAtomic(true);
400
401 if (!Subtarget.hasMips32r2()) {
402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
404 }
405
406 // MIPS16 lacks MIPS32's clz and clo instructions.
407 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
408 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
409 if (!Subtarget.hasMips64())
410 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
411
412 if (!Subtarget.hasMips32r2())
413 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
414 if (!Subtarget.hasMips64r2())
415 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
416
417 if (Subtarget.isGP64bit()) {
418 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
419 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
420 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
421 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
422 }
423
424 setOperationAction(ISD::TRAP, MVT::Other, Legal);
425
426 setTargetDAGCombine(ISD::SDIVREM);
427 setTargetDAGCombine(ISD::UDIVREM);
428 setTargetDAGCombine(ISD::SELECT);
429 setTargetDAGCombine(ISD::AND);
430 setTargetDAGCombine(ISD::OR);
431 setTargetDAGCombine(ISD::ADD);
432
433 setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2);
434
435 // The arguments on the stack are defined in terms of 4-byte slots on O32
436 // and 8-byte slots on N32/N64.
437 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? 8 : 4);
438
439 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
440
441 MaxStoresPerMemcpy = 16;
442
443 isMicroMips = Subtarget.inMicroMipsMode();
444 }
445
create(const MipsTargetMachine & TM,const MipsSubtarget & STI)446 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
447 const MipsSubtarget &STI) {
448 if (STI.inMips16Mode())
449 return llvm::createMips16TargetLowering(TM, STI);
450
451 return llvm::createMipsSETargetLowering(TM, STI);
452 }
453
454 // Create a fast isel object.
455 FastISel *
createFastISel(FunctionLoweringInfo & funcInfo,const TargetLibraryInfo * libInfo) const456 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
457 const TargetLibraryInfo *libInfo) const {
458 if (!funcInfo.MF->getTarget().Options.EnableFastISel)
459 return TargetLowering::createFastISel(funcInfo, libInfo);
460 return Mips::createFastISel(funcInfo, libInfo);
461 }
462
getSetCCResultType(const DataLayout &,LLVMContext &,EVT VT) const463 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
464 EVT VT) const {
465 if (!VT.isVector())
466 return MVT::i32;
467 return VT.changeVectorElementTypeToInteger();
468 }
469
performDivRemCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)470 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
471 TargetLowering::DAGCombinerInfo &DCI,
472 const MipsSubtarget &Subtarget) {
473 if (DCI.isBeforeLegalizeOps())
474 return SDValue();
475
476 EVT Ty = N->getValueType(0);
477 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
478 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
479 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
480 MipsISD::DivRemU16;
481 SDLoc DL(N);
482
483 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
484 N->getOperand(0), N->getOperand(1));
485 SDValue InChain = DAG.getEntryNode();
486 SDValue InGlue = DivRem;
487
488 // insert MFLO
489 if (N->hasAnyUseOfValue(0)) {
490 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
491 InGlue);
492 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
493 InChain = CopyFromLo.getValue(1);
494 InGlue = CopyFromLo.getValue(2);
495 }
496
497 // insert MFHI
498 if (N->hasAnyUseOfValue(1)) {
499 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
500 HI, Ty, InGlue);
501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
502 }
503
504 return SDValue();
505 }
506
condCodeToFCC(ISD::CondCode CC)507 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
508 switch (CC) {
509 default: llvm_unreachable("Unknown fp condition code!");
510 case ISD::SETEQ:
511 case ISD::SETOEQ: return Mips::FCOND_OEQ;
512 case ISD::SETUNE: return Mips::FCOND_UNE;
513 case ISD::SETLT:
514 case ISD::SETOLT: return Mips::FCOND_OLT;
515 case ISD::SETGT:
516 case ISD::SETOGT: return Mips::FCOND_OGT;
517 case ISD::SETLE:
518 case ISD::SETOLE: return Mips::FCOND_OLE;
519 case ISD::SETGE:
520 case ISD::SETOGE: return Mips::FCOND_OGE;
521 case ISD::SETULT: return Mips::FCOND_ULT;
522 case ISD::SETULE: return Mips::FCOND_ULE;
523 case ISD::SETUGT: return Mips::FCOND_UGT;
524 case ISD::SETUGE: return Mips::FCOND_UGE;
525 case ISD::SETUO: return Mips::FCOND_UN;
526 case ISD::SETO: return Mips::FCOND_OR;
527 case ISD::SETNE:
528 case ISD::SETONE: return Mips::FCOND_ONE;
529 case ISD::SETUEQ: return Mips::FCOND_UEQ;
530 }
531 }
532
533
534 /// This function returns true if the floating point conditional branches and
535 /// conditional moves which use condition code CC should be inverted.
invertFPCondCodeUser(Mips::CondCode CC)536 static bool invertFPCondCodeUser(Mips::CondCode CC) {
537 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
538 return false;
539
540 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
541 "Illegal Condition Code");
542
543 return true;
544 }
545
546 // Creates and returns an FPCmp node from a setcc node.
547 // Returns Op if setcc is not a floating point comparison.
createFPCmp(SelectionDAG & DAG,const SDValue & Op)548 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
549 // must be a SETCC node
550 if (Op.getOpcode() != ISD::SETCC)
551 return Op;
552
553 SDValue LHS = Op.getOperand(0);
554
555 if (!LHS.getValueType().isFloatingPoint())
556 return Op;
557
558 SDValue RHS = Op.getOperand(1);
559 SDLoc DL(Op);
560
561 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
562 // node if necessary.
563 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
564
565 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
566 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
567 }
568
569 // Creates and returns a CMovFPT/F node.
createCMovFP(SelectionDAG & DAG,SDValue Cond,SDValue True,SDValue False,SDLoc DL)570 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
571 SDValue False, SDLoc DL) {
572 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
573 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
574 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
575
576 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
577 True.getValueType(), True, FCC0, False, Cond);
578 }
579
performSELECTCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)580 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
581 TargetLowering::DAGCombinerInfo &DCI,
582 const MipsSubtarget &Subtarget) {
583 if (DCI.isBeforeLegalizeOps())
584 return SDValue();
585
586 SDValue SetCC = N->getOperand(0);
587
588 if ((SetCC.getOpcode() != ISD::SETCC) ||
589 !SetCC.getOperand(0).getValueType().isInteger())
590 return SDValue();
591
592 SDValue False = N->getOperand(2);
593 EVT FalseTy = False.getValueType();
594
595 if (!FalseTy.isInteger())
596 return SDValue();
597
598 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
599
600 // If the RHS (False) is 0, we swap the order of the operands
601 // of ISD::SELECT (obviously also inverting the condition) so that we can
602 // take advantage of conditional moves using the $0 register.
603 // Example:
604 // return (a != 0) ? x : 0;
605 // load $reg, x
606 // movz $reg, $0, a
607 if (!FalseC)
608 return SDValue();
609
610 const SDLoc DL(N);
611
612 if (!FalseC->getZExtValue()) {
613 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
614 SDValue True = N->getOperand(1);
615
616 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
617 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
618
619 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
620 }
621
622 // If both operands are integer constants there's a possibility that we
623 // can do some interesting optimizations.
624 SDValue True = N->getOperand(1);
625 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
626
627 if (!TrueC || !True.getValueType().isInteger())
628 return SDValue();
629
630 // We'll also ignore MVT::i64 operands as this optimizations proves
631 // to be ineffective because of the required sign extensions as the result
632 // of a SETCC operator is always MVT::i32 for non-vector types.
633 if (True.getValueType() == MVT::i64)
634 return SDValue();
635
636 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
637
638 // 1) (a < x) ? y : y-1
639 // slti $reg1, a, x
640 // addiu $reg2, $reg1, y-1
641 if (Diff == 1)
642 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
643
644 // 2) (a < x) ? y-1 : y
645 // slti $reg1, a, x
646 // xor $reg1, $reg1, 1
647 // addiu $reg2, $reg1, y-1
648 if (Diff == -1) {
649 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
650 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
651 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
652 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
653 }
654
655 // Couldn't optimize.
656 return SDValue();
657 }
658
performCMovFPCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)659 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
660 TargetLowering::DAGCombinerInfo &DCI,
661 const MipsSubtarget &Subtarget) {
662 if (DCI.isBeforeLegalizeOps())
663 return SDValue();
664
665 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
666
667 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
668 if (!FalseC || FalseC->getZExtValue())
669 return SDValue();
670
671 // Since RHS (False) is 0, we swap the order of the True/False operands
672 // (obviously also inverting the condition) so that we can
673 // take advantage of conditional moves using the $0 register.
674 // Example:
675 // return (a != 0) ? x : 0;
676 // load $reg, x
677 // movz $reg, $0, a
678 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
679 MipsISD::CMovFP_T;
680
681 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
682 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
683 ValueIfFalse, FCC, ValueIfTrue, Glue);
684 }
685
performANDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)686 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
687 TargetLowering::DAGCombinerInfo &DCI,
688 const MipsSubtarget &Subtarget) {
689 // Pattern match EXT.
690 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
691 // => ext $dst, $src, size, pos
692 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
693 return SDValue();
694
695 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1);
696 unsigned ShiftRightOpc = ShiftRight.getOpcode();
697
698 // Op's first operand must be a shift right.
699 if (ShiftRightOpc != ISD::SRA && ShiftRightOpc != ISD::SRL)
700 return SDValue();
701
702 // The second operand of the shift must be an immediate.
703 ConstantSDNode *CN;
704 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
705 return SDValue();
706
707 uint64_t Pos = CN->getZExtValue();
708 uint64_t SMPos, SMSize;
709
710 // Op's second operand must be a shifted mask.
711 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
712 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
713 return SDValue();
714
715 // Return if the shifted mask does not start at bit 0 or the sum of its size
716 // and Pos exceeds the word's size.
717 EVT ValTy = N->getValueType(0);
718 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
719 return SDValue();
720
721 SDLoc DL(N);
722 return DAG.getNode(MipsISD::Ext, DL, ValTy,
723 ShiftRight.getOperand(0),
724 DAG.getConstant(Pos, DL, MVT::i32),
725 DAG.getConstant(SMSize, DL, MVT::i32));
726 }
727
performORCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)728 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
729 TargetLowering::DAGCombinerInfo &DCI,
730 const MipsSubtarget &Subtarget) {
731 // Pattern match INS.
732 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
733 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
734 // => ins $dst, $src, size, pos, $src1
735 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
736 return SDValue();
737
738 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
739 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
740 ConstantSDNode *CN;
741
742 // See if Op's first operand matches (and $src1 , mask0).
743 if (And0.getOpcode() != ISD::AND)
744 return SDValue();
745
746 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
747 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
748 return SDValue();
749
750 // See if Op's second operand matches (and (shl $src, pos), mask1).
751 if (And1.getOpcode() != ISD::AND)
752 return SDValue();
753
754 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
755 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
756 return SDValue();
757
758 // The shift masks must have the same position and size.
759 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
760 return SDValue();
761
762 SDValue Shl = And1.getOperand(0);
763 if (Shl.getOpcode() != ISD::SHL)
764 return SDValue();
765
766 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
767 return SDValue();
768
769 unsigned Shamt = CN->getZExtValue();
770
771 // Return if the shift amount and the first bit position of mask are not the
772 // same.
773 EVT ValTy = N->getValueType(0);
774 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
775 return SDValue();
776
777 SDLoc DL(N);
778 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
779 DAG.getConstant(SMPos0, DL, MVT::i32),
780 DAG.getConstant(SMSize0, DL, MVT::i32),
781 And0.getOperand(0));
782 }
783
performADDCombine(SDNode * N,SelectionDAG & DAG,TargetLowering::DAGCombinerInfo & DCI,const MipsSubtarget & Subtarget)784 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
785 TargetLowering::DAGCombinerInfo &DCI,
786 const MipsSubtarget &Subtarget) {
787 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
788
789 if (DCI.isBeforeLegalizeOps())
790 return SDValue();
791
792 SDValue Add = N->getOperand(1);
793
794 if (Add.getOpcode() != ISD::ADD)
795 return SDValue();
796
797 SDValue Lo = Add.getOperand(1);
798
799 if ((Lo.getOpcode() != MipsISD::Lo) ||
800 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
801 return SDValue();
802
803 EVT ValTy = N->getValueType(0);
804 SDLoc DL(N);
805
806 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
807 Add.getOperand(0));
808 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
809 }
810
PerformDAGCombine(SDNode * N,DAGCombinerInfo & DCI) const811 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
812 const {
813 SelectionDAG &DAG = DCI.DAG;
814 unsigned Opc = N->getOpcode();
815
816 switch (Opc) {
817 default: break;
818 case ISD::SDIVREM:
819 case ISD::UDIVREM:
820 return performDivRemCombine(N, DAG, DCI, Subtarget);
821 case ISD::SELECT:
822 return performSELECTCombine(N, DAG, DCI, Subtarget);
823 case MipsISD::CMovFP_F:
824 case MipsISD::CMovFP_T:
825 return performCMovFPCombine(N, DAG, DCI, Subtarget);
826 case ISD::AND:
827 return performANDCombine(N, DAG, DCI, Subtarget);
828 case ISD::OR:
829 return performORCombine(N, DAG, DCI, Subtarget);
830 case ISD::ADD:
831 return performADDCombine(N, DAG, DCI, Subtarget);
832 }
833
834 return SDValue();
835 }
836
isCheapToSpeculateCttz() const837 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
838 return Subtarget.hasMips32();
839 }
840
isCheapToSpeculateCtlz() const841 bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
842 return Subtarget.hasMips32();
843 }
844
845 void
LowerOperationWrapper(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const846 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
847 SmallVectorImpl<SDValue> &Results,
848 SelectionDAG &DAG) const {
849 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
850
851 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
852 Results.push_back(Res.getValue(I));
853 }
854
855 void
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const856 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
857 SmallVectorImpl<SDValue> &Results,
858 SelectionDAG &DAG) const {
859 return LowerOperationWrapper(N, Results, DAG);
860 }
861
862 SDValue MipsTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const863 LowerOperation(SDValue Op, SelectionDAG &DAG) const
864 {
865 switch (Op.getOpcode())
866 {
867 case ISD::BR_JT: return lowerBR_JT(Op, DAG);
868 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
869 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
870 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
871 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
872 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
873 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
874 case ISD::SELECT: return lowerSELECT(Op, DAG);
875 case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG);
876 case ISD::SETCC: return lowerSETCC(Op, DAG);
877 case ISD::VASTART: return lowerVASTART(Op, DAG);
878 case ISD::VAARG: return lowerVAARG(Op, DAG);
879 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
880 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
881 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
882 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
883 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
884 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
885 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
886 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
887 case ISD::LOAD: return lowerLOAD(Op, DAG);
888 case ISD::STORE: return lowerSTORE(Op, DAG);
889 case ISD::ADD: return lowerADD(Op, DAG);
890 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
891 }
892 return SDValue();
893 }
894
895 //===----------------------------------------------------------------------===//
896 // Lower helper functions
897 //===----------------------------------------------------------------------===//
898
899 // addLiveIn - This helper function adds the specified physical register to the
900 // MachineFunction as a live in value. It also creates a corresponding
901 // virtual register for it.
902 static unsigned
addLiveIn(MachineFunction & MF,unsigned PReg,const TargetRegisterClass * RC)903 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
904 {
905 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
906 MF.getRegInfo().addLiveIn(PReg, VReg);
907 return VReg;
908 }
909
insertDivByZeroTrap(MachineInstr * MI,MachineBasicBlock & MBB,const TargetInstrInfo & TII,bool Is64Bit)910 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr *MI,
911 MachineBasicBlock &MBB,
912 const TargetInstrInfo &TII,
913 bool Is64Bit) {
914 if (NoZeroDivCheck)
915 return &MBB;
916
917 // Insert instruction "teq $divisor_reg, $zero, 7".
918 MachineBasicBlock::iterator I(MI);
919 MachineInstrBuilder MIB;
920 MachineOperand &Divisor = MI->getOperand(2);
921 MIB = BuildMI(MBB, std::next(I), MI->getDebugLoc(), TII.get(Mips::TEQ))
922 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
923 .addReg(Mips::ZERO).addImm(7);
924
925 // Use the 32-bit sub-register if this is a 64-bit division.
926 if (Is64Bit)
927 MIB->getOperand(0).setSubReg(Mips::sub_32);
928
929 // Clear Divisor's kill flag.
930 Divisor.setIsKill(false);
931
932 // We would normally delete the original instruction here but in this case
933 // we only needed to inject an additional instruction rather than replace it.
934
935 return &MBB;
936 }
937
938 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const939 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
940 MachineBasicBlock *BB) const {
941 switch (MI->getOpcode()) {
942 default:
943 llvm_unreachable("Unexpected instr type to insert");
944 case Mips::ATOMIC_LOAD_ADD_I8:
945 return emitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu);
946 case Mips::ATOMIC_LOAD_ADD_I16:
947 return emitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu);
948 case Mips::ATOMIC_LOAD_ADD_I32:
949 return emitAtomicBinary(MI, BB, 4, Mips::ADDu);
950 case Mips::ATOMIC_LOAD_ADD_I64:
951 return emitAtomicBinary(MI, BB, 8, Mips::DADDu);
952
953 case Mips::ATOMIC_LOAD_AND_I8:
954 return emitAtomicBinaryPartword(MI, BB, 1, Mips::AND);
955 case Mips::ATOMIC_LOAD_AND_I16:
956 return emitAtomicBinaryPartword(MI, BB, 2, Mips::AND);
957 case Mips::ATOMIC_LOAD_AND_I32:
958 return emitAtomicBinary(MI, BB, 4, Mips::AND);
959 case Mips::ATOMIC_LOAD_AND_I64:
960 return emitAtomicBinary(MI, BB, 8, Mips::AND64);
961
962 case Mips::ATOMIC_LOAD_OR_I8:
963 return emitAtomicBinaryPartword(MI, BB, 1, Mips::OR);
964 case Mips::ATOMIC_LOAD_OR_I16:
965 return emitAtomicBinaryPartword(MI, BB, 2, Mips::OR);
966 case Mips::ATOMIC_LOAD_OR_I32:
967 return emitAtomicBinary(MI, BB, 4, Mips::OR);
968 case Mips::ATOMIC_LOAD_OR_I64:
969 return emitAtomicBinary(MI, BB, 8, Mips::OR64);
970
971 case Mips::ATOMIC_LOAD_XOR_I8:
972 return emitAtomicBinaryPartword(MI, BB, 1, Mips::XOR);
973 case Mips::ATOMIC_LOAD_XOR_I16:
974 return emitAtomicBinaryPartword(MI, BB, 2, Mips::XOR);
975 case Mips::ATOMIC_LOAD_XOR_I32:
976 return emitAtomicBinary(MI, BB, 4, Mips::XOR);
977 case Mips::ATOMIC_LOAD_XOR_I64:
978 return emitAtomicBinary(MI, BB, 8, Mips::XOR64);
979
980 case Mips::ATOMIC_LOAD_NAND_I8:
981 return emitAtomicBinaryPartword(MI, BB, 1, 0, true);
982 case Mips::ATOMIC_LOAD_NAND_I16:
983 return emitAtomicBinaryPartword(MI, BB, 2, 0, true);
984 case Mips::ATOMIC_LOAD_NAND_I32:
985 return emitAtomicBinary(MI, BB, 4, 0, true);
986 case Mips::ATOMIC_LOAD_NAND_I64:
987 return emitAtomicBinary(MI, BB, 8, 0, true);
988
989 case Mips::ATOMIC_LOAD_SUB_I8:
990 return emitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu);
991 case Mips::ATOMIC_LOAD_SUB_I16:
992 return emitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu);
993 case Mips::ATOMIC_LOAD_SUB_I32:
994 return emitAtomicBinary(MI, BB, 4, Mips::SUBu);
995 case Mips::ATOMIC_LOAD_SUB_I64:
996 return emitAtomicBinary(MI, BB, 8, Mips::DSUBu);
997
998 case Mips::ATOMIC_SWAP_I8:
999 return emitAtomicBinaryPartword(MI, BB, 1, 0);
1000 case Mips::ATOMIC_SWAP_I16:
1001 return emitAtomicBinaryPartword(MI, BB, 2, 0);
1002 case Mips::ATOMIC_SWAP_I32:
1003 return emitAtomicBinary(MI, BB, 4, 0);
1004 case Mips::ATOMIC_SWAP_I64:
1005 return emitAtomicBinary(MI, BB, 8, 0);
1006
1007 case Mips::ATOMIC_CMP_SWAP_I8:
1008 return emitAtomicCmpSwapPartword(MI, BB, 1);
1009 case Mips::ATOMIC_CMP_SWAP_I16:
1010 return emitAtomicCmpSwapPartword(MI, BB, 2);
1011 case Mips::ATOMIC_CMP_SWAP_I32:
1012 return emitAtomicCmpSwap(MI, BB, 4);
1013 case Mips::ATOMIC_CMP_SWAP_I64:
1014 return emitAtomicCmpSwap(MI, BB, 8);
1015 case Mips::PseudoSDIV:
1016 case Mips::PseudoUDIV:
1017 case Mips::DIV:
1018 case Mips::DIVU:
1019 case Mips::MOD:
1020 case Mips::MODU:
1021 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false);
1022 case Mips::PseudoDSDIV:
1023 case Mips::PseudoDUDIV:
1024 case Mips::DDIV:
1025 case Mips::DDIVU:
1026 case Mips::DMOD:
1027 case Mips::DMODU:
1028 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true);
1029 case Mips::SEL_D:
1030 return emitSEL_D(MI, BB);
1031
1032 case Mips::PseudoSELECT_I:
1033 case Mips::PseudoSELECT_I64:
1034 case Mips::PseudoSELECT_S:
1035 case Mips::PseudoSELECT_D32:
1036 case Mips::PseudoSELECT_D64:
1037 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1038 case Mips::PseudoSELECTFP_F_I:
1039 case Mips::PseudoSELECTFP_F_I64:
1040 case Mips::PseudoSELECTFP_F_S:
1041 case Mips::PseudoSELECTFP_F_D32:
1042 case Mips::PseudoSELECTFP_F_D64:
1043 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1044 case Mips::PseudoSELECTFP_T_I:
1045 case Mips::PseudoSELECTFP_T_I64:
1046 case Mips::PseudoSELECTFP_T_S:
1047 case Mips::PseudoSELECTFP_T_D32:
1048 case Mips::PseudoSELECTFP_T_D64:
1049 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1050 }
1051 }
1052
1053 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1054 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1055 MachineBasicBlock *
emitAtomicBinary(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1056 MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
1057 unsigned Size, unsigned BinOpcode,
1058 bool Nand) const {
1059 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicBinary.");
1060
1061 MachineFunction *MF = BB->getParent();
1062 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1063 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1064 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1065 DebugLoc DL = MI->getDebugLoc();
1066 unsigned LL, SC, AND, NOR, ZERO, BEQ;
1067
1068 if (Size == 4) {
1069 if (isMicroMips) {
1070 LL = Mips::LL_MM;
1071 SC = Mips::SC_MM;
1072 } else {
1073 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1074 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1075 }
1076 AND = Mips::AND;
1077 NOR = Mips::NOR;
1078 ZERO = Mips::ZERO;
1079 BEQ = Mips::BEQ;
1080 } else {
1081 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1082 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1083 AND = Mips::AND64;
1084 NOR = Mips::NOR64;
1085 ZERO = Mips::ZERO_64;
1086 BEQ = Mips::BEQ64;
1087 }
1088
1089 unsigned OldVal = MI->getOperand(0).getReg();
1090 unsigned Ptr = MI->getOperand(1).getReg();
1091 unsigned Incr = MI->getOperand(2).getReg();
1092
1093 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1094 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1095 unsigned Success = RegInfo.createVirtualRegister(RC);
1096
1097 // insert new blocks after the current block
1098 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1099 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1100 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1101 MachineFunction::iterator It = ++BB->getIterator();
1102 MF->insert(It, loopMBB);
1103 MF->insert(It, exitMBB);
1104
1105 // Transfer the remainder of BB and its successor edges to exitMBB.
1106 exitMBB->splice(exitMBB->begin(), BB,
1107 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1108 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1109
1110 // thisMBB:
1111 // ...
1112 // fallthrough --> loopMBB
1113 BB->addSuccessor(loopMBB);
1114 loopMBB->addSuccessor(loopMBB);
1115 loopMBB->addSuccessor(exitMBB);
1116
1117 // loopMBB:
1118 // ll oldval, 0(ptr)
1119 // <binop> storeval, oldval, incr
1120 // sc success, storeval, 0(ptr)
1121 // beq success, $0, loopMBB
1122 BB = loopMBB;
1123 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
1124 if (Nand) {
1125 // and andres, oldval, incr
1126 // nor storeval, $0, andres
1127 BuildMI(BB, DL, TII->get(AND), AndRes).addReg(OldVal).addReg(Incr);
1128 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes);
1129 } else if (BinOpcode) {
1130 // <binop> storeval, oldval, incr
1131 BuildMI(BB, DL, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr);
1132 } else {
1133 StoreVal = Incr;
1134 }
1135 BuildMI(BB, DL, TII->get(SC), Success).addReg(StoreVal).addReg(Ptr).addImm(0);
1136 BuildMI(BB, DL, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB);
1137
1138 MI->eraseFromParent(); // The instruction is gone now.
1139
1140 return exitMBB;
1141 }
1142
emitSignExtendToI32InReg(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned DstReg,unsigned SrcReg) const1143 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1144 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1145 unsigned SrcReg) const {
1146 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1147 DebugLoc DL = MI->getDebugLoc();
1148
1149 if (Subtarget.hasMips32r2() && Size == 1) {
1150 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1151 return BB;
1152 }
1153
1154 if (Subtarget.hasMips32r2() && Size == 2) {
1155 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1156 return BB;
1157 }
1158
1159 MachineFunction *MF = BB->getParent();
1160 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1161 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1162 unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1163
1164 assert(Size < 32);
1165 int64_t ShiftImm = 32 - (Size * 8);
1166
1167 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1168 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1169
1170 return BB;
1171 }
1172
emitAtomicBinaryPartword(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size,unsigned BinOpcode,bool Nand) const1173 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1174 MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
1175 bool Nand) const {
1176 assert((Size == 1 || Size == 2) &&
1177 "Unsupported size for EmitAtomicBinaryPartial.");
1178
1179 MachineFunction *MF = BB->getParent();
1180 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1181 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1182 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1183 DebugLoc DL = MI->getDebugLoc();
1184
1185 unsigned Dest = MI->getOperand(0).getReg();
1186 unsigned Ptr = MI->getOperand(1).getReg();
1187 unsigned Incr = MI->getOperand(2).getReg();
1188
1189 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1190 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1191 unsigned Mask = RegInfo.createVirtualRegister(RC);
1192 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1193 unsigned NewVal = RegInfo.createVirtualRegister(RC);
1194 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1195 unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1196 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1197 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1198 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1199 unsigned AndRes = RegInfo.createVirtualRegister(RC);
1200 unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1201 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1202 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1203 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1204 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1205 unsigned Success = RegInfo.createVirtualRegister(RC);
1206
1207 // insert new blocks after the current block
1208 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1209 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1210 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1211 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1212 MachineFunction::iterator It = ++BB->getIterator();
1213 MF->insert(It, loopMBB);
1214 MF->insert(It, sinkMBB);
1215 MF->insert(It, exitMBB);
1216
1217 // Transfer the remainder of BB and its successor edges to exitMBB.
1218 exitMBB->splice(exitMBB->begin(), BB,
1219 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1220 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1221
1222 BB->addSuccessor(loopMBB);
1223 loopMBB->addSuccessor(loopMBB);
1224 loopMBB->addSuccessor(sinkMBB);
1225 sinkMBB->addSuccessor(exitMBB);
1226
1227 // thisMBB:
1228 // addiu masklsb2,$0,-4 # 0xfffffffc
1229 // and alignedaddr,ptr,masklsb2
1230 // andi ptrlsb2,ptr,3
1231 // sll shiftamt,ptrlsb2,3
1232 // ori maskupper,$0,255 # 0xff
1233 // sll mask,maskupper,shiftamt
1234 // nor mask2,$0,mask
1235 // sll incr2,incr,shiftamt
1236
1237 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1238 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1239 .addReg(Mips::ZERO).addImm(-4);
1240 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1241 .addReg(Ptr).addReg(MaskLSB2);
1242 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1243 if (Subtarget.isLittle()) {
1244 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1245 } else {
1246 unsigned Off = RegInfo.createVirtualRegister(RC);
1247 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1248 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1249 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1250 }
1251 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1252 .addReg(Mips::ZERO).addImm(MaskImm);
1253 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1254 .addReg(MaskUpper).addReg(ShiftAmt);
1255 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1256 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1257
1258 // atomic.load.binop
1259 // loopMBB:
1260 // ll oldval,0(alignedaddr)
1261 // binop binopres,oldval,incr2
1262 // and newval,binopres,mask
1263 // and maskedoldval0,oldval,mask2
1264 // or storeval,maskedoldval0,newval
1265 // sc success,storeval,0(alignedaddr)
1266 // beq success,$0,loopMBB
1267
1268 // atomic.swap
1269 // loopMBB:
1270 // ll oldval,0(alignedaddr)
1271 // and newval,incr2,mask
1272 // and maskedoldval0,oldval,mask2
1273 // or storeval,maskedoldval0,newval
1274 // sc success,storeval,0(alignedaddr)
1275 // beq success,$0,loopMBB
1276
1277 BB = loopMBB;
1278 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1279 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1280 if (Nand) {
1281 // and andres, oldval, incr2
1282 // nor binopres, $0, andres
1283 // and newval, binopres, mask
1284 BuildMI(BB, DL, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2);
1285 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes)
1286 .addReg(Mips::ZERO).addReg(AndRes);
1287 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1288 } else if (BinOpcode) {
1289 // <binop> binopres, oldval, incr2
1290 // and newval, binopres, mask
1291 BuildMI(BB, DL, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2);
1292 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask);
1293 } else { // atomic.swap
1294 // and newval, incr2, mask
1295 BuildMI(BB, DL, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask);
1296 }
1297
1298 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1299 .addReg(OldVal).addReg(Mask2);
1300 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1301 .addReg(MaskedOldVal0).addReg(NewVal);
1302 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1303 BuildMI(BB, DL, TII->get(SC), Success)
1304 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1305 BuildMI(BB, DL, TII->get(Mips::BEQ))
1306 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB);
1307
1308 // sinkMBB:
1309 // and maskedoldval1,oldval,mask
1310 // srl srlres,maskedoldval1,shiftamt
1311 // sign_extend dest,srlres
1312 BB = sinkMBB;
1313
1314 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1315 .addReg(OldVal).addReg(Mask);
1316 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1317 .addReg(MaskedOldVal1).addReg(ShiftAmt);
1318 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1319
1320 MI->eraseFromParent(); // The instruction is gone now.
1321
1322 return exitMBB;
1323 }
1324
emitAtomicCmpSwap(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size) const1325 MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI,
1326 MachineBasicBlock *BB,
1327 unsigned Size) const {
1328 assert((Size == 4 || Size == 8) && "Unsupported size for EmitAtomicCmpSwap.");
1329
1330 MachineFunction *MF = BB->getParent();
1331 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1332 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1333 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1334 DebugLoc DL = MI->getDebugLoc();
1335 unsigned LL, SC, ZERO, BNE, BEQ;
1336
1337 if (Size == 4) {
1338 if (isMicroMips) {
1339 LL = Mips::LL_MM;
1340 SC = Mips::SC_MM;
1341 } else {
1342 LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL;
1343 SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC;
1344 }
1345 ZERO = Mips::ZERO;
1346 BNE = Mips::BNE;
1347 BEQ = Mips::BEQ;
1348 } else {
1349 LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
1350 SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
1351 ZERO = Mips::ZERO_64;
1352 BNE = Mips::BNE64;
1353 BEQ = Mips::BEQ64;
1354 }
1355
1356 unsigned Dest = MI->getOperand(0).getReg();
1357 unsigned Ptr = MI->getOperand(1).getReg();
1358 unsigned OldVal = MI->getOperand(2).getReg();
1359 unsigned NewVal = MI->getOperand(3).getReg();
1360
1361 unsigned Success = RegInfo.createVirtualRegister(RC);
1362
1363 // insert new blocks after the current block
1364 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1365 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1366 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1367 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1368 MachineFunction::iterator It = ++BB->getIterator();
1369 MF->insert(It, loop1MBB);
1370 MF->insert(It, loop2MBB);
1371 MF->insert(It, exitMBB);
1372
1373 // Transfer the remainder of BB and its successor edges to exitMBB.
1374 exitMBB->splice(exitMBB->begin(), BB,
1375 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1376 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1377
1378 // thisMBB:
1379 // ...
1380 // fallthrough --> loop1MBB
1381 BB->addSuccessor(loop1MBB);
1382 loop1MBB->addSuccessor(exitMBB);
1383 loop1MBB->addSuccessor(loop2MBB);
1384 loop2MBB->addSuccessor(loop1MBB);
1385 loop2MBB->addSuccessor(exitMBB);
1386
1387 // loop1MBB:
1388 // ll dest, 0(ptr)
1389 // bne dest, oldval, exitMBB
1390 BB = loop1MBB;
1391 BuildMI(BB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
1392 BuildMI(BB, DL, TII->get(BNE))
1393 .addReg(Dest).addReg(OldVal).addMBB(exitMBB);
1394
1395 // loop2MBB:
1396 // sc success, newval, 0(ptr)
1397 // beq success, $0, loop1MBB
1398 BB = loop2MBB;
1399 BuildMI(BB, DL, TII->get(SC), Success)
1400 .addReg(NewVal).addReg(Ptr).addImm(0);
1401 BuildMI(BB, DL, TII->get(BEQ))
1402 .addReg(Success).addReg(ZERO).addMBB(loop1MBB);
1403
1404 MI->eraseFromParent(); // The instruction is gone now.
1405
1406 return exitMBB;
1407 }
1408
1409 MachineBasicBlock *
emitAtomicCmpSwapPartword(MachineInstr * MI,MachineBasicBlock * BB,unsigned Size) const1410 MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI,
1411 MachineBasicBlock *BB,
1412 unsigned Size) const {
1413 assert((Size == 1 || Size == 2) &&
1414 "Unsupported size for EmitAtomicCmpSwapPartial.");
1415
1416 MachineFunction *MF = BB->getParent();
1417 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1418 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1419 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1420 DebugLoc DL = MI->getDebugLoc();
1421
1422 unsigned Dest = MI->getOperand(0).getReg();
1423 unsigned Ptr = MI->getOperand(1).getReg();
1424 unsigned CmpVal = MI->getOperand(2).getReg();
1425 unsigned NewVal = MI->getOperand(3).getReg();
1426
1427 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC);
1428 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1429 unsigned Mask = RegInfo.createVirtualRegister(RC);
1430 unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1431 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1432 unsigned OldVal = RegInfo.createVirtualRegister(RC);
1433 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1434 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1435 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC);
1436 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1437 unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1438 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1439 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1440 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1441 unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1442 unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1443 unsigned Success = RegInfo.createVirtualRegister(RC);
1444
1445 // insert new blocks after the current block
1446 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1447 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1448 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
1449 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1450 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1451 MachineFunction::iterator It = ++BB->getIterator();
1452 MF->insert(It, loop1MBB);
1453 MF->insert(It, loop2MBB);
1454 MF->insert(It, sinkMBB);
1455 MF->insert(It, exitMBB);
1456
1457 // Transfer the remainder of BB and its successor edges to exitMBB.
1458 exitMBB->splice(exitMBB->begin(), BB,
1459 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1460 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1461
1462 BB->addSuccessor(loop1MBB);
1463 loop1MBB->addSuccessor(sinkMBB);
1464 loop1MBB->addSuccessor(loop2MBB);
1465 loop2MBB->addSuccessor(loop1MBB);
1466 loop2MBB->addSuccessor(sinkMBB);
1467 sinkMBB->addSuccessor(exitMBB);
1468
1469 // FIXME: computation of newval2 can be moved to loop2MBB.
1470 // thisMBB:
1471 // addiu masklsb2,$0,-4 # 0xfffffffc
1472 // and alignedaddr,ptr,masklsb2
1473 // andi ptrlsb2,ptr,3
1474 // sll shiftamt,ptrlsb2,3
1475 // ori maskupper,$0,255 # 0xff
1476 // sll mask,maskupper,shiftamt
1477 // nor mask2,$0,mask
1478 // andi maskedcmpval,cmpval,255
1479 // sll shiftedcmpval,maskedcmpval,shiftamt
1480 // andi maskednewval,newval,255
1481 // sll shiftednewval,maskednewval,shiftamt
1482 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1483 BuildMI(BB, DL, TII->get(Mips::ADDiu), MaskLSB2)
1484 .addReg(Mips::ZERO).addImm(-4);
1485 BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr)
1486 .addReg(Ptr).addReg(MaskLSB2);
1487 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3);
1488 if (Subtarget.isLittle()) {
1489 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1490 } else {
1491 unsigned Off = RegInfo.createVirtualRegister(RC);
1492 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1493 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1494 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1495 }
1496 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1497 .addReg(Mips::ZERO).addImm(MaskImm);
1498 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1499 .addReg(MaskUpper).addReg(ShiftAmt);
1500 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1501 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1502 .addReg(CmpVal).addImm(MaskImm);
1503 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1504 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1505 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1506 .addReg(NewVal).addImm(MaskImm);
1507 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1508 .addReg(MaskedNewVal).addReg(ShiftAmt);
1509
1510 // loop1MBB:
1511 // ll oldval,0(alginedaddr)
1512 // and maskedoldval0,oldval,mask
1513 // bne maskedoldval0,shiftedcmpval,sinkMBB
1514 BB = loop1MBB;
1515 unsigned LL = isMicroMips ? Mips::LL_MM : Mips::LL;
1516 BuildMI(BB, DL, TII->get(LL), OldVal).addReg(AlignedAddr).addImm(0);
1517 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal0)
1518 .addReg(OldVal).addReg(Mask);
1519 BuildMI(BB, DL, TII->get(Mips::BNE))
1520 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB);
1521
1522 // loop2MBB:
1523 // and maskedoldval1,oldval,mask2
1524 // or storeval,maskedoldval1,shiftednewval
1525 // sc success,storeval,0(alignedaddr)
1526 // beq success,$0,loop1MBB
1527 BB = loop2MBB;
1528 BuildMI(BB, DL, TII->get(Mips::AND), MaskedOldVal1)
1529 .addReg(OldVal).addReg(Mask2);
1530 BuildMI(BB, DL, TII->get(Mips::OR), StoreVal)
1531 .addReg(MaskedOldVal1).addReg(ShiftedNewVal);
1532 unsigned SC = isMicroMips ? Mips::SC_MM : Mips::SC;
1533 BuildMI(BB, DL, TII->get(SC), Success)
1534 .addReg(StoreVal).addReg(AlignedAddr).addImm(0);
1535 BuildMI(BB, DL, TII->get(Mips::BEQ))
1536 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB);
1537
1538 // sinkMBB:
1539 // srl srlres,maskedoldval0,shiftamt
1540 // sign_extend dest,srlres
1541 BB = sinkMBB;
1542
1543 BuildMI(BB, DL, TII->get(Mips::SRLV), SrlRes)
1544 .addReg(MaskedOldVal0).addReg(ShiftAmt);
1545 BB = emitSignExtendToI32InReg(MI, BB, Size, Dest, SrlRes);
1546
1547 MI->eraseFromParent(); // The instruction is gone now.
1548
1549 return exitMBB;
1550 }
1551
emitSEL_D(MachineInstr * MI,MachineBasicBlock * BB) const1552 MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI,
1553 MachineBasicBlock *BB) const {
1554 MachineFunction *MF = BB->getParent();
1555 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1556 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1557 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1558 DebugLoc DL = MI->getDebugLoc();
1559 MachineBasicBlock::iterator II(MI);
1560
1561 unsigned Fc = MI->getOperand(1).getReg();
1562 const auto &FGR64RegClass = TRI->getRegClass(Mips::FGR64RegClassID);
1563
1564 unsigned Fc2 = RegInfo.createVirtualRegister(FGR64RegClass);
1565
1566 BuildMI(*BB, II, DL, TII->get(Mips::SUBREG_TO_REG), Fc2)
1567 .addImm(0)
1568 .addReg(Fc)
1569 .addImm(Mips::sub_lo);
1570
1571 // We don't erase the original instruction, we just replace the condition
1572 // register with the 64-bit super-register.
1573 MI->getOperand(1).setReg(Fc2);
1574
1575 return BB;
1576 }
1577
1578 //===----------------------------------------------------------------------===//
1579 // Misc Lower Operation implementation
1580 //===----------------------------------------------------------------------===//
lowerBR_JT(SDValue Op,SelectionDAG & DAG) const1581 SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
1582 SDValue Chain = Op.getOperand(0);
1583 SDValue Table = Op.getOperand(1);
1584 SDValue Index = Op.getOperand(2);
1585 SDLoc DL(Op);
1586 auto &TD = DAG.getDataLayout();
1587 EVT PTy = getPointerTy(TD);
1588 unsigned EntrySize =
1589 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
1590
1591 Index = DAG.getNode(ISD::MUL, DL, PTy, Index,
1592 DAG.getConstant(EntrySize, DL, PTy));
1593 SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table);
1594
1595 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
1596 Addr =
1597 DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr,
1598 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
1599 MemVT, false, false, false, 0);
1600 Chain = Addr.getValue(1);
1601
1602 if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || ABI.IsN64()) {
1603 // For PIC, the sequence is:
1604 // BRIND(load(Jumptable + index) + RelocBase)
1605 // RelocBase can be JumpTable, GOT or some sort of global base.
1606 Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr,
1607 getPICJumpTableRelocBase(Table, DAG));
1608 }
1609
1610 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr);
1611 }
1612
lowerBRCOND(SDValue Op,SelectionDAG & DAG) const1613 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1614 // The first operand is the chain, the second is the condition, the third is
1615 // the block to branch to if the condition is true.
1616 SDValue Chain = Op.getOperand(0);
1617 SDValue Dest = Op.getOperand(2);
1618 SDLoc DL(Op);
1619
1620 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1621 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1622
1623 // Return if flag is not set by a floating point comparison.
1624 if (CondRes.getOpcode() != MipsISD::FPCmp)
1625 return Op;
1626
1627 SDValue CCNode = CondRes.getOperand(2);
1628 Mips::CondCode CC =
1629 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1630 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1631 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1632 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1633 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1634 FCC0, Dest, CondRes);
1635 }
1636
1637 SDValue MipsTargetLowering::
lowerSELECT(SDValue Op,SelectionDAG & DAG) const1638 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1639 {
1640 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1641 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1642
1643 // Return if flag is not set by a floating point comparison.
1644 if (Cond.getOpcode() != MipsISD::FPCmp)
1645 return Op;
1646
1647 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1648 SDLoc(Op));
1649 }
1650
1651 SDValue MipsTargetLowering::
lowerSELECT_CC(SDValue Op,SelectionDAG & DAG) const1652 lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
1653 {
1654 SDLoc DL(Op);
1655 EVT Ty = Op.getOperand(0).getValueType();
1656 SDValue Cond =
1657 DAG.getNode(ISD::SETCC, DL, getSetCCResultType(DAG.getDataLayout(),
1658 *DAG.getContext(), Ty),
1659 Op.getOperand(0), Op.getOperand(1), Op.getOperand(4));
1660
1661 return DAG.getNode(ISD::SELECT, DL, Op.getValueType(), Cond, Op.getOperand(2),
1662 Op.getOperand(3));
1663 }
1664
lowerSETCC(SDValue Op,SelectionDAG & DAG) const1665 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1666 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1667 SDValue Cond = createFPCmp(DAG, Op);
1668
1669 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1670 "Floating point operand expected.");
1671
1672 SDLoc DL(Op);
1673 SDValue True = DAG.getConstant(1, DL, MVT::i32);
1674 SDValue False = DAG.getConstant(0, DL, MVT::i32);
1675
1676 return createCMovFP(DAG, Cond, True, False, DL);
1677 }
1678
lowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1679 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1680 SelectionDAG &DAG) const {
1681 EVT Ty = Op.getValueType();
1682 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1683 const GlobalValue *GV = N->getGlobal();
1684
1685 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1686 const MipsTargetObjectFile *TLOF =
1687 static_cast<const MipsTargetObjectFile *>(
1688 getTargetMachine().getObjFileLowering());
1689 if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine()))
1690 // %gp_rel relocation
1691 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1692
1693 // %hi/%lo relocation
1694 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1695 }
1696
1697 if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV)))
1698 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1699
1700 if (LargeGOT)
1701 return getAddrGlobalLargeGOT(
1702 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1703 DAG.getEntryNode(),
1704 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1705
1706 return getAddrGlobal(
1707 N, SDLoc(N), Ty, DAG,
1708 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16,
1709 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1710 }
1711
lowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1712 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
1713 SelectionDAG &DAG) const {
1714 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
1715 EVT Ty = Op.getValueType();
1716
1717 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1718 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1719
1720 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1721 }
1722
1723 SDValue MipsTargetLowering::
lowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1724 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
1725 {
1726 // If the relocation model is PIC, use the General Dynamic TLS Model or
1727 // Local Dynamic TLS model, otherwise use the Initial Exec or
1728 // Local Exec TLS Model.
1729
1730 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1731 if (DAG.getTarget().Options.EmulatedTLS)
1732 return LowerToTLSEmulatedModel(GA, DAG);
1733
1734 SDLoc DL(GA);
1735 const GlobalValue *GV = GA->getGlobal();
1736 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1737
1738 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1739
1740 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1741 // General Dynamic and Local Dynamic TLS Model.
1742 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
1743 : MipsII::MO_TLSGD;
1744
1745 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
1746 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
1747 getGlobalReg(DAG, PtrVT), TGA);
1748 unsigned PtrSize = PtrVT.getSizeInBits();
1749 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
1750
1751 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
1752
1753 ArgListTy Args;
1754 ArgListEntry Entry;
1755 Entry.Node = Argument;
1756 Entry.Ty = PtrTy;
1757 Args.push_back(Entry);
1758
1759 TargetLowering::CallLoweringInfo CLI(DAG);
1760 CLI.setDebugLoc(DL).setChain(DAG.getEntryNode())
1761 .setCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args), 0);
1762 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1763
1764 SDValue Ret = CallResult.first;
1765
1766 if (model != TLSModel::LocalDynamic)
1767 return Ret;
1768
1769 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1770 MipsII::MO_DTPREL_HI);
1771 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1772 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1773 MipsII::MO_DTPREL_LO);
1774 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1775 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
1776 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
1777 }
1778
1779 SDValue Offset;
1780 if (model == TLSModel::InitialExec) {
1781 // Initial Exec TLS Model
1782 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1783 MipsII::MO_GOTTPREL);
1784 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
1785 TGA);
1786 Offset = DAG.getLoad(PtrVT, DL,
1787 DAG.getEntryNode(), TGA, MachinePointerInfo(),
1788 false, false, false, 0);
1789 } else {
1790 // Local Exec TLS Model
1791 assert(model == TLSModel::LocalExec);
1792 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1793 MipsII::MO_TPREL_HI);
1794 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
1795 MipsII::MO_TPREL_LO);
1796 SDValue Hi = DAG.getNode(MipsISD::Hi, DL, PtrVT, TGAHi);
1797 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
1798 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1799 }
1800
1801 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
1802 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
1803 }
1804
1805 SDValue MipsTargetLowering::
lowerJumpTable(SDValue Op,SelectionDAG & DAG) const1806 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
1807 {
1808 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
1809 EVT Ty = Op.getValueType();
1810
1811 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64())
1812 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1813
1814 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1815 }
1816
1817 SDValue MipsTargetLowering::
lowerConstantPool(SDValue Op,SelectionDAG & DAG) const1818 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
1819 {
1820 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
1821 EVT Ty = Op.getValueType();
1822
1823 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !ABI.IsN64()) {
1824 const MipsTargetObjectFile *TLOF =
1825 static_cast<const MipsTargetObjectFile *>(
1826 getTargetMachine().getObjFileLowering());
1827
1828 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
1829 getTargetMachine()))
1830 // %gp_rel relocation
1831 return getAddrGPRel(N, SDLoc(N), Ty, DAG);
1832
1833 return getAddrNonPIC(N, SDLoc(N), Ty, DAG);
1834 }
1835
1836 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1837 }
1838
lowerVASTART(SDValue Op,SelectionDAG & DAG) const1839 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1840 MachineFunction &MF = DAG.getMachineFunction();
1841 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
1842
1843 SDLoc DL(Op);
1844 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1845 getPointerTy(MF.getDataLayout()));
1846
1847 // vastart just stores the address of the VarArgsFrameIndex slot into the
1848 // memory location argument.
1849 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1850 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
1851 MachinePointerInfo(SV), false, false, 0);
1852 }
1853
lowerVAARG(SDValue Op,SelectionDAG & DAG) const1854 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
1855 SDNode *Node = Op.getNode();
1856 EVT VT = Node->getValueType(0);
1857 SDValue Chain = Node->getOperand(0);
1858 SDValue VAListPtr = Node->getOperand(1);
1859 unsigned Align = Node->getConstantOperandVal(3);
1860 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1861 SDLoc DL(Node);
1862 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
1863
1864 SDValue VAListLoad =
1865 DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain, VAListPtr,
1866 MachinePointerInfo(SV), false, false, false, 0);
1867 SDValue VAList = VAListLoad;
1868
1869 // Re-align the pointer if necessary.
1870 // It should only ever be necessary for 64-bit types on O32 since the minimum
1871 // argument alignment is the same as the maximum type alignment for N32/N64.
1872 //
1873 // FIXME: We currently align too often. The code generator doesn't notice
1874 // when the pointer is still aligned from the last va_arg (or pair of
1875 // va_args for the i64 on O32 case).
1876 if (Align > getMinStackArgumentAlignment()) {
1877 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
1878
1879 VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1880 DAG.getConstant(Align - 1, DL, VAList.getValueType()));
1881
1882 VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList,
1883 DAG.getConstant(-(int64_t)Align, DL,
1884 VAList.getValueType()));
1885 }
1886
1887 // Increment the pointer, VAList, to the next vaarg.
1888 auto &TD = DAG.getDataLayout();
1889 unsigned ArgSizeInBytes =
1890 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
1891 SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
1892 DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes,
1893 ArgSlotSizeInBytes),
1894 DL, VAList.getValueType()));
1895 // Store the incremented VAList to the legalized pointer
1896 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
1897 MachinePointerInfo(SV), false, false, 0);
1898
1899 // In big-endian mode we must adjust the pointer when the load size is smaller
1900 // than the argument slot size. We must also reduce the known alignment to
1901 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
1902 // the correct half of the slot, and reduce the alignment from 8 (slot
1903 // alignment) down to 4 (type alignment).
1904 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
1905 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
1906 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
1907 DAG.getIntPtrConstant(Adjustment, DL));
1908 }
1909 // Load the actual argument out of the pointer VAList
1910 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false,
1911 false, 0);
1912 }
1913
lowerFCOPYSIGN32(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)1914 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
1915 bool HasExtractInsert) {
1916 EVT TyX = Op.getOperand(0).getValueType();
1917 EVT TyY = Op.getOperand(1).getValueType();
1918 SDLoc DL(Op);
1919 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1920 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
1921 SDValue Res;
1922
1923 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
1924 // to i32.
1925 SDValue X = (TyX == MVT::f32) ?
1926 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
1927 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
1928 Const1);
1929 SDValue Y = (TyY == MVT::f32) ?
1930 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
1931 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
1932 Const1);
1933
1934 if (HasExtractInsert) {
1935 // ext E, Y, 31, 1 ; extract bit31 of Y
1936 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
1937 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
1938 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
1939 } else {
1940 // sll SllX, X, 1
1941 // srl SrlX, SllX, 1
1942 // srl SrlY, Y, 31
1943 // sll SllY, SrlX, 31
1944 // or Or, SrlX, SllY
1945 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
1946 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
1947 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
1948 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
1949 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
1950 }
1951
1952 if (TyX == MVT::f32)
1953 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
1954
1955 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
1956 Op.getOperand(0),
1957 DAG.getConstant(0, DL, MVT::i32));
1958 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
1959 }
1960
lowerFCOPYSIGN64(SDValue Op,SelectionDAG & DAG,bool HasExtractInsert)1961 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
1962 bool HasExtractInsert) {
1963 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
1964 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
1965 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
1966 SDLoc DL(Op);
1967 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
1968
1969 // Bitcast to integer nodes.
1970 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
1971 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
1972
1973 if (HasExtractInsert) {
1974 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
1975 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
1976 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
1977 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
1978
1979 if (WidthX > WidthY)
1980 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
1981 else if (WidthY > WidthX)
1982 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
1983
1984 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
1985 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
1986 X);
1987 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
1988 }
1989
1990 // (d)sll SllX, X, 1
1991 // (d)srl SrlX, SllX, 1
1992 // (d)srl SrlY, Y, width(Y)-1
1993 // (d)sll SllY, SrlX, width(Y)-1
1994 // or Or, SrlX, SllY
1995 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
1996 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
1997 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
1998 DAG.getConstant(WidthY - 1, DL, MVT::i32));
1999
2000 if (WidthX > WidthY)
2001 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2002 else if (WidthY > WidthX)
2003 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2004
2005 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2006 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2007 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2008 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2009 }
2010
2011 SDValue
lowerFCOPYSIGN(SDValue Op,SelectionDAG & DAG) const2012 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2013 if (Subtarget.isGP64bit())
2014 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2015
2016 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2017 }
2018
2019 SDValue MipsTargetLowering::
lowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const2020 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2021 // check the depth
2022 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2023 "Frame address can only be determined for current frame.");
2024
2025 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2026 MFI->setFrameAddressIsTaken(true);
2027 EVT VT = Op.getValueType();
2028 SDLoc DL(Op);
2029 SDValue FrameAddr = DAG.getCopyFromReg(
2030 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2031 return FrameAddr;
2032 }
2033
lowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const2034 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2035 SelectionDAG &DAG) const {
2036 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2037 return SDValue();
2038
2039 // check the depth
2040 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
2041 "Return address can be determined only for current frame.");
2042
2043 MachineFunction &MF = DAG.getMachineFunction();
2044 MachineFrameInfo *MFI = MF.getFrameInfo();
2045 MVT VT = Op.getSimpleValueType();
2046 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2047 MFI->setReturnAddressIsTaken(true);
2048
2049 // Return RA, which contains the return address. Mark it an implicit live-in.
2050 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2051 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2052 }
2053
2054 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2055 // generated from __builtin_eh_return (offset, handler)
2056 // The effect of this is to adjust the stack pointer by "offset"
2057 // and then branch to "handler".
lowerEH_RETURN(SDValue Op,SelectionDAG & DAG) const2058 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2059 const {
2060 MachineFunction &MF = DAG.getMachineFunction();
2061 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2062
2063 MipsFI->setCallsEhReturn();
2064 SDValue Chain = Op.getOperand(0);
2065 SDValue Offset = Op.getOperand(1);
2066 SDValue Handler = Op.getOperand(2);
2067 SDLoc DL(Op);
2068 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2069
2070 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2071 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2072 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2073 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2074 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2075 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2076 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2077 DAG.getRegister(OffsetReg, Ty),
2078 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2079 Chain.getValue(1));
2080 }
2081
lowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const2082 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2083 SelectionDAG &DAG) const {
2084 // FIXME: Need pseudo-fence for 'singlethread' fences
2085 // FIXME: Set SType for weaker fences where supported/appropriate.
2086 unsigned SType = 0;
2087 SDLoc DL(Op);
2088 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2089 DAG.getConstant(SType, DL, MVT::i32));
2090 }
2091
lowerShiftLeftParts(SDValue Op,SelectionDAG & DAG) const2092 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2093 SelectionDAG &DAG) const {
2094 SDLoc DL(Op);
2095 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2096
2097 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2098 SDValue Shamt = Op.getOperand(2);
2099 // if shamt < (VT.bits):
2100 // lo = (shl lo, shamt)
2101 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2102 // else:
2103 // lo = 0
2104 // hi = (shl lo, shamt[4:0])
2105 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2106 DAG.getConstant(-1, DL, MVT::i32));
2107 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2108 DAG.getConstant(1, DL, VT));
2109 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2110 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2111 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2112 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2113 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2114 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2115 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2116 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2117 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2118
2119 SDValue Ops[2] = {Lo, Hi};
2120 return DAG.getMergeValues(Ops, DL);
2121 }
2122
lowerShiftRightParts(SDValue Op,SelectionDAG & DAG,bool IsSRA) const2123 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2124 bool IsSRA) const {
2125 SDLoc DL(Op);
2126 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2127 SDValue Shamt = Op.getOperand(2);
2128 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2129
2130 // if shamt < (VT.bits):
2131 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2132 // if isSRA:
2133 // hi = (sra hi, shamt)
2134 // else:
2135 // hi = (srl hi, shamt)
2136 // else:
2137 // if isSRA:
2138 // lo = (sra hi, shamt[4:0])
2139 // hi = (sra hi, 31)
2140 // else:
2141 // lo = (srl hi, shamt[4:0])
2142 // hi = 0
2143 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2144 DAG.getConstant(-1, DL, MVT::i32));
2145 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2146 DAG.getConstant(1, DL, VT));
2147 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2148 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2149 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2150 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2151 DL, VT, Hi, Shamt);
2152 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2153 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2154 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2155 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2156 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2157 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2158 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2159
2160 SDValue Ops[2] = {Lo, Hi};
2161 return DAG.getMergeValues(Ops, DL);
2162 }
2163
createLoadLR(unsigned Opc,SelectionDAG & DAG,LoadSDNode * LD,SDValue Chain,SDValue Src,unsigned Offset)2164 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2165 SDValue Chain, SDValue Src, unsigned Offset) {
2166 SDValue Ptr = LD->getBasePtr();
2167 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2168 EVT BasePtrVT = Ptr.getValueType();
2169 SDLoc DL(LD);
2170 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2171
2172 if (Offset)
2173 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2174 DAG.getConstant(Offset, DL, BasePtrVT));
2175
2176 SDValue Ops[] = { Chain, Ptr, Src };
2177 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2178 LD->getMemOperand());
2179 }
2180
2181 // Expand an unaligned 32 or 64-bit integer load node.
lowerLOAD(SDValue Op,SelectionDAG & DAG) const2182 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2183 LoadSDNode *LD = cast<LoadSDNode>(Op);
2184 EVT MemVT = LD->getMemoryVT();
2185
2186 if (Subtarget.systemSupportsUnalignedAccess())
2187 return Op;
2188
2189 // Return if load is aligned or if MemVT is neither i32 nor i64.
2190 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2191 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2192 return SDValue();
2193
2194 bool IsLittle = Subtarget.isLittle();
2195 EVT VT = Op.getValueType();
2196 ISD::LoadExtType ExtType = LD->getExtensionType();
2197 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2198
2199 assert((VT == MVT::i32) || (VT == MVT::i64));
2200
2201 // Expand
2202 // (set dst, (i64 (load baseptr)))
2203 // to
2204 // (set tmp, (ldl (add baseptr, 7), undef))
2205 // (set dst, (ldr baseptr, tmp))
2206 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2207 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2208 IsLittle ? 7 : 0);
2209 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2210 IsLittle ? 0 : 7);
2211 }
2212
2213 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2214 IsLittle ? 3 : 0);
2215 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2216 IsLittle ? 0 : 3);
2217
2218 // Expand
2219 // (set dst, (i32 (load baseptr))) or
2220 // (set dst, (i64 (sextload baseptr))) or
2221 // (set dst, (i64 (extload baseptr)))
2222 // to
2223 // (set tmp, (lwl (add baseptr, 3), undef))
2224 // (set dst, (lwr baseptr, tmp))
2225 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2226 (ExtType == ISD::EXTLOAD))
2227 return LWR;
2228
2229 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2230
2231 // Expand
2232 // (set dst, (i64 (zextload baseptr)))
2233 // to
2234 // (set tmp0, (lwl (add baseptr, 3), undef))
2235 // (set tmp1, (lwr baseptr, tmp0))
2236 // (set tmp2, (shl tmp1, 32))
2237 // (set dst, (srl tmp2, 32))
2238 SDLoc DL(LD);
2239 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2240 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2241 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2242 SDValue Ops[] = { SRL, LWR.getValue(1) };
2243 return DAG.getMergeValues(Ops, DL);
2244 }
2245
createStoreLR(unsigned Opc,SelectionDAG & DAG,StoreSDNode * SD,SDValue Chain,unsigned Offset)2246 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2247 SDValue Chain, unsigned Offset) {
2248 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2249 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2250 SDLoc DL(SD);
2251 SDVTList VTList = DAG.getVTList(MVT::Other);
2252
2253 if (Offset)
2254 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2255 DAG.getConstant(Offset, DL, BasePtrVT));
2256
2257 SDValue Ops[] = { Chain, Value, Ptr };
2258 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2259 SD->getMemOperand());
2260 }
2261
2262 // Expand an unaligned 32 or 64-bit integer store node.
lowerUnalignedIntStore(StoreSDNode * SD,SelectionDAG & DAG,bool IsLittle)2263 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2264 bool IsLittle) {
2265 SDValue Value = SD->getValue(), Chain = SD->getChain();
2266 EVT VT = Value.getValueType();
2267
2268 // Expand
2269 // (store val, baseptr) or
2270 // (truncstore val, baseptr)
2271 // to
2272 // (swl val, (add baseptr, 3))
2273 // (swr val, baseptr)
2274 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2275 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2276 IsLittle ? 3 : 0);
2277 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2278 }
2279
2280 assert(VT == MVT::i64);
2281
2282 // Expand
2283 // (store val, baseptr)
2284 // to
2285 // (sdl val, (add baseptr, 7))
2286 // (sdr val, baseptr)
2287 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2288 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2289 }
2290
2291 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
lowerFP_TO_SINT_STORE(StoreSDNode * SD,SelectionDAG & DAG)2292 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG) {
2293 SDValue Val = SD->getValue();
2294
2295 if (Val.getOpcode() != ISD::FP_TO_SINT)
2296 return SDValue();
2297
2298 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2299 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2300 Val.getOperand(0));
2301
2302 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2303 SD->getPointerInfo(), SD->isVolatile(),
2304 SD->isNonTemporal(), SD->getAlignment());
2305 }
2306
lowerSTORE(SDValue Op,SelectionDAG & DAG) const2307 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2308 StoreSDNode *SD = cast<StoreSDNode>(Op);
2309 EVT MemVT = SD->getMemoryVT();
2310
2311 // Lower unaligned integer stores.
2312 if (!Subtarget.systemSupportsUnalignedAccess() &&
2313 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2314 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2315 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2316
2317 return lowerFP_TO_SINT_STORE(SD, DAG);
2318 }
2319
lowerADD(SDValue Op,SelectionDAG & DAG) const2320 SDValue MipsTargetLowering::lowerADD(SDValue Op, SelectionDAG &DAG) const {
2321 if (Op->getOperand(0).getOpcode() != ISD::FRAMEADDR
2322 || cast<ConstantSDNode>
2323 (Op->getOperand(0).getOperand(0))->getZExtValue() != 0
2324 || Op->getOperand(1).getOpcode() != ISD::FRAME_TO_ARGS_OFFSET)
2325 return SDValue();
2326
2327 // The pattern
2328 // (add (frameaddr 0), (frame_to_args_offset))
2329 // results from lowering llvm.eh.dwarf.cfa intrinsic. Transform it to
2330 // (add FrameObject, 0)
2331 // where FrameObject is a fixed StackObject with offset 0 which points to
2332 // the old stack pointer.
2333 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2334 EVT ValTy = Op->getValueType(0);
2335 int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2336 SDValue InArgsAddr = DAG.getFrameIndex(FI, ValTy);
2337 SDLoc DL(Op);
2338 return DAG.getNode(ISD::ADD, DL, ValTy, InArgsAddr,
2339 DAG.getConstant(0, DL, ValTy));
2340 }
2341
lowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG) const2342 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2343 SelectionDAG &DAG) const {
2344 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2345 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2346 Op.getOperand(0));
2347 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2348 }
2349
2350 //===----------------------------------------------------------------------===//
2351 // Calling Convention Implementation
2352 //===----------------------------------------------------------------------===//
2353
2354 //===----------------------------------------------------------------------===//
2355 // TODO: Implement a generic logic using tblgen that can support this.
2356 // Mips O32 ABI rules:
2357 // ---
2358 // i32 - Passed in A0, A1, A2, A3 and stack
2359 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2360 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2361 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2362 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2363 // not used, it must be shadowed. If only A3 is available, shadow it and
2364 // go to stack.
2365 //
2366 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2367 //===----------------------------------------------------------------------===//
2368
CC_MipsO32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State,ArrayRef<MCPhysReg> F64Regs)2369 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2370 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2371 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2372 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2373 State.getMachineFunction().getSubtarget());
2374
2375 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2376 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2377
2378 // Do not process byval args here.
2379 if (ArgFlags.isByVal())
2380 return true;
2381
2382 // Promote i8 and i16
2383 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2384 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2385 LocVT = MVT::i32;
2386 if (ArgFlags.isSExt())
2387 LocInfo = CCValAssign::SExtUpper;
2388 else if (ArgFlags.isZExt())
2389 LocInfo = CCValAssign::ZExtUpper;
2390 else
2391 LocInfo = CCValAssign::AExtUpper;
2392 }
2393 }
2394
2395 // Promote i8 and i16
2396 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2397 LocVT = MVT::i32;
2398 if (ArgFlags.isSExt())
2399 LocInfo = CCValAssign::SExt;
2400 else if (ArgFlags.isZExt())
2401 LocInfo = CCValAssign::ZExt;
2402 else
2403 LocInfo = CCValAssign::AExt;
2404 }
2405
2406 unsigned Reg;
2407
2408 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2409 // is true: function is vararg, argument is 3rd or higher, there is previous
2410 // argument which is not f32 or f64.
2411 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2412 State.getFirstUnallocated(F32Regs) != ValNo;
2413 unsigned OrigAlign = ArgFlags.getOrigAlign();
2414 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2415
2416 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2417 Reg = State.AllocateReg(IntRegs);
2418 // If this is the first part of an i64 arg,
2419 // the allocated register must be either A0 or A2.
2420 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2421 Reg = State.AllocateReg(IntRegs);
2422 LocVT = MVT::i32;
2423 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2424 // Allocate int register and shadow next int register. If first
2425 // available register is Mips::A1 or Mips::A3, shadow it too.
2426 Reg = State.AllocateReg(IntRegs);
2427 if (Reg == Mips::A1 || Reg == Mips::A3)
2428 Reg = State.AllocateReg(IntRegs);
2429 State.AllocateReg(IntRegs);
2430 LocVT = MVT::i32;
2431 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2432 // we are guaranteed to find an available float register
2433 if (ValVT == MVT::f32) {
2434 Reg = State.AllocateReg(F32Regs);
2435 // Shadow int register
2436 State.AllocateReg(IntRegs);
2437 } else {
2438 Reg = State.AllocateReg(F64Regs);
2439 // Shadow int registers
2440 unsigned Reg2 = State.AllocateReg(IntRegs);
2441 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2442 State.AllocateReg(IntRegs);
2443 State.AllocateReg(IntRegs);
2444 }
2445 } else
2446 llvm_unreachable("Cannot handle this ValVT.");
2447
2448 if (!Reg) {
2449 unsigned Offset = State.AllocateStack(ValVT.getSizeInBits() >> 3,
2450 OrigAlign);
2451 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2452 } else
2453 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2454
2455 return false;
2456 }
2457
CC_MipsO32_FP32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2458 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2459 MVT LocVT, CCValAssign::LocInfo LocInfo,
2460 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2461 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2462
2463 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2464 }
2465
CC_MipsO32_FP64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)2466 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2467 MVT LocVT, CCValAssign::LocInfo LocInfo,
2468 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2469 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2470
2471 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2472 }
2473
2474 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2475 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2476 CCState &State) LLVM_ATTRIBUTE_UNUSED;
2477
2478 #include "MipsGenCallingConv.inc"
2479
2480 //===----------------------------------------------------------------------===//
2481 // Call Calling Convention Implementation
2482 //===----------------------------------------------------------------------===//
2483
2484 // Return next O32 integer argument register.
getNextIntArgReg(unsigned Reg)2485 static unsigned getNextIntArgReg(unsigned Reg) {
2486 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2487 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2488 }
2489
2490 SDValue
passArgOnStack(SDValue StackPtr,unsigned Offset,SDValue Chain,SDValue Arg,SDLoc DL,bool IsTailCall,SelectionDAG & DAG) const2491 MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2492 SDValue Chain, SDValue Arg, SDLoc DL,
2493 bool IsTailCall, SelectionDAG &DAG) const {
2494 if (!IsTailCall) {
2495 SDValue PtrOff =
2496 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2497 DAG.getIntPtrConstant(Offset, DL));
2498 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo(), false,
2499 false, 0);
2500 }
2501
2502 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2503 int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2504 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2505 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2506 /*isVolatile=*/ true, false, 0);
2507 }
2508
2509 void MipsTargetLowering::
getOpndList(SmallVectorImpl<SDValue> & Ops,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,bool IsPICCall,bool GlobalOrExternal,bool InternalLinkage,bool IsCallReloc,CallLoweringInfo & CLI,SDValue Callee,SDValue Chain) const2510 getOpndList(SmallVectorImpl<SDValue> &Ops,
2511 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
2512 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2513 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2514 SDValue Chain) const {
2515 // Insert node "GP copy globalreg" before call to function.
2516 //
2517 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2518 // in PIC mode) allow symbols to be resolved via lazy binding.
2519 // The lazy binding stub requires GP to point to the GOT.
2520 // Note that we don't need GP to point to the GOT for indirect calls
2521 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2522 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2523 // used for the function (that is, Mips linker doesn't generate lazy binding
2524 // stub for a function whose address is taken in the program).
2525 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2526 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2527 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2528 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2529 }
2530
2531 // Build a sequence of copy-to-reg nodes chained together with token
2532 // chain and flag operands which copy the outgoing args into registers.
2533 // The InFlag in necessary since all emitted instructions must be
2534 // stuck together.
2535 SDValue InFlag;
2536
2537 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2538 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2539 RegsToPass[i].second, InFlag);
2540 InFlag = Chain.getValue(1);
2541 }
2542
2543 // Add argument registers to the end of the list so that they are
2544 // known live into the call.
2545 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2546 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2547 RegsToPass[i].second.getValueType()));
2548
2549 // Add a register mask operand representing the call-preserved registers.
2550 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2551 const uint32_t *Mask =
2552 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2553 assert(Mask && "Missing call preserved mask for calling convention");
2554 if (Subtarget.inMips16HardFloat()) {
2555 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2556 llvm::StringRef Sym = G->getGlobal()->getName();
2557 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2558 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2559 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2560 }
2561 }
2562 }
2563 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2564
2565 if (InFlag.getNode())
2566 Ops.push_back(InFlag);
2567 }
2568
2569 /// LowerCall - functions arguments are copied from virtual regs to
2570 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
2571 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const2572 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2573 SmallVectorImpl<SDValue> &InVals) const {
2574 SelectionDAG &DAG = CLI.DAG;
2575 SDLoc DL = CLI.DL;
2576 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
2577 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
2578 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
2579 SDValue Chain = CLI.Chain;
2580 SDValue Callee = CLI.Callee;
2581 bool &IsTailCall = CLI.IsTailCall;
2582 CallingConv::ID CallConv = CLI.CallConv;
2583 bool IsVarArg = CLI.IsVarArg;
2584
2585 MachineFunction &MF = DAG.getMachineFunction();
2586 MachineFrameInfo *MFI = MF.getFrameInfo();
2587 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
2588 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2589 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
2590
2591 // Analyze operands of the call, assigning locations to each operand.
2592 SmallVector<CCValAssign, 16> ArgLocs;
2593 MipsCCState CCInfo(
2594 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
2595 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
2596
2597 // Allocate the reserved argument area. It seems strange to do this from the
2598 // caller side but removing it breaks the frame size calculation.
2599 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2600
2601 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode());
2602
2603 // Get a count of how many bytes are to be pushed on the stack.
2604 unsigned NextStackOffset = CCInfo.getNextStackOffset();
2605
2606 // Check if it's really possible to do a tail call.
2607 if (IsTailCall)
2608 IsTailCall = isEligibleForTailCallOptimization(
2609 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
2610
2611 if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall())
2612 report_fatal_error("failed to perform tail call elimination on a call "
2613 "site marked musttail");
2614
2615 if (IsTailCall)
2616 ++NumTailCalls;
2617
2618 // Chain is the output chain of the last Load/Store or CopyToReg node.
2619 // ByValChain is the output chain of the last Memcpy node created for copying
2620 // byval arguments to the stack.
2621 unsigned StackAlignment = TFL->getStackAlignment();
2622 NextStackOffset = RoundUpToAlignment(NextStackOffset, StackAlignment);
2623 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
2624
2625 if (!IsTailCall)
2626 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL);
2627
2628 SDValue StackPtr =
2629 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
2630 getPointerTy(DAG.getDataLayout()));
2631
2632 // With EABI is it possible to have 16 args on registers.
2633 std::deque< std::pair<unsigned, SDValue> > RegsToPass;
2634 SmallVector<SDValue, 8> MemOpChains;
2635
2636 CCInfo.rewindByValRegsInfo();
2637
2638 // Walk the register/memloc assignments, inserting copies/loads.
2639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2640 SDValue Arg = OutVals[i];
2641 CCValAssign &VA = ArgLocs[i];
2642 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
2643 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2644 bool UseUpperBits = false;
2645
2646 // ByVal Arg.
2647 if (Flags.isByVal()) {
2648 unsigned FirstByValReg, LastByValReg;
2649 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2650 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2651
2652 assert(Flags.getByValSize() &&
2653 "ByVal args of size 0 should have been ignored by front-end.");
2654 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2655 assert(!IsTailCall &&
2656 "Do not tail-call optimize if there is a byval argument.");
2657 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
2658 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
2659 VA);
2660 CCInfo.nextInRegsParam();
2661 continue;
2662 }
2663
2664 // Promote the value if needed.
2665 switch (VA.getLocInfo()) {
2666 default:
2667 llvm_unreachable("Unknown loc info!");
2668 case CCValAssign::Full:
2669 if (VA.isRegLoc()) {
2670 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
2671 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
2672 (ValVT == MVT::i64 && LocVT == MVT::f64))
2673 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2674 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
2675 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2676 Arg, DAG.getConstant(0, DL, MVT::i32));
2677 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2678 Arg, DAG.getConstant(1, DL, MVT::i32));
2679 if (!Subtarget.isLittle())
2680 std::swap(Lo, Hi);
2681 unsigned LocRegLo = VA.getLocReg();
2682 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
2683 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
2684 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
2685 continue;
2686 }
2687 }
2688 break;
2689 case CCValAssign::BCvt:
2690 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
2691 break;
2692 case CCValAssign::SExtUpper:
2693 UseUpperBits = true;
2694 // Fallthrough
2695 case CCValAssign::SExt:
2696 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
2697 break;
2698 case CCValAssign::ZExtUpper:
2699 UseUpperBits = true;
2700 // Fallthrough
2701 case CCValAssign::ZExt:
2702 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
2703 break;
2704 case CCValAssign::AExtUpper:
2705 UseUpperBits = true;
2706 // Fallthrough
2707 case CCValAssign::AExt:
2708 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
2709 break;
2710 }
2711
2712 if (UseUpperBits) {
2713 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
2714 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2715 Arg = DAG.getNode(
2716 ISD::SHL, DL, VA.getLocVT(), Arg,
2717 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2718 }
2719
2720 // Arguments that can be passed on register must be kept at
2721 // RegsToPass vector
2722 if (VA.isRegLoc()) {
2723 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2724 continue;
2725 }
2726
2727 // Register can't get to this point...
2728 assert(VA.isMemLoc());
2729
2730 // emit ISD::STORE whichs stores the
2731 // parameter value to a stack Location
2732 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
2733 Chain, Arg, DL, IsTailCall, DAG));
2734 }
2735
2736 // Transform all store nodes into one single node because all store
2737 // nodes are independent of each other.
2738 if (!MemOpChains.empty())
2739 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
2740
2741 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2742 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2743 // node so that legalize doesn't hack it.
2744 bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to
2745 // jalr $25
2746 bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false;
2747 SDValue CalleeLo;
2748 EVT Ty = Callee.getValueType();
2749
2750 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2751 if (IsPICCall) {
2752 const GlobalValue *Val = G->getGlobal();
2753 InternalLinkage = Val->hasInternalLinkage();
2754
2755 if (InternalLinkage)
2756 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
2757 else if (LargeGOT) {
2758 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2759 MipsII::MO_CALL_LO16, Chain,
2760 FuncInfo->callPtrInfo(Val));
2761 IsCallReloc = true;
2762 } else {
2763 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2764 FuncInfo->callPtrInfo(Val));
2765 IsCallReloc = true;
2766 }
2767 } else
2768 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
2769 getPointerTy(DAG.getDataLayout()), 0,
2770 MipsII::MO_NO_FLAG);
2771 GlobalOrExternal = true;
2772 }
2773 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2774 const char *Sym = S->getSymbol();
2775
2776 if (!ABI.IsN64() && !IsPIC) // !N64 && static
2777 Callee = DAG.getTargetExternalSymbol(
2778 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
2779 else if (LargeGOT) {
2780 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
2781 MipsII::MO_CALL_LO16, Chain,
2782 FuncInfo->callPtrInfo(Sym));
2783 IsCallReloc = true;
2784 } else { // N64 || PIC
2785 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
2786 FuncInfo->callPtrInfo(Sym));
2787 IsCallReloc = true;
2788 }
2789
2790 GlobalOrExternal = true;
2791 }
2792
2793 SmallVector<SDValue, 8> Ops(1, Chain);
2794 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2795
2796 getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage,
2797 IsCallReloc, CLI, Callee, Chain);
2798
2799 if (IsTailCall)
2800 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
2801
2802 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
2803 SDValue InFlag = Chain.getValue(1);
2804
2805 // Create the CALLSEQ_END node.
2806 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
2807 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
2808 InFlag = Chain.getValue(1);
2809
2810 // Handle result values, copying them out of physregs into vregs that we
2811 // return.
2812 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
2813 InVals, CLI);
2814 }
2815
2816 /// LowerCallResult - Lower the result values of a call into the
2817 /// appropriate copies out of appropriate physical registers.
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,TargetLowering::CallLoweringInfo & CLI) const2818 SDValue MipsTargetLowering::LowerCallResult(
2819 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
2820 const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
2821 SmallVectorImpl<SDValue> &InVals,
2822 TargetLowering::CallLoweringInfo &CLI) const {
2823 // Assign locations to each value returned by this call.
2824 SmallVector<CCValAssign, 16> RVLocs;
2825 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
2826 *DAG.getContext());
2827 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI);
2828
2829 // Copy all of the result registers out of their specified physreg.
2830 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2831 CCValAssign &VA = RVLocs[i];
2832 assert(VA.isRegLoc() && "Can only return in registers!");
2833
2834 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
2835 RVLocs[i].getLocVT(), InFlag);
2836 Chain = Val.getValue(1);
2837 InFlag = Val.getValue(2);
2838
2839 if (VA.isUpperBitsInLoc()) {
2840 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
2841 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2842 unsigned Shift =
2843 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2844 Val = DAG.getNode(
2845 Shift, DL, VA.getLocVT(), Val,
2846 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2847 }
2848
2849 switch (VA.getLocInfo()) {
2850 default:
2851 llvm_unreachable("Unknown loc info!");
2852 case CCValAssign::Full:
2853 break;
2854 case CCValAssign::BCvt:
2855 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
2856 break;
2857 case CCValAssign::AExt:
2858 case CCValAssign::AExtUpper:
2859 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2860 break;
2861 case CCValAssign::ZExt:
2862 case CCValAssign::ZExtUpper:
2863 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
2864 DAG.getValueType(VA.getValVT()));
2865 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2866 break;
2867 case CCValAssign::SExt:
2868 case CCValAssign::SExtUpper:
2869 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
2870 DAG.getValueType(VA.getValVT()));
2871 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
2872 break;
2873 }
2874
2875 InVals.push_back(Val);
2876 }
2877
2878 return Chain;
2879 }
2880
UnpackFromArgumentSlot(SDValue Val,const CCValAssign & VA,EVT ArgVT,SDLoc DL,SelectionDAG & DAG)2881 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
2882 EVT ArgVT, SDLoc DL, SelectionDAG &DAG) {
2883 MVT LocVT = VA.getLocVT();
2884 EVT ValVT = VA.getValVT();
2885
2886 // Shift into the upper bits if necessary.
2887 switch (VA.getLocInfo()) {
2888 default:
2889 break;
2890 case CCValAssign::AExtUpper:
2891 case CCValAssign::SExtUpper:
2892 case CCValAssign::ZExtUpper: {
2893 unsigned ValSizeInBits = ArgVT.getSizeInBits();
2894 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
2895 unsigned Opcode =
2896 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
2897 Val = DAG.getNode(
2898 Opcode, DL, VA.getLocVT(), Val,
2899 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
2900 break;
2901 }
2902 }
2903
2904 // If this is an value smaller than the argument slot size (32-bit for O32,
2905 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
2906 // size. Extract the value and insert any appropriate assertions regarding
2907 // sign/zero extension.
2908 switch (VA.getLocInfo()) {
2909 default:
2910 llvm_unreachable("Unknown loc info!");
2911 case CCValAssign::Full:
2912 break;
2913 case CCValAssign::AExtUpper:
2914 case CCValAssign::AExt:
2915 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2916 break;
2917 case CCValAssign::SExtUpper:
2918 case CCValAssign::SExt:
2919 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
2920 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2921 break;
2922 case CCValAssign::ZExtUpper:
2923 case CCValAssign::ZExt:
2924 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
2925 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
2926 break;
2927 case CCValAssign::BCvt:
2928 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
2929 break;
2930 }
2931
2932 return Val;
2933 }
2934
2935 //===----------------------------------------------------------------------===//
2936 // Formal Arguments Calling Convention Implementation
2937 //===----------------------------------------------------------------------===//
2938 /// LowerFormalArguments - transform physical registers into virtual registers
2939 /// and generate load operations for arguments places on the stack.
2940 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const2941 MipsTargetLowering::LowerFormalArguments(SDValue Chain,
2942 CallingConv::ID CallConv,
2943 bool IsVarArg,
2944 const SmallVectorImpl<ISD::InputArg> &Ins,
2945 SDLoc DL, SelectionDAG &DAG,
2946 SmallVectorImpl<SDValue> &InVals)
2947 const {
2948 MachineFunction &MF = DAG.getMachineFunction();
2949 MachineFrameInfo *MFI = MF.getFrameInfo();
2950 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2951
2952 MipsFI->setVarArgsFrameIndex(0);
2953
2954 // Used with vargs to acumulate store chains.
2955 std::vector<SDValue> OutChains;
2956
2957 // Assign locations to all of the incoming arguments.
2958 SmallVector<CCValAssign, 16> ArgLocs;
2959 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
2960 *DAG.getContext());
2961 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
2962 const Function *Func = DAG.getMachineFunction().getFunction();
2963 Function::const_arg_iterator FuncArg = Func->arg_begin();
2964
2965 if (Func->hasFnAttribute("interrupt") && !Func->arg_empty())
2966 report_fatal_error(
2967 "Functions with the interrupt attribute cannot have arguments!");
2968
2969 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
2970 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
2971 CCInfo.getInRegsParamsCount() > 0);
2972
2973 unsigned CurArgIdx = 0;
2974 CCInfo.rewindByValRegsInfo();
2975
2976 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2977 CCValAssign &VA = ArgLocs[i];
2978 if (Ins[i].isOrigArg()) {
2979 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
2980 CurArgIdx = Ins[i].getOrigArgIndex();
2981 }
2982 EVT ValVT = VA.getValVT();
2983 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2984 bool IsRegLoc = VA.isRegLoc();
2985
2986 if (Flags.isByVal()) {
2987 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
2988 unsigned FirstByValReg, LastByValReg;
2989 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
2990 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
2991
2992 assert(Flags.getByValSize() &&
2993 "ByVal args of size 0 should have been ignored by front-end.");
2994 assert(ByValIdx < CCInfo.getInRegsParamsCount());
2995 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
2996 FirstByValReg, LastByValReg, VA, CCInfo);
2997 CCInfo.nextInRegsParam();
2998 continue;
2999 }
3000
3001 // Arguments stored on registers
3002 if (IsRegLoc) {
3003 MVT RegVT = VA.getLocVT();
3004 unsigned ArgReg = VA.getLocReg();
3005 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3006
3007 // Transform the arguments stored on
3008 // physical registers into virtual ones
3009 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3010 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3011
3012 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3013
3014 // Handle floating point arguments passed in integer registers and
3015 // long double arguments passed in floating point registers.
3016 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3017 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3018 (RegVT == MVT::f64 && ValVT == MVT::i64))
3019 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3020 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3021 ValVT == MVT::f64) {
3022 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3023 getNextIntArgReg(ArgReg), RC);
3024 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3025 if (!Subtarget.isLittle())
3026 std::swap(ArgValue, ArgValue2);
3027 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3028 ArgValue, ArgValue2);
3029 }
3030
3031 InVals.push_back(ArgValue);
3032 } else { // VA.isRegLoc()
3033 MVT LocVT = VA.getLocVT();
3034
3035 if (ABI.IsO32()) {
3036 // We ought to be able to use LocVT directly but O32 sets it to i32
3037 // when allocating floating point values to integer registers.
3038 // This shouldn't influence how we load the value into registers unless
3039 // we are targeting softfloat.
3040 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3041 LocVT = VA.getValVT();
3042 }
3043
3044 // sanity check
3045 assert(VA.isMemLoc());
3046
3047 // The stack pointer offset is relative to the caller stack frame.
3048 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
3049 VA.getLocMemOffset(), true);
3050
3051 // Create load nodes to retrieve arguments from the stack
3052 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3053 SDValue ArgValue = DAG.getLoad(
3054 LocVT, DL, Chain, FIN,
3055 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3056 false, false, false, 0);
3057 OutChains.push_back(ArgValue.getValue(1));
3058
3059 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3060
3061 InVals.push_back(ArgValue);
3062 }
3063 }
3064
3065 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3066 // The mips ABIs for returning structs by value requires that we copy
3067 // the sret argument into $v0 for the return. Save the argument into
3068 // a virtual register so that we can access it from the return points.
3069 if (Ins[i].Flags.isSRet()) {
3070 unsigned Reg = MipsFI->getSRetReturnReg();
3071 if (!Reg) {
3072 Reg = MF.getRegInfo().createVirtualRegister(
3073 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3074 MipsFI->setSRetReturnReg(Reg);
3075 }
3076 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3077 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3078 break;
3079 }
3080 }
3081
3082 if (IsVarArg)
3083 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3084
3085 // All stores are grouped in one node to allow the matching between
3086 // the size of Ins and InVals. This only happens when on varg functions
3087 if (!OutChains.empty()) {
3088 OutChains.push_back(Chain);
3089 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3090 }
3091
3092 return Chain;
3093 }
3094
3095 //===----------------------------------------------------------------------===//
3096 // Return Value Calling Convention Implementation
3097 //===----------------------------------------------------------------------===//
3098
3099 bool
CanLowerReturn(CallingConv::ID CallConv,MachineFunction & MF,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,LLVMContext & Context) const3100 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3101 MachineFunction &MF, bool IsVarArg,
3102 const SmallVectorImpl<ISD::OutputArg> &Outs,
3103 LLVMContext &Context) const {
3104 SmallVector<CCValAssign, 16> RVLocs;
3105 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3106 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3107 }
3108
3109 bool
shouldSignExtendTypeInLibCall(EVT Type,bool IsSigned) const3110 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3111 if (Subtarget.hasMips3() && Subtarget.useSoftFloat()) {
3112 if (Type == MVT::i32)
3113 return true;
3114 }
3115 return IsSigned;
3116 }
3117
3118 SDValue
LowerInterruptReturn(SmallVectorImpl<SDValue> & RetOps,SDLoc DL,SelectionDAG & DAG) const3119 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3120 SDLoc DL, SelectionDAG &DAG) const {
3121
3122 MachineFunction &MF = DAG.getMachineFunction();
3123 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3124
3125 MipsFI->setISR();
3126
3127 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3128 }
3129
3130 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const3131 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3132 bool IsVarArg,
3133 const SmallVectorImpl<ISD::OutputArg> &Outs,
3134 const SmallVectorImpl<SDValue> &OutVals,
3135 SDLoc DL, SelectionDAG &DAG) const {
3136 // CCValAssign - represent the assignment of
3137 // the return value to a location
3138 SmallVector<CCValAssign, 16> RVLocs;
3139 MachineFunction &MF = DAG.getMachineFunction();
3140
3141 // CCState - Info about the registers and stack slot.
3142 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3143
3144 // Analyze return values.
3145 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3146
3147 SDValue Flag;
3148 SmallVector<SDValue, 4> RetOps(1, Chain);
3149
3150 // Copy the result values into the output registers.
3151 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3152 SDValue Val = OutVals[i];
3153 CCValAssign &VA = RVLocs[i];
3154 assert(VA.isRegLoc() && "Can only return in registers!");
3155 bool UseUpperBits = false;
3156
3157 switch (VA.getLocInfo()) {
3158 default:
3159 llvm_unreachable("Unknown loc info!");
3160 case CCValAssign::Full:
3161 break;
3162 case CCValAssign::BCvt:
3163 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3164 break;
3165 case CCValAssign::AExtUpper:
3166 UseUpperBits = true;
3167 // Fallthrough
3168 case CCValAssign::AExt:
3169 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3170 break;
3171 case CCValAssign::ZExtUpper:
3172 UseUpperBits = true;
3173 // Fallthrough
3174 case CCValAssign::ZExt:
3175 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3176 break;
3177 case CCValAssign::SExtUpper:
3178 UseUpperBits = true;
3179 // Fallthrough
3180 case CCValAssign::SExt:
3181 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3182 break;
3183 }
3184
3185 if (UseUpperBits) {
3186 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3187 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3188 Val = DAG.getNode(
3189 ISD::SHL, DL, VA.getLocVT(), Val,
3190 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3191 }
3192
3193 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3194
3195 // Guarantee that all emitted copies are stuck together with flags.
3196 Flag = Chain.getValue(1);
3197 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3198 }
3199
3200 // The mips ABIs for returning structs by value requires that we copy
3201 // the sret argument into $v0 for the return. We saved the argument into
3202 // a virtual register in the entry block, so now we copy the value out
3203 // and into $v0.
3204 if (MF.getFunction()->hasStructRetAttr()) {
3205 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3206 unsigned Reg = MipsFI->getSRetReturnReg();
3207
3208 if (!Reg)
3209 llvm_unreachable("sret virtual register not created in the entry block");
3210 SDValue Val =
3211 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3212 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3213
3214 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3215 Flag = Chain.getValue(1);
3216 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3217 }
3218
3219 RetOps[0] = Chain; // Update chain.
3220
3221 // Add the flag if we have it.
3222 if (Flag.getNode())
3223 RetOps.push_back(Flag);
3224
3225 // ISRs must use "eret".
3226 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt"))
3227 return LowerInterruptReturn(RetOps, DL, DAG);
3228
3229 // Standard return on Mips is a "jr $ra"
3230 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3231 }
3232
3233 //===----------------------------------------------------------------------===//
3234 // Mips Inline Assembly Support
3235 //===----------------------------------------------------------------------===//
3236
3237 /// getConstraintType - Given a constraint letter, return the type of
3238 /// constraint it is for this target.
3239 MipsTargetLowering::ConstraintType
getConstraintType(StringRef Constraint) const3240 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3241 // Mips specific constraints
3242 // GCC config/mips/constraints.md
3243 //
3244 // 'd' : An address register. Equivalent to r
3245 // unless generating MIPS16 code.
3246 // 'y' : Equivalent to r; retained for
3247 // backwards compatibility.
3248 // 'c' : A register suitable for use in an indirect
3249 // jump. This will always be $25 for -mabicalls.
3250 // 'l' : The lo register. 1 word storage.
3251 // 'x' : The hilo register pair. Double word storage.
3252 if (Constraint.size() == 1) {
3253 switch (Constraint[0]) {
3254 default : break;
3255 case 'd':
3256 case 'y':
3257 case 'f':
3258 case 'c':
3259 case 'l':
3260 case 'x':
3261 return C_RegisterClass;
3262 case 'R':
3263 return C_Memory;
3264 }
3265 }
3266
3267 if (Constraint == "ZC")
3268 return C_Memory;
3269
3270 return TargetLowering::getConstraintType(Constraint);
3271 }
3272
3273 /// Examine constraint type and operand type and determine a weight value.
3274 /// This object must already have been set up with the operand type
3275 /// and the current alternative constraint selected.
3276 TargetLowering::ConstraintWeight
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3277 MipsTargetLowering::getSingleConstraintMatchWeight(
3278 AsmOperandInfo &info, const char *constraint) const {
3279 ConstraintWeight weight = CW_Invalid;
3280 Value *CallOperandVal = info.CallOperandVal;
3281 // If we don't have a value, we can't do a match,
3282 // but allow it at the lowest weight.
3283 if (!CallOperandVal)
3284 return CW_Default;
3285 Type *type = CallOperandVal->getType();
3286 // Look at the constraint type.
3287 switch (*constraint) {
3288 default:
3289 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3290 break;
3291 case 'd':
3292 case 'y':
3293 if (type->isIntegerTy())
3294 weight = CW_Register;
3295 break;
3296 case 'f': // FPU or MSA register
3297 if (Subtarget.hasMSA() && type->isVectorTy() &&
3298 cast<VectorType>(type)->getBitWidth() == 128)
3299 weight = CW_Register;
3300 else if (type->isFloatTy())
3301 weight = CW_Register;
3302 break;
3303 case 'c': // $25 for indirect jumps
3304 case 'l': // lo register
3305 case 'x': // hilo register pair
3306 if (type->isIntegerTy())
3307 weight = CW_SpecificReg;
3308 break;
3309 case 'I': // signed 16 bit immediate
3310 case 'J': // integer zero
3311 case 'K': // unsigned 16 bit immediate
3312 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3313 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3314 case 'O': // signed 15 bit immediate (+- 16383)
3315 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3316 if (isa<ConstantInt>(CallOperandVal))
3317 weight = CW_Constant;
3318 break;
3319 case 'R':
3320 weight = CW_Memory;
3321 break;
3322 }
3323 return weight;
3324 }
3325
3326 /// This is a helper function to parse a physical register string and split it
3327 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3328 /// that is returned indicates whether parsing was successful. The second flag
3329 /// is true if the numeric part exists.
parsePhysicalReg(StringRef C,StringRef & Prefix,unsigned long long & Reg)3330 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3331 unsigned long long &Reg) {
3332 if (C.front() != '{' || C.back() != '}')
3333 return std::make_pair(false, false);
3334
3335 // Search for the first numeric character.
3336 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3337 I = std::find_if(B, E, isdigit);
3338
3339 Prefix = StringRef(B, I - B);
3340
3341 // The second flag is set to false if no numeric characters were found.
3342 if (I == E)
3343 return std::make_pair(true, false);
3344
3345 // Parse the numeric characters.
3346 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3347 true);
3348 }
3349
3350 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
parseRegForInlineAsmConstraint(StringRef C,MVT VT) const3351 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3352 const TargetRegisterInfo *TRI =
3353 Subtarget.getRegisterInfo();
3354 const TargetRegisterClass *RC;
3355 StringRef Prefix;
3356 unsigned long long Reg;
3357
3358 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3359
3360 if (!R.first)
3361 return std::make_pair(0U, nullptr);
3362
3363 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3364 // No numeric characters follow "hi" or "lo".
3365 if (R.second)
3366 return std::make_pair(0U, nullptr);
3367
3368 RC = TRI->getRegClass(Prefix == "hi" ?
3369 Mips::HI32RegClassID : Mips::LO32RegClassID);
3370 return std::make_pair(*(RC->begin()), RC);
3371 } else if (Prefix.startswith("$msa")) {
3372 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3373
3374 // No numeric characters follow the name.
3375 if (R.second)
3376 return std::make_pair(0U, nullptr);
3377
3378 Reg = StringSwitch<unsigned long long>(Prefix)
3379 .Case("$msair", Mips::MSAIR)
3380 .Case("$msacsr", Mips::MSACSR)
3381 .Case("$msaaccess", Mips::MSAAccess)
3382 .Case("$msasave", Mips::MSASave)
3383 .Case("$msamodify", Mips::MSAModify)
3384 .Case("$msarequest", Mips::MSARequest)
3385 .Case("$msamap", Mips::MSAMap)
3386 .Case("$msaunmap", Mips::MSAUnmap)
3387 .Default(0);
3388
3389 if (!Reg)
3390 return std::make_pair(0U, nullptr);
3391
3392 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3393 return std::make_pair(Reg, RC);
3394 }
3395
3396 if (!R.second)
3397 return std::make_pair(0U, nullptr);
3398
3399 if (Prefix == "$f") { // Parse $f0-$f31.
3400 // If the size of FP registers is 64-bit or Reg is an even number, select
3401 // the 64-bit register class. Otherwise, select the 32-bit register class.
3402 if (VT == MVT::Other)
3403 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3404
3405 RC = getRegClassFor(VT);
3406
3407 if (RC == &Mips::AFGR64RegClass) {
3408 assert(Reg % 2 == 0);
3409 Reg >>= 1;
3410 }
3411 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3412 RC = TRI->getRegClass(Mips::FCCRegClassID);
3413 else if (Prefix == "$w") { // Parse $w0-$w31.
3414 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3415 } else { // Parse $0-$31.
3416 assert(Prefix == "$");
3417 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3418 }
3419
3420 assert(Reg < RC->getNumRegs());
3421 return std::make_pair(*(RC->begin() + Reg), RC);
3422 }
3423
3424 /// Given a register class constraint, like 'r', if this corresponds directly
3425 /// to an LLVM register class, return a register of 0 and the register class
3426 /// pointer.
3427 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const3428 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3429 StringRef Constraint,
3430 MVT VT) const {
3431 if (Constraint.size() == 1) {
3432 switch (Constraint[0]) {
3433 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3434 case 'y': // Same as 'r'. Exists for compatibility.
3435 case 'r':
3436 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3437 if (Subtarget.inMips16Mode())
3438 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3439 return std::make_pair(0U, &Mips::GPR32RegClass);
3440 }
3441 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3442 return std::make_pair(0U, &Mips::GPR32RegClass);
3443 if (VT == MVT::i64 && Subtarget.isGP64bit())
3444 return std::make_pair(0U, &Mips::GPR64RegClass);
3445 // This will generate an error message
3446 return std::make_pair(0U, nullptr);
3447 case 'f': // FPU or MSA register
3448 if (VT == MVT::v16i8)
3449 return std::make_pair(0U, &Mips::MSA128BRegClass);
3450 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3451 return std::make_pair(0U, &Mips::MSA128HRegClass);
3452 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3453 return std::make_pair(0U, &Mips::MSA128WRegClass);
3454 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3455 return std::make_pair(0U, &Mips::MSA128DRegClass);
3456 else if (VT == MVT::f32)
3457 return std::make_pair(0U, &Mips::FGR32RegClass);
3458 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3459 if (Subtarget.isFP64bit())
3460 return std::make_pair(0U, &Mips::FGR64RegClass);
3461 return std::make_pair(0U, &Mips::AFGR64RegClass);
3462 }
3463 break;
3464 case 'c': // register suitable for indirect jump
3465 if (VT == MVT::i32)
3466 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3467 assert(VT == MVT::i64 && "Unexpected type.");
3468 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3469 case 'l': // register suitable for indirect jump
3470 if (VT == MVT::i32)
3471 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
3472 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
3473 case 'x': // register suitable for indirect jump
3474 // Fixme: Not triggering the use of both hi and low
3475 // This will generate an error message
3476 return std::make_pair(0U, nullptr);
3477 }
3478 }
3479
3480 std::pair<unsigned, const TargetRegisterClass *> R;
3481 R = parseRegForInlineAsmConstraint(Constraint, VT);
3482
3483 if (R.second)
3484 return R;
3485
3486 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3487 }
3488
3489 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3490 /// vector. If it is invalid, don't add anything to Ops.
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3491 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3492 std::string &Constraint,
3493 std::vector<SDValue>&Ops,
3494 SelectionDAG &DAG) const {
3495 SDLoc DL(Op);
3496 SDValue Result;
3497
3498 // Only support length 1 constraints for now.
3499 if (Constraint.length() > 1) return;
3500
3501 char ConstraintLetter = Constraint[0];
3502 switch (ConstraintLetter) {
3503 default: break; // This will fall through to the generic implementation
3504 case 'I': // Signed 16 bit constant
3505 // If this fails, the parent routine will give an error
3506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3507 EVT Type = Op.getValueType();
3508 int64_t Val = C->getSExtValue();
3509 if (isInt<16>(Val)) {
3510 Result = DAG.getTargetConstant(Val, DL, Type);
3511 break;
3512 }
3513 }
3514 return;
3515 case 'J': // integer zero
3516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3517 EVT Type = Op.getValueType();
3518 int64_t Val = C->getZExtValue();
3519 if (Val == 0) {
3520 Result = DAG.getTargetConstant(0, DL, Type);
3521 break;
3522 }
3523 }
3524 return;
3525 case 'K': // unsigned 16 bit immediate
3526 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3527 EVT Type = Op.getValueType();
3528 uint64_t Val = (uint64_t)C->getZExtValue();
3529 if (isUInt<16>(Val)) {
3530 Result = DAG.getTargetConstant(Val, DL, Type);
3531 break;
3532 }
3533 }
3534 return;
3535 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3537 EVT Type = Op.getValueType();
3538 int64_t Val = C->getSExtValue();
3539 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
3540 Result = DAG.getTargetConstant(Val, DL, Type);
3541 break;
3542 }
3543 }
3544 return;
3545 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3546 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3547 EVT Type = Op.getValueType();
3548 int64_t Val = C->getSExtValue();
3549 if ((Val >= -65535) && (Val <= -1)) {
3550 Result = DAG.getTargetConstant(Val, DL, Type);
3551 break;
3552 }
3553 }
3554 return;
3555 case 'O': // signed 15 bit immediate
3556 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3557 EVT Type = Op.getValueType();
3558 int64_t Val = C->getSExtValue();
3559 if ((isInt<15>(Val))) {
3560 Result = DAG.getTargetConstant(Val, DL, Type);
3561 break;
3562 }
3563 }
3564 return;
3565 case 'P': // immediate in the range of 1 to 65535 (inclusive)
3566 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3567 EVT Type = Op.getValueType();
3568 int64_t Val = C->getSExtValue();
3569 if ((Val <= 65535) && (Val >= 1)) {
3570 Result = DAG.getTargetConstant(Val, DL, Type);
3571 break;
3572 }
3573 }
3574 return;
3575 }
3576
3577 if (Result.getNode()) {
3578 Ops.push_back(Result);
3579 return;
3580 }
3581
3582 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3583 }
3584
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS) const3585 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3586 const AddrMode &AM, Type *Ty,
3587 unsigned AS) const {
3588 // No global is ever allowed as a base.
3589 if (AM.BaseGV)
3590 return false;
3591
3592 switch (AM.Scale) {
3593 case 0: // "r+i" or just "i", depending on HasBaseReg.
3594 break;
3595 case 1:
3596 if (!AM.HasBaseReg) // allow "r+i".
3597 break;
3598 return false; // disallow "r+r" or "r+r+i".
3599 default:
3600 return false;
3601 }
3602
3603 return true;
3604 }
3605
3606 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3607 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3608 // The Mips target isn't yet aware of offsets.
3609 return false;
3610 }
3611
getOptimalMemOpType(uint64_t Size,unsigned DstAlign,unsigned SrcAlign,bool IsMemset,bool ZeroMemset,bool MemcpyStrSrc,MachineFunction & MF) const3612 EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
3613 unsigned SrcAlign,
3614 bool IsMemset, bool ZeroMemset,
3615 bool MemcpyStrSrc,
3616 MachineFunction &MF) const {
3617 if (Subtarget.hasMips64())
3618 return MVT::i64;
3619
3620 return MVT::i32;
3621 }
3622
isFPImmLegal(const APFloat & Imm,EVT VT) const3623 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
3624 if (VT != MVT::f32 && VT != MVT::f64)
3625 return false;
3626 if (Imm.isNegZero())
3627 return false;
3628 return Imm.isZero();
3629 }
3630
getJumpTableEncoding() const3631 unsigned MipsTargetLowering::getJumpTableEncoding() const {
3632 if (ABI.IsN64())
3633 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
3634
3635 return TargetLowering::getJumpTableEncoding();
3636 }
3637
useSoftFloat() const3638 bool MipsTargetLowering::useSoftFloat() const {
3639 return Subtarget.useSoftFloat();
3640 }
3641
copyByValRegs(SDValue Chain,SDLoc DL,std::vector<SDValue> & OutChains,SelectionDAG & DAG,const ISD::ArgFlagsTy & Flags,SmallVectorImpl<SDValue> & InVals,const Argument * FuncArg,unsigned FirstReg,unsigned LastReg,const CCValAssign & VA,MipsCCState & State) const3642 void MipsTargetLowering::copyByValRegs(
3643 SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,
3644 const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,
3645 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg,
3646 const CCValAssign &VA, MipsCCState &State) const {
3647 MachineFunction &MF = DAG.getMachineFunction();
3648 MachineFrameInfo *MFI = MF.getFrameInfo();
3649 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
3650 unsigned NumRegs = LastReg - FirstReg;
3651 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
3652 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
3653 int FrameObjOffset;
3654 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
3655
3656 if (RegAreaSize)
3657 FrameObjOffset =
3658 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3659 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
3660 else
3661 FrameObjOffset = VA.getLocMemOffset();
3662
3663 // Create frame object.
3664 EVT PtrTy = getPointerTy(DAG.getDataLayout());
3665 int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true);
3666 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
3667 InVals.push_back(FIN);
3668
3669 if (!NumRegs)
3670 return;
3671
3672 // Copy arg registers.
3673 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
3674 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3675
3676 for (unsigned I = 0; I < NumRegs; ++I) {
3677 unsigned ArgReg = ByValArgRegs[FirstReg + I];
3678 unsigned VReg = addLiveIn(MF, ArgReg, RC);
3679 unsigned Offset = I * GPRSizeInBytes;
3680 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
3681 DAG.getConstant(Offset, DL, PtrTy));
3682 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
3683 StorePtr, MachinePointerInfo(FuncArg, Offset),
3684 false, false, 0);
3685 OutChains.push_back(Store);
3686 }
3687 }
3688
3689 // Copy byVal arg to registers and stack.
passByValArg(SDValue Chain,SDLoc DL,std::deque<std::pair<unsigned,SDValue>> & RegsToPass,SmallVectorImpl<SDValue> & MemOpChains,SDValue StackPtr,MachineFrameInfo * MFI,SelectionDAG & DAG,SDValue Arg,unsigned FirstReg,unsigned LastReg,const ISD::ArgFlagsTy & Flags,bool isLittle,const CCValAssign & VA) const3690 void MipsTargetLowering::passByValArg(
3691 SDValue Chain, SDLoc DL,
3692 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
3693 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
3694 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
3695 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
3696 const CCValAssign &VA) const {
3697 unsigned ByValSizeInBytes = Flags.getByValSize();
3698 unsigned OffsetInBytes = 0; // From beginning of struct
3699 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3700 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
3701 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
3702 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3703 unsigned NumRegs = LastReg - FirstReg;
3704
3705 if (NumRegs) {
3706 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
3707 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
3708 unsigned I = 0;
3709
3710 // Copy words to registers.
3711 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
3712 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3713 DAG.getConstant(OffsetInBytes, DL, PtrTy));
3714 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
3715 MachinePointerInfo(), false, false, false,
3716 Alignment);
3717 MemOpChains.push_back(LoadVal.getValue(1));
3718 unsigned ArgReg = ArgRegs[FirstReg + I];
3719 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
3720 }
3721
3722 // Return if the struct has been fully copied.
3723 if (ByValSizeInBytes == OffsetInBytes)
3724 return;
3725
3726 // Copy the remainder of the byval argument with sub-word loads and shifts.
3727 if (LeftoverBytes) {
3728 SDValue Val;
3729
3730 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
3731 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
3732 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
3733
3734 if (RemainingSizeInBytes < LoadSizeInBytes)
3735 continue;
3736
3737 // Load subword.
3738 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3739 DAG.getConstant(OffsetInBytes, DL,
3740 PtrTy));
3741 SDValue LoadVal = DAG.getExtLoad(
3742 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
3743 MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false,
3744 Alignment);
3745 MemOpChains.push_back(LoadVal.getValue(1));
3746
3747 // Shift the loaded value.
3748 unsigned Shamt;
3749
3750 if (isLittle)
3751 Shamt = TotalBytesLoaded * 8;
3752 else
3753 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
3754
3755 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
3756 DAG.getConstant(Shamt, DL, MVT::i32));
3757
3758 if (Val.getNode())
3759 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
3760 else
3761 Val = Shift;
3762
3763 OffsetInBytes += LoadSizeInBytes;
3764 TotalBytesLoaded += LoadSizeInBytes;
3765 Alignment = std::min(Alignment, LoadSizeInBytes);
3766 }
3767
3768 unsigned ArgReg = ArgRegs[FirstReg + I];
3769 RegsToPass.push_back(std::make_pair(ArgReg, Val));
3770 return;
3771 }
3772 }
3773
3774 // Copy remainder of byval arg to it with memcpy.
3775 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
3776 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
3777 DAG.getConstant(OffsetInBytes, DL, PtrTy));
3778 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
3779 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
3780 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
3781 DAG.getConstant(MemCpySize, DL, PtrTy),
3782 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
3783 /*isTailCall=*/false,
3784 MachinePointerInfo(), MachinePointerInfo());
3785 MemOpChains.push_back(Chain);
3786 }
3787
writeVarArgRegs(std::vector<SDValue> & OutChains,SDValue Chain,SDLoc DL,SelectionDAG & DAG,CCState & State) const3788 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
3789 SDValue Chain, SDLoc DL,
3790 SelectionDAG &DAG,
3791 CCState &State) const {
3792 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
3793 unsigned Idx = State.getFirstUnallocated(ArgRegs);
3794 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3795 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
3796 const TargetRegisterClass *RC = getRegClassFor(RegTy);
3797 MachineFunction &MF = DAG.getMachineFunction();
3798 MachineFrameInfo *MFI = MF.getFrameInfo();
3799 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3800
3801 // Offset of the first variable argument from stack pointer.
3802 int VaArgOffset;
3803
3804 if (ArgRegs.size() == Idx)
3805 VaArgOffset =
3806 RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes);
3807 else {
3808 VaArgOffset =
3809 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
3810 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
3811 }
3812
3813 // Record the frame index of the first variable argument
3814 // which is a value necessary to VASTART.
3815 int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3816 MipsFI->setVarArgsFrameIndex(FI);
3817
3818 // Copy the integer registers that have not been used for argument passing
3819 // to the argument register save area. For O32, the save area is allocated
3820 // in the caller's stack frame, while for N32/64, it is allocated in the
3821 // callee's stack frame.
3822 for (unsigned I = Idx; I < ArgRegs.size();
3823 ++I, VaArgOffset += RegSizeInBytes) {
3824 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
3825 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
3826 FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
3827 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3828 SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff,
3829 MachinePointerInfo(), false, false, 0);
3830 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
3831 (Value *)nullptr);
3832 OutChains.push_back(Store);
3833 }
3834 }
3835
HandleByVal(CCState * State,unsigned & Size,unsigned Align) const3836 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
3837 unsigned Align) const {
3838 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3839
3840 assert(Size && "Byval argument's size shouldn't be 0.");
3841
3842 Align = std::min(Align, TFL->getStackAlignment());
3843
3844 unsigned FirstReg = 0;
3845 unsigned NumRegs = 0;
3846
3847 if (State->getCallingConv() != CallingConv::Fast) {
3848 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
3849 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
3850 // FIXME: The O32 case actually describes no shadow registers.
3851 const MCPhysReg *ShadowRegs =
3852 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
3853
3854 // We used to check the size as well but we can't do that anymore since
3855 // CCState::HandleByVal() rounds up the size after calling this function.
3856 assert(!(Align % RegSizeInBytes) &&
3857 "Byval argument's alignment should be a multiple of"
3858 "RegSizeInBytes.");
3859
3860 FirstReg = State->getFirstUnallocated(IntArgRegs);
3861
3862 // If Align > RegSizeInBytes, the first arg register must be even.
3863 // FIXME: This condition happens to do the right thing but it's not the
3864 // right way to test it. We want to check that the stack frame offset
3865 // of the register is aligned.
3866 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
3867 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
3868 ++FirstReg;
3869 }
3870
3871 // Mark the registers allocated.
3872 Size = RoundUpToAlignment(Size, RegSizeInBytes);
3873 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
3874 Size -= RegSizeInBytes, ++I, ++NumRegs)
3875 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
3876 }
3877
3878 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
3879 }
3880
3881 MachineBasicBlock *
emitPseudoSELECT(MachineInstr * MI,MachineBasicBlock * BB,bool isFPCmp,unsigned Opc) const3882 MipsTargetLowering::emitPseudoSELECT(MachineInstr *MI, MachineBasicBlock *BB,
3883 bool isFPCmp, unsigned Opc) const {
3884 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
3885 "Subtarget already supports SELECT nodes with the use of"
3886 "conditional-move instructions.");
3887
3888 const TargetInstrInfo *TII =
3889 Subtarget.getInstrInfo();
3890 DebugLoc DL = MI->getDebugLoc();
3891
3892 // To "insert" a SELECT instruction, we actually have to insert the
3893 // diamond control-flow pattern. The incoming instruction knows the
3894 // destination vreg to set, the condition code register to branch on, the
3895 // true/false values to select between, and a branch opcode to use.
3896 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3897 MachineFunction::iterator It = ++BB->getIterator();
3898
3899 // thisMBB:
3900 // ...
3901 // TrueVal = ...
3902 // setcc r1, r2, r3
3903 // bNE r1, r0, copy1MBB
3904 // fallthrough --> copy0MBB
3905 MachineBasicBlock *thisMBB = BB;
3906 MachineFunction *F = BB->getParent();
3907 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3908 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3909 F->insert(It, copy0MBB);
3910 F->insert(It, sinkMBB);
3911
3912 // Transfer the remainder of BB and its successor edges to sinkMBB.
3913 sinkMBB->splice(sinkMBB->begin(), BB,
3914 std::next(MachineBasicBlock::iterator(MI)), BB->end());
3915 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3916
3917 // Next, add the true and fallthrough blocks as its successors.
3918 BB->addSuccessor(copy0MBB);
3919 BB->addSuccessor(sinkMBB);
3920
3921 if (isFPCmp) {
3922 // bc1[tf] cc, sinkMBB
3923 BuildMI(BB, DL, TII->get(Opc))
3924 .addReg(MI->getOperand(1).getReg())
3925 .addMBB(sinkMBB);
3926 } else {
3927 // bne rs, $0, sinkMBB
3928 BuildMI(BB, DL, TII->get(Opc))
3929 .addReg(MI->getOperand(1).getReg())
3930 .addReg(Mips::ZERO)
3931 .addMBB(sinkMBB);
3932 }
3933
3934 // copy0MBB:
3935 // %FalseValue = ...
3936 // # fallthrough to sinkMBB
3937 BB = copy0MBB;
3938
3939 // Update machine-CFG edges
3940 BB->addSuccessor(sinkMBB);
3941
3942 // sinkMBB:
3943 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
3944 // ...
3945 BB = sinkMBB;
3946
3947 BuildMI(*BB, BB->begin(), DL,
3948 TII->get(Mips::PHI), MI->getOperand(0).getReg())
3949 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
3950 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
3951
3952 MI->eraseFromParent(); // The pseudo instruction is gone now.
3953
3954 return BB;
3955 }
3956
3957 // FIXME? Maybe this could be a TableGen attribute on some registers and
3958 // this table could be generated automatically from RegInfo.
getRegisterByName(const char * RegName,EVT VT,SelectionDAG & DAG) const3959 unsigned MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
3960 SelectionDAG &DAG) const {
3961 // Named registers is expected to be fairly rare. For now, just support $28
3962 // since the linux kernel uses it.
3963 if (Subtarget.isGP64bit()) {
3964 unsigned Reg = StringSwitch<unsigned>(RegName)
3965 .Case("$28", Mips::GP_64)
3966 .Default(0);
3967 if (Reg)
3968 return Reg;
3969 } else {
3970 unsigned Reg = StringSwitch<unsigned>(RegName)
3971 .Case("$28", Mips::GP)
3972 .Default(0);
3973 if (Reg)
3974 return Reg;
3975 }
3976 report_fatal_error("Invalid register name global variable");
3977 }
3978