1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include "util/u_format.h"
27 #include "util/u_inlines.h"
28 #include "translate/translate.h"
29
30 #include "nouveau/nouveau_fence.h"
31 #include "nouveau/nv_object.xml.h"
32 #include "nv30-40_3d.xml.h"
33 #include "nv30_context.h"
34 #include "nv30_format.h"
35
36 static void
nv30_emit_vtxattr(struct nv30_context * nv30,struct pipe_vertex_buffer * vb,struct pipe_vertex_element * ve,unsigned attr)37 nv30_emit_vtxattr(struct nv30_context *nv30, struct pipe_vertex_buffer *vb,
38 struct pipe_vertex_element *ve, unsigned attr)
39 {
40 const unsigned nc = util_format_get_nr_components(ve->src_format);
41 struct nouveau_pushbuf *push = nv30->base.pushbuf;
42 struct nv04_resource *res = nv04_resource(vb->buffer);
43 const void *data;
44 float v[4];
45
46 data = nouveau_resource_map_offset(&nv30->base, res, vb->buffer_offset +
47 ve->src_offset, NOUVEAU_BO_RD);
48
49 util_format_read_4f(ve->src_format, v, 0, data, 0, 0, 0, 1, 1);
50
51 switch (nc) {
52 case 4:
53 BEGIN_NV04(push, NV30_3D(VTX_ATTR_4F(attr)), 4);
54 PUSH_DATAf(push, v[0]);
55 PUSH_DATAf(push, v[1]);
56 PUSH_DATAf(push, v[2]);
57 PUSH_DATAf(push, v[3]);
58 break;
59 case 3:
60 BEGIN_NV04(push, NV30_3D(VTX_ATTR_3F(attr)), 3);
61 PUSH_DATAf(push, v[0]);
62 PUSH_DATAf(push, v[1]);
63 PUSH_DATAf(push, v[2]);
64 break;
65 case 2:
66 BEGIN_NV04(push, NV30_3D(VTX_ATTR_2F(attr)), 2);
67 PUSH_DATAf(push, v[0]);
68 PUSH_DATAf(push, v[1]);
69 break;
70 case 1:
71 BEGIN_NV04(push, NV30_3D(VTX_ATTR_1F(attr)), 1);
72 PUSH_DATAf(push, v[0]);
73 break;
74 default:
75 assert(0);
76 break;
77 }
78 }
79
80 static INLINE void
nv30_vbuf_range(struct nv30_context * nv30,int vbi,uint32_t * base,uint32_t * size)81 nv30_vbuf_range(struct nv30_context *nv30, int vbi,
82 uint32_t *base, uint32_t *size)
83 {
84 assert(nv30->vbo_max_index != ~0);
85 *base = nv30->vbo_min_index * nv30->vtxbuf[vbi].stride;
86 *size = (nv30->vbo_max_index -
87 nv30->vbo_min_index + 1) * nv30->vtxbuf[vbi].stride;
88 }
89
90 static void
nv30_prevalidate_vbufs(struct nv30_context * nv30)91 nv30_prevalidate_vbufs(struct nv30_context *nv30)
92 {
93 struct pipe_vertex_buffer *vb;
94 struct nv04_resource *buf;
95 int i;
96 uint32_t base, size;
97
98 nv30->vbo_fifo = nv30->vbo_user = 0;
99
100 for (i = 0; i < nv30->num_vtxbufs; i++) {
101 vb = &nv30->vtxbuf[i];
102 if (!vb->stride || !vb->buffer) /* NOTE: user_buffer not implemented */
103 continue;
104 buf = nv04_resource(vb->buffer);
105
106 /* NOTE: user buffers with temporary storage count as mapped by GPU */
107 if (!nouveau_resource_mapped_by_gpu(vb->buffer)) {
108 if (nv30->vbo_push_hint) {
109 nv30->vbo_fifo = ~0;
110 continue;
111 } else {
112 if (buf->status & NOUVEAU_BUFFER_STATUS_USER_MEMORY) {
113 nv30->vbo_user |= 1 << i;
114 assert(vb->stride > vb->buffer_offset);
115 nv30_vbuf_range(nv30, i, &base, &size);
116 nouveau_user_buffer_upload(&nv30->base, buf, base, size);
117 } else {
118 nouveau_buffer_migrate(&nv30->base, buf, NOUVEAU_BO_GART);
119 }
120 nv30->base.vbo_dirty = TRUE;
121 }
122 }
123 }
124 }
125
126 static void
nv30_update_user_vbufs(struct nv30_context * nv30)127 nv30_update_user_vbufs(struct nv30_context *nv30)
128 {
129 struct nouveau_pushbuf *push = nv30->base.pushbuf;
130 uint32_t base, offset, size;
131 int i;
132 uint32_t written = 0;
133
134 for (i = 0; i < nv30->vertex->num_elements; i++) {
135 struct pipe_vertex_element *ve = &nv30->vertex->pipe[i];
136 const int b = ve->vertex_buffer_index;
137 struct pipe_vertex_buffer *vb = &nv30->vtxbuf[b];
138 struct nv04_resource *buf = nv04_resource(vb->buffer);
139
140 if (!(nv30->vbo_user & (1 << b)))
141 continue;
142
143 if (!vb->stride) {
144 nv30_emit_vtxattr(nv30, vb, ve, i);
145 continue;
146 }
147 nv30_vbuf_range(nv30, b, &base, &size);
148
149 if (!(written & (1 << b))) {
150 written |= 1 << b;
151 nouveau_user_buffer_upload(&nv30->base, buf, base, size);
152 }
153
154 offset = vb->buffer_offset + ve->src_offset;
155
156 BEGIN_NV04(push, NV30_3D(VTXBUF(i)), 1);
157 PUSH_RESRC(push, NV30_3D(VTXBUF(i)), BUFCTX_VTXTMP, buf, offset,
158 NOUVEAU_BO_LOW | NOUVEAU_BO_RD,
159 0, NV30_3D_VTXBUF_DMA1);
160 }
161 nv30->base.vbo_dirty = TRUE;
162 }
163
164 static INLINE void
nv30_release_user_vbufs(struct nv30_context * nv30)165 nv30_release_user_vbufs(struct nv30_context *nv30)
166 {
167 uint32_t vbo_user = nv30->vbo_user;
168
169 while (vbo_user) {
170 int i = ffs(vbo_user) - 1;
171 vbo_user &= ~(1 << i);
172
173 nouveau_buffer_release_gpu_storage(nv04_resource(nv30->vtxbuf[i].buffer));
174 }
175
176 nouveau_bufctx_reset(nv30->bufctx, BUFCTX_VTXTMP);
177 }
178
179 void
nv30_vbo_validate(struct nv30_context * nv30)180 nv30_vbo_validate(struct nv30_context *nv30)
181 {
182 struct nouveau_pushbuf *push = nv30->base.pushbuf;
183 struct nv30_vertex_stateobj *vertex = nv30->vertex;
184 struct pipe_vertex_element *ve;
185 struct pipe_vertex_buffer *vb;
186 unsigned i, redefine;
187
188 nouveau_bufctx_reset(nv30->bufctx, BUFCTX_VTXBUF);
189 if (!nv30->vertex || nv30->draw_flags)
190 return;
191
192 if (unlikely(vertex->need_conversion)) {
193 nv30->vbo_fifo = ~0;
194 nv30->vbo_user = 0;
195 } else {
196 nv30_prevalidate_vbufs(nv30);
197 }
198
199 if (!PUSH_SPACE(push, 128))
200 return;
201
202 redefine = MAX2(vertex->num_elements, nv30->state.num_vtxelts);
203 BEGIN_NV04(push, NV30_3D(VTXFMT(0)), redefine);
204
205 for (i = 0; i < vertex->num_elements; i++) {
206 ve = &vertex->pipe[i];
207 vb = &nv30->vtxbuf[ve->vertex_buffer_index];
208
209 if (likely(vb->stride) || nv30->vbo_fifo)
210 PUSH_DATA (push, (vb->stride << 8) | vertex->element[i].state);
211 else
212 PUSH_DATA (push, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
213 }
214
215 for (; i < nv30->state.num_vtxelts; i++) {
216 PUSH_DATA (push, NV30_3D_VTXFMT_TYPE_V32_FLOAT);
217 }
218
219 for (i = 0; i < vertex->num_elements; i++) {
220 struct nv04_resource *res;
221 unsigned offset;
222 boolean user;
223
224 ve = &vertex->pipe[i];
225 vb = &nv30->vtxbuf[ve->vertex_buffer_index];
226 user = (nv30->vbo_user & (1 << ve->vertex_buffer_index));
227
228 res = nv04_resource(vb->buffer);
229
230 if (nv30->vbo_fifo || unlikely(vb->stride == 0)) {
231 if (!nv30->vbo_fifo)
232 nv30_emit_vtxattr(nv30, vb, ve, i);
233 continue;
234 }
235
236 offset = ve->src_offset + vb->buffer_offset;
237
238 BEGIN_NV04(push, NV30_3D(VTXBUF(i)), 1);
239 PUSH_RESRC(push, NV30_3D(VTXBUF(i)), user ? BUFCTX_VTXTMP : BUFCTX_VTXBUF,
240 res, offset, NOUVEAU_BO_LOW | NOUVEAU_BO_RD,
241 0, NV30_3D_VTXBUF_DMA1);
242 }
243
244 nv30->state.num_vtxelts = vertex->num_elements;
245 }
246
247 static void *
nv30_vertex_state_create(struct pipe_context * pipe,unsigned num_elements,const struct pipe_vertex_element * elements)248 nv30_vertex_state_create(struct pipe_context *pipe, unsigned num_elements,
249 const struct pipe_vertex_element *elements)
250 {
251 struct nv30_vertex_stateobj *so;
252 struct translate_key transkey;
253 unsigned i;
254
255 assert(num_elements);
256
257 so = MALLOC(sizeof(*so) + sizeof(*so->element) * num_elements);
258 if (!so)
259 return NULL;
260 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
261 so->num_elements = num_elements;
262 so->need_conversion = FALSE;
263
264 transkey.nr_elements = 0;
265 transkey.output_stride = 0;
266
267 for (i = 0; i < num_elements; i++) {
268 const struct pipe_vertex_element *ve = &elements[i];
269 const unsigned vbi = ve->vertex_buffer_index;
270 enum pipe_format fmt = ve->src_format;
271
272 so->element[i].state = nv30_vtxfmt(pipe->screen, fmt)->hw;
273 if (!so->element[i].state) {
274 switch (util_format_get_nr_components(fmt)) {
275 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break;
276 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break;
277 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break;
278 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break;
279 default:
280 assert(0);
281 return NULL;
282 }
283 so->element[i].state = nv30_vtxfmt(pipe->screen, fmt)->hw;
284 so->need_conversion = TRUE;
285 }
286
287 if (1) {
288 unsigned j = transkey.nr_elements++;
289
290 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL;
291 transkey.element[j].input_format = ve->src_format;
292 transkey.element[j].input_buffer = vbi;
293 transkey.element[j].input_offset = ve->src_offset;
294 transkey.element[j].instance_divisor = ve->instance_divisor;
295
296 transkey.element[j].output_format = fmt;
297 transkey.element[j].output_offset = transkey.output_stride;
298 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3;
299 }
300 }
301
302 so->translate = translate_create(&transkey);
303 so->vtx_size = transkey.output_stride / 4;
304 so->vtx_per_packet_max = NV04_PFIFO_MAX_PACKET_LEN / MAX2(so->vtx_size, 1);
305 return so;
306 }
307
308 static void
nv30_vertex_state_delete(struct pipe_context * pipe,void * hwcso)309 nv30_vertex_state_delete(struct pipe_context *pipe, void *hwcso)
310 {
311 struct nv30_vertex_stateobj *so = hwcso;
312
313 if (so->translate)
314 so->translate->release(so->translate);
315 FREE(hwcso);
316 }
317
318 static void
nv30_vertex_state_bind(struct pipe_context * pipe,void * hwcso)319 nv30_vertex_state_bind(struct pipe_context *pipe, void *hwcso)
320 {
321 struct nv30_context *nv30 = nv30_context(pipe);
322
323 nv30->vertex = hwcso;
324 nv30->dirty |= NV30_NEW_VERTEX;
325 }
326
327 static void
nv30_draw_arrays(struct nv30_context * nv30,unsigned mode,unsigned start,unsigned count,unsigned instance_count)328 nv30_draw_arrays(struct nv30_context *nv30,
329 unsigned mode, unsigned start, unsigned count,
330 unsigned instance_count)
331 {
332 struct nouveau_pushbuf *push = nv30->base.pushbuf;
333 unsigned prim;
334
335 prim = nv30_prim_gl(mode);
336
337 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
338 PUSH_DATA (push, prim);
339 while (count) {
340 const unsigned mpush = 2047 * 256;
341 unsigned npush = (count > mpush) ? mpush : count;
342 unsigned wpush = ((npush + 255) & ~255) >> 8;
343
344 count -= npush;
345
346 BEGIN_NI04(push, NV30_3D(VB_VERTEX_BATCH), wpush);
347 while (npush >= 256) {
348 PUSH_DATA (push, 0xff000000 | start);
349 start += 256;
350 npush -= 256;
351 }
352
353 if (npush)
354 PUSH_DATA (push, ((npush - 1) << 24) | start);
355 }
356 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
357 PUSH_DATA (push, NV30_3D_VERTEX_BEGIN_END_STOP);
358 }
359
360 static void
nv30_draw_elements_inline_u08(struct nouveau_pushbuf * push,const uint8_t * map,unsigned start,unsigned count)361 nv30_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
362 unsigned start, unsigned count)
363 {
364 map += start;
365
366 if (count & 1) {
367 BEGIN_NV04(push, NV30_3D(VB_ELEMENT_U32), 1);
368 PUSH_DATA (push, *map++);
369 }
370
371 count >>= 1;
372 while (count) {
373 unsigned npush = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
374 count -= npush;
375
376 BEGIN_NI04(push, NV30_3D(VB_ELEMENT_U16), npush);
377 while (npush--) {
378 PUSH_DATA (push, (map[1] << 16) | map[0]);
379 map += 2;
380 }
381 }
382
383 }
384
385 static void
nv30_draw_elements_inline_u16(struct nouveau_pushbuf * push,const uint16_t * map,unsigned start,unsigned count)386 nv30_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map,
387 unsigned start, unsigned count)
388 {
389 map += start;
390
391 if (count & 1) {
392 BEGIN_NV04(push, NV30_3D(VB_ELEMENT_U32), 1);
393 PUSH_DATA (push, *map++);
394 }
395
396 count >>= 1;
397 while (count) {
398 unsigned npush = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
399 count -= npush;
400
401 BEGIN_NI04(push, NV30_3D(VB_ELEMENT_U16), npush);
402 while (npush--) {
403 PUSH_DATA (push, (map[1] << 16) | map[0]);
404 map += 2;
405 }
406 }
407 }
408
409 static void
nv30_draw_elements_inline_u32(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)410 nv30_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map,
411 unsigned start, unsigned count)
412 {
413 map += start;
414
415 while (count) {
416 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);
417
418 BEGIN_NI04(push, NV30_3D(VB_ELEMENT_U32), nr);
419 PUSH_DATAp(push, map, nr);
420
421 map += nr;
422 count -= nr;
423 }
424 }
425
426 static void
nv30_draw_elements_inline_u32_short(struct nouveau_pushbuf * push,const uint32_t * map,unsigned start,unsigned count)427 nv30_draw_elements_inline_u32_short(struct nouveau_pushbuf *push,
428 const uint32_t *map,
429 unsigned start, unsigned count)
430 {
431 map += start;
432
433 if (count & 1) {
434 BEGIN_NV04(push, NV30_3D(VB_ELEMENT_U32), 1);
435 PUSH_DATA (push, *map++);
436 }
437
438 count >>= 1;
439 while (count) {
440 unsigned npush = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN);;
441 count -= npush;
442
443 BEGIN_NI04(push, NV30_3D(VB_ELEMENT_U16), npush);
444 while (npush--) {
445 PUSH_DATA (push, (map[1] << 16) | map[0]);
446 map += 2;
447 }
448 }
449 }
450
451 static void
nv30_draw_elements(struct nv30_context * nv30,boolean shorten,unsigned mode,unsigned start,unsigned count,unsigned instance_count,int32_t index_bias)452 nv30_draw_elements(struct nv30_context *nv30, boolean shorten,
453 unsigned mode, unsigned start, unsigned count,
454 unsigned instance_count, int32_t index_bias)
455 {
456 const unsigned index_size = nv30->idxbuf.index_size;
457 struct nouveau_pushbuf *push = nv30->base.pushbuf;
458 struct nouveau_object *eng3d = nv30->screen->eng3d;
459 unsigned prim = nv30_prim_gl(mode);
460
461 #if 0 /*XXX*/
462 if (index_bias != nv30->state.index_bias) {
463 BEGIN_NV04(push, NV30_3D(VB_ELEMENT_BASE), 1);
464 PUSH_DATA (push, index_bias);
465 nv30->state.index_bias = index_bias;
466 }
467 #endif
468
469 if (eng3d->oclass == NV40_3D_CLASS && index_size > 1 &&
470 nv30->idxbuf.buffer) {
471 struct nv04_resource *res = nv04_resource(nv30->idxbuf.buffer);
472 unsigned offset = nv30->idxbuf.offset;
473
474 assert(nouveau_resource_mapped_by_gpu(&res->base));
475
476 BEGIN_NV04(push, NV30_3D(IDXBUF_OFFSET), 2);
477 PUSH_RESRC(push, NV30_3D(IDXBUF_OFFSET), BUFCTX_IDXBUF, res, offset,
478 NOUVEAU_BO_LOW | NOUVEAU_BO_RD, 0, 0);
479 PUSH_MTHD (push, NV30_3D(IDXBUF_FORMAT), BUFCTX_IDXBUF, res->bo,
480 (index_size == 2) ? 0x00000010 : 0x00000000,
481 res->domain | NOUVEAU_BO_RD,
482 0, NV30_3D_IDXBUF_FORMAT_DMA1);
483 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
484 PUSH_DATA (push, prim);
485 while (count) {
486 const unsigned mpush = 2047 * 256;
487 unsigned npush = (count > mpush) ? mpush : count;
488 unsigned wpush = ((npush + 255) & ~255) >> 8;
489
490 count -= npush;
491
492 BEGIN_NI04(push, NV30_3D(VB_INDEX_BATCH), wpush);
493 while (npush >= 256) {
494 PUSH_DATA (push, 0xff000000 | start);
495 start += 256;
496 npush -= 256;
497 }
498
499 if (npush)
500 PUSH_DATA (push, ((npush - 1) << 24) | start);
501 }
502 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
503 PUSH_DATA (push, NV30_3D_VERTEX_BEGIN_END_STOP);
504 PUSH_RESET(push, BUFCTX_IDXBUF);
505 } else {
506 const void *data;
507 if (nv30->idxbuf.buffer)
508 data = nouveau_resource_map_offset(&nv30->base,
509 nv04_resource(nv30->idxbuf.buffer),
510 nv30->idxbuf.offset, NOUVEAU_BO_RD);
511 else
512 data = nv30->idxbuf.user_buffer;
513 if (!data)
514 return;
515
516 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
517 PUSH_DATA (push, prim);
518 switch (index_size) {
519 case 1:
520 nv30_draw_elements_inline_u08(push, data, start, count);
521 break;
522 case 2:
523 nv30_draw_elements_inline_u16(push, data, start, count);
524 break;
525 case 4:
526 if (shorten)
527 nv30_draw_elements_inline_u32_short(push, data, start, count);
528 else
529 nv30_draw_elements_inline_u32(push, data, start, count);
530 break;
531 default:
532 assert(0);
533 return;
534 }
535 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
536 PUSH_DATA (push, NV30_3D_VERTEX_BEGIN_END_STOP);
537 }
538 }
539
540 static void
nv30_draw_vbo(struct pipe_context * pipe,const struct pipe_draw_info * info)541 nv30_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
542 {
543 struct nv30_context *nv30 = nv30_context(pipe);
544 struct nouveau_pushbuf *push = nv30->base.pushbuf;
545
546 /* For picking only a few vertices from a large user buffer, push is better,
547 * if index count is larger and we expect repeated vertices, suggest upload.
548 */
549 nv30->vbo_push_hint = /* the 64 is heuristic */
550 !(info->indexed &&
551 ((info->max_index - info->min_index + 64) < info->count));
552
553 nv30->vbo_min_index = info->min_index;
554 nv30->vbo_max_index = info->max_index;
555
556 if (nv30->vbo_push_hint != !!nv30->vbo_fifo)
557 nv30->dirty |= NV30_NEW_ARRAYS;
558
559 push->user_priv = &nv30->bufctx;
560 if (nv30->vbo_user && !(nv30->dirty & (NV30_NEW_VERTEX | NV30_NEW_ARRAYS)))
561 nv30_update_user_vbufs(nv30);
562
563 nv30_state_validate(nv30, TRUE);
564 if (nv30->draw_flags) {
565 nv30_render_vbo(pipe, info);
566 return;
567 } else
568 if (nv30->vbo_fifo) {
569 nv30_push_vbo(nv30, info);
570 return;
571 }
572
573 if (nv30->base.vbo_dirty) {
574 BEGIN_NV04(push, NV30_3D(VTX_CACHE_INVALIDATE_1710), 1);
575 PUSH_DATA (push, 0);
576 nv30->base.vbo_dirty = FALSE;
577 }
578
579 if (!info->indexed) {
580 nv30_draw_arrays(nv30,
581 info->mode, info->start, info->count,
582 info->instance_count);
583 } else {
584 boolean shorten = info->max_index <= 65535;
585
586 if (info->primitive_restart != nv30->state.prim_restart) {
587 if (info->primitive_restart) {
588 BEGIN_NV04(push, NV40_3D(PRIM_RESTART_ENABLE), 2);
589 PUSH_DATA (push, 1);
590 PUSH_DATA (push, info->restart_index);
591
592 if (info->restart_index > 65535)
593 shorten = FALSE;
594 } else {
595 BEGIN_NV04(push, NV40_3D(PRIM_RESTART_ENABLE), 1);
596 PUSH_DATA (push, 0);
597 }
598 nv30->state.prim_restart = info->primitive_restart;
599 } else
600 if (info->primitive_restart) {
601 BEGIN_NV04(push, NV40_3D(PRIM_RESTART_INDEX), 1);
602 PUSH_DATA (push, info->restart_index);
603
604 if (info->restart_index > 65535)
605 shorten = FALSE;
606 }
607
608 nv30_draw_elements(nv30, shorten,
609 info->mode, info->start, info->count,
610 info->instance_count, info->index_bias);
611 }
612
613 nv30_state_release(nv30);
614 nv30_release_user_vbufs(nv30);
615 }
616
617 void
nv30_vbo_init(struct pipe_context * pipe)618 nv30_vbo_init(struct pipe_context *pipe)
619 {
620 pipe->create_vertex_elements_state = nv30_vertex_state_create;
621 pipe->delete_vertex_elements_state = nv30_vertex_state_delete;
622 pipe->bind_vertex_elements_state = nv30_vertex_state_bind;
623 pipe->draw_vbo = nv30_draw_vbo;
624 }
625