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Searched defs:rN (Results 1 – 24 of 24) sorted by relevance

/external/valgrind/VEX/priv/
Dguest_arm_toIR.c2369 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, in mk_EA_reg_plusminus_imm12()
2388 IRExpr* mk_EA_reg_plusminus_shifted_reg ( UInt rN, UInt bU, UInt rM, in mk_EA_reg_plusminus_shifted_reg()
2458 IRExpr* mk_EA_reg_plusminus_imm8 ( UInt rN, UInt bU, UInt imm8, in mk_EA_reg_plusminus_imm8()
2475 IRExpr* mk_EA_reg_plusminus_reg ( UInt rN, UInt bU, UInt rM, in mk_EA_reg_plusminus_reg()
8334 UInt rN = INSN(19,16); in dis_neon_load_or_store() local
10921 UInt rD = 99, rN = 99, rM = 99, rA = 99; in decode_V6MEDIA_instruction() local
12336 UInt rD = 99, rN = 99, rM = 99, rA = 99; in decode_V6MEDIA_instruction() local
12393 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99; in decode_V6MEDIA_instruction() local
12482 UInt rN = 99, rDlo = 99, rDhi = 99, rM = 99; in decode_V6MEDIA_instruction() local
12588 UInt rN, /* base reg */ in mk_ldm_stm()
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Dhost_arm64_defs.c1013 ARM64Instr* ARM64Instr_VLdStH ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStH()
1023 ARM64Instr* ARM64Instr_VLdStS ( Bool isLoad, HReg sD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStS()
1033 ARM64Instr* ARM64Instr_VLdStD ( Bool isLoad, HReg dD, HReg rN, UInt uimm12 ) { in ARM64Instr_VLdStD()
1043 ARM64Instr* ARM64Instr_VLdStQ ( Bool isLoad, HReg rQ, HReg rN ) { in ARM64Instr_VLdStQ()
3266 UInt rN = iregEnc(i->ARM64in.Arith.argL); in emit_ARM64Instr() local
3292 UInt rN = iregEnc(i->ARM64in.Cmp.argL); in emit_ARM64Instr() local
3319 UInt rN = iregEnc(i->ARM64in.Logic.argL); in emit_ARM64Instr() local
3359 UInt rN = iregEnc(i->ARM64in.Test.argL); in emit_ARM64Instr() local
3378 UInt rN = iregEnc(i->ARM64in.Shift.argL); in emit_ARM64Instr() local
3811 UInt rN = iregEnc(i->ARM64in.VLdStH.rN); in emit_ARM64Instr() local
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Dhost_arm_defs.c365 ARMAModeN *mkARMAModeN_RR ( HReg rN, HReg rM ) { in mkARMAModeN_RR()
373 ARMAModeN *mkARMAModeN_R ( HReg rN ) { in mkARMAModeN_R()
1504 ARMInstr* ARMInstr_Add32 ( HReg rD, HReg rN, UInt imm32 ) { in ARMInstr_Add32()
2839 UInt rN = 0; in imm32_to_ireg() local
2973 UInt rN = iregEnc(i->ARMin.Alu.argL); in emit_ARMInstr() local
3117 HReg rN = am->ARMam2.RI.reg; in emit_ARMInstr() local
3164 HReg rN = am->ARMam2.RI.reg; in emit_ARMInstr() local
3505 UInt rN = iregEnc(i->ARMin.VLdStD.amode->reg); in emit_ARMInstr() local
3521 UInt rN = iregEnc(i->ARMin.VLdStS.amode->reg); in emit_ARMInstr() local
Dhost_arm64_isel.c2189 HReg rN = iselIntExpr_R(env, e->Iex.Load.addr); in iselV128Expr_wrk() local
3036 HReg rN = get_baseblock_register(); in iselDblExpr_wrk() local
3223 HReg rN = get_baseblock_register(); in iselFltExpr_wrk() local
3370 HReg rN = get_baseblock_register(); in iselF16Expr_wrk() local
Dhost_arm64_defs.h681 HReg rN; member
688 HReg rN; member
695 HReg rN; member
702 HReg rN; // address member
Dhost_arm_defs.h215 HReg rN; member
219 HReg rN; member
944 HReg rN; member
Dguest_arm64_toIR.c2814 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2856 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
2922 UInt rN = INSN(9,5); in dis_ARM64_data_processing_register() local
4816 UInt rN = INSN(9,5); in dis_ARM64_load_store() local
/external/lzma/Asm/x86/
DXzCrc64Opt.asm11 rN equ r10 define
101 rN equ r7 define
D7zCrcOpt.asm9 rN equ r7 define
DAesOpt.asm19 rN equ r0 define
/external/compiler-rt/lib/builtins/arm/
Dsync_fetch_and_umin_4.S17 #define umin_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lo) argument
Dsync_fetch_and_max_4.S17 #define max_4(rD, rN, rM) MINMAX_4(rD, rN, rM, gt) argument
Dsync_fetch_and_nand_4.S17 #define nand_4(rD, rN, rM) bic rD, rN, rM argument
Dsync_fetch_and_xor_4.S17 #define xor_4(rD, rN, rM) eor rD, rN, rM argument
Dsync_fetch_and_min_4.S17 #define min_4(rD, rN, rM) MINMAX_4(rD, rN, rM, lt) argument
Dsync_fetch_and_add_4.S18 #define add_4(rD, rN, rM) add rD, rN, rM argument
Dsync_fetch_and_sub_4.S18 #define sub_4(rD, rN, rM) sub rD, rN, rM argument
Dsync_fetch_and_umax_4.S17 #define umax_4(rD, rN, rM) MINMAX_4(rD, rN, rM, hi) argument
Dsync_fetch_and_and_4.S17 #define and_4(rD, rN, rM) and rD, rN, rM argument
Dsync_fetch_and_or_4.S17 #define or_4(rD, rN, rM) orr rD, rN, rM argument
Dsync-ops.h51 #define MINMAX_4(rD, rN, rM, cmp_kind) \ argument
/external/valgrind/none/tests/arm/
Dvfp.c605 #define TESTINSN_VLDR(instruction, dD, rN, rNval, offset) \ argument
/external/v8/tools/profviz/
Dgnuplot-4.6.3-emscripten.js4496 …0,A=0,B=0,C=0,D=0,E=0,F=0,G=0,H=0,I=0,J=0,K=0,L=0,M=0,N=0,O=0,Q=0,R=0,S=0,T=0,U=0,V=0,W=0,X=0,Y=0,…
/external/v8/test/mjsunit/asm/poppler/
Dpoppler.js7321 …((e|0)==0|(b|0)==0){if((f|0)==0){f=0;a=0;break}hd[c[a+8>>2]&127](a,f);f=0;a=0;break}if((2147483647…