1//===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the TableGen definitions from which the ARM NEON header 11// file will be generated. See ARM document DUI0348B. 12// 13//===----------------------------------------------------------------------===// 14// 15// Each intrinsic is a subclass of the Inst class. An intrinsic can either 16// generate a __builtin_* call or it can expand to a set of generic operations. 17// 18// The operations are subclasses of Operation providing a list of DAGs, the 19// last of which is the return value. The available DAG nodes are documented 20// below. 21// 22//===----------------------------------------------------------------------===// 23 24// The base Operation class. All operations must subclass this. 25class Operation<list<dag> ops=[]> { 26 list<dag> Ops = ops; 27 bit Unavailable = 0; 28} 29// An operation that only contains a single DAG. 30class Op<dag op> : Operation<[op]>; 31// A shorter version of Operation - takes a list of DAGs. The last of these will 32// be the return value. 33class LOp<list<dag> ops> : Operation<ops>; 34 35// These defs and classes are used internally to implement the SetTheory 36// expansion and should be ignored. 37foreach Index = 0-63 in 38 def sv##Index; 39class MaskExpand; 40 41//===----------------------------------------------------------------------===// 42// Available operations 43//===----------------------------------------------------------------------===// 44 45// DAG arguments can either be operations (documented below) or variables. 46// Variables are prefixed with '$'. There are variables for each input argument, 47// with the name $pN, where N starts at zero. So the zero'th argument will be 48// $p0, the first $p1 etc. 49 50// op - Binary or unary operator, depending on the number of arguments. The 51// operator itself is just treated as a raw string and is not checked. 52// example: (op "+", $p0, $p1) -> "__p0 + __p1". 53// (op "-", $p0) -> "-__p0" 54def op; 55// call - Invoke another intrinsic. The input types are type checked and 56// disambiguated. If there is no intrinsic defined that takes 57// the given types (or if there is a type ambiguity) an error is 58// generated at tblgen time. The name of the intrinsic is the raw 59// name as given to the Inst class (not mangled). 60// example: (call "vget_high", $p0) -> "vgetq_high_s16(__p0)" 61// (assuming $p0 has type int16x8_t). 62def call; 63// cast - Perform a cast to a different type. This gets emitted as a static 64// C-style cast. For a pure reinterpret cast (T x = *(T*)&y), use 65// "bitcast". 66// 67// The syntax is (cast MOD* VAL). The last argument is the value to 68// cast, preceded by a sequence of type modifiers. The target type 69// starts off as the type of VAL, and is modified by MOD in sequence. 70// The available modifiers are: 71// - $X - Take the type of parameter/variable X. For example: 72// (cast $p0, $p1) would cast $p1 to the type of $p0. 73// - "R" - The type of the return type. 74// - A typedef string - A NEON or stdint.h type that is then parsed. 75// for example: (cast "uint32x4_t", $p0). 76// - "U" - Make the type unsigned. 77// - "S" - Make the type signed. 78// - "H" - Halve the number of lanes in the type. 79// - "D" - Double the number of lanes in the type. 80// - "8" - Convert type to an equivalent vector of 8-bit signed 81// integers. 82// example: (cast "R", "U", $p0) -> "(uint32x4_t)__p0" (assuming the return 83// value is of type "int32x4_t". 84// (cast $p0, "D", "8", $p1) -> "(int8x16_t)__p1" (assuming __p0 85// has type float64x1_t or any other vector type of 64 bits). 86// (cast "int32_t", $p2) -> "(int32_t)__p2" 87def cast; 88// bitcast - Same as "cast", except a reinterpret-cast is produced: 89// (bitcast "T", $p0) -> "*(T*)&__p0". 90// The VAL argument is saved to a temporary so it can be used 91// as an l-value. 92def bitcast; 93// dup - Take a scalar argument and create a vector by duplicating it into 94// all lanes. The type of the vector is the base type of the intrinsic. 95// example: (dup $p1) -> "(uint32x2_t) {__p1, __p1}" (assuming the base type 96// is uint32x2_t). 97def dup; 98// splat - Take a vector and a lane index, and return a vector of the same type 99// containing repeated instances of the source vector at the lane index. 100// example: (splat $p0, $p1) -> 101// "__builtin_shufflevector(__p0, __p0, __p1, __p1, __p1, __p1)" 102// (assuming __p0 has four elements). 103def splat; 104// save_temp - Create a temporary (local) variable. The variable takes a name 105// based on the zero'th parameter and can be referenced using 106// using that name in subsequent DAGs in the same 107// operation. The scope of a temp is the operation. If a variable 108// with the given name already exists, an error will be given at 109// tblgen time. 110// example: [(save_temp $var, (call "foo", $p0)), 111// (op "+", $var, $p1)] -> 112// "int32x2_t __var = foo(__p0); return __var + __p1;" 113def save_temp; 114// name_replace - Return the name of the current intrinsic with the first 115// argument replaced by the second argument. Raises an error if 116// the first argument does not exist in the intrinsic name. 117// example: (call (name_replace "_high_", "_"), $p0) (to call the non-high 118// version of this intrinsic). 119def name_replace; 120// literal - Create a literal piece of code. The code is treated as a raw 121// string, and must be given a type. The type is a stdint.h or 122// NEON intrinsic type as given to (cast). 123// example: (literal "int32_t", "0") 124def literal; 125// shuffle - Create a vector shuffle. The syntax is (shuffle ARG0, ARG1, MASK). 126// The MASK argument is a set of elements. The elements are generated 127// from the two special defs "mask0" and "mask1". "mask0" expands to 128// the lane indices in sequence for ARG0, and "mask1" expands to 129// the lane indices in sequence for ARG1. They can be used as-is, e.g. 130// 131// (shuffle $p0, $p1, mask0) -> $p0 132// (shuffle $p0, $p1, mask1) -> $p1 133// 134// or, more usefully, they can be manipulated using the SetTheory 135// operators plus some extra operators defined in the NEON emitter. 136// The operators are described below. 137// example: (shuffle $p0, $p1, (add (highhalf mask0), (highhalf mask1))) -> 138// A concatenation of the high halves of the input vectors. 139def shuffle; 140 141// add, interleave, decimate: These set operators are vanilla SetTheory 142// operators and take their normal definition. 143def add; 144def interleave; 145def decimate; 146// rotl - Rotate set left by a number of elements. 147// example: (rotl mask0, 3) -> [3, 4, 5, 6, 0, 1, 2] 148def rotl; 149// rotl - Rotate set right by a number of elements. 150// example: (rotr mask0, 3) -> [4, 5, 6, 0, 1, 2, 3] 151def rotr; 152// highhalf - Take only the high half of the input. 153// example: (highhalf mask0) -> [4, 5, 6, 7] (assuming mask0 had 8 elements) 154def highhalf; 155// highhalf - Take only the low half of the input. 156// example: (lowhalf mask0) -> [0, 1, 2, 3] (assuming mask0 had 8 elements) 157def lowhalf; 158// rev - Perform a variable-width reversal of the elements. The zero'th argument 159// is a width in bits to reverse. The lanes this maps to is determined 160// based on the element width of the underlying type. 161// example: (rev 32, mask0) -> [3, 2, 1, 0, 7, 6, 5, 4] (if 8-bit elements) 162// example: (rev 32, mask0) -> [1, 0, 3, 2] (if 16-bit elements) 163def rev; 164// mask0 - The initial sequence of lanes for shuffle ARG0 165def mask0 : MaskExpand; 166// mask0 - The initial sequence of lanes for shuffle ARG1 167def mask1 : MaskExpand; 168 169def OP_NONE : Operation; 170def OP_UNAVAILABLE : Operation { 171 let Unavailable = 1; 172} 173 174//===----------------------------------------------------------------------===// 175// Instruction definitions 176//===----------------------------------------------------------------------===// 177 178// Every intrinsic subclasses "Inst". An intrinsic has a name, a prototype and 179// a sequence of typespecs. 180// 181// The name is the base name of the intrinsic, for example "vget_lane". This is 182// then mangled by the tblgen backend to add type information ("vget_lane_s16"). 183// 184// A typespec is a sequence of uppercase characters (modifiers) followed by one 185// lowercase character. A typespec encodes a particular "base type" of the 186// intrinsic. 187// 188// An example typespec is "Qs" - quad-size short - uint16x8_t. The available 189// typespec codes are given below. 190// 191// The string given to an Inst class is a sequence of typespecs. The intrinsic 192// is instantiated for every typespec in the sequence. For example "sdQsQd". 193// 194// The prototype is a string that defines the return type of the intrinsic 195// and the type of each argument. The return type and every argument gets a 196// "modifier" that can change in some way the "base type" of the intrinsic. 197// 198// The modifier 'd' means "default" and does not modify the base type in any 199// way. The available modifiers are given below. 200// 201// Typespecs 202// --------- 203// c: char 204// s: short 205// i: int 206// l: long 207// k: 128-bit long 208// f: float 209// h: half-float 210// d: double 211// 212// Typespec modifiers 213// ------------------ 214// S: scalar, only used for function mangling. 215// U: unsigned 216// Q: 128b 217// H: 128b without mangling 'q' 218// P: polynomial 219// 220// Prototype modifiers 221// ------------------- 222// prototype: return (arg, arg, ...) 223// 224// v: void 225// t: best-fit integer (int/poly args) 226// x: signed integer (int/float args) 227// u: unsigned integer (int/float args) 228// f: float (int args) 229// F: double (int args) 230// d: default 231// g: default, ignore 'Q' size modifier. 232// j: default, force 'Q' size modifier. 233// w: double width elements, same num elts 234// n: double width elements, half num elts 235// h: half width elements, double num elts 236// q: half width elements, quad num elts 237// e: half width elements, double num elts, unsigned 238// m: half width elements, same num elts 239// i: constant int 240// l: constant uint64 241// s: scalar of element type 242// z: scalar of half width element type, signed 243// r: scalar of double width element type, signed 244// a: scalar of element type (splat to vector type) 245// b: scalar of unsigned integer/long type (int/float args) 246// $: scalar of signed integer/long type (int/float args) 247// y: scalar of float 248// o: scalar of double 249// k: default elt width, double num elts 250// 2,3,4: array of default vectors 251// B,C,D: array of default elts, force 'Q' size modifier. 252// p: pointer type 253// c: const pointer type 254 255// Every intrinsic subclasses Inst. 256class Inst <string n, string p, string t, Operation o> { 257 string Name = n; 258 string Prototype = p; 259 string Types = t; 260 string ArchGuard = ""; 261 262 Operation Operation = o; 263 bit CartesianProductOfTypes = 0; 264 bit BigEndianSafe = 0; 265 bit isShift = 0; 266 bit isScalarShift = 0; 267 bit isScalarNarrowShift = 0; 268 bit isVCVT_N = 0; 269 // For immediate checks: the immediate will be assumed to specify the lane of 270 // a Q register. Only used for intrinsics which end up calling polymorphic 271 // builtins. 272 bit isLaneQ = 0; 273 274 // Certain intrinsics have different names than their representative 275 // instructions. This field allows us to handle this correctly when we 276 // are generating tests. 277 string InstName = ""; 278 279 // Certain intrinsics even though they are not a WOpInst or LOpInst, 280 // generate a WOpInst/LOpInst instruction (see below for definition 281 // of a WOpInst/LOpInst). For testing purposes we need to know 282 // this. Ex: vset_lane which outputs vmov instructions. 283 bit isHiddenWInst = 0; 284 bit isHiddenLInst = 0; 285} 286 287// The following instruction classes are implemented via builtins. 288// These declarations are used to generate Builtins.def: 289// 290// SInst: Instruction with signed/unsigned suffix (e.g., "s8", "u8", "p8") 291// IInst: Instruction with generic integer suffix (e.g., "i8") 292// WInst: Instruction with only bit size suffix (e.g., "8") 293class SInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 294class IInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 295class WInst<string n, string p, string t> : Inst<n, p, t, OP_NONE> {} 296 297// The following instruction classes are implemented via operators 298// instead of builtins. As such these declarations are only used for 299// the purpose of generating tests. 300// 301// SOpInst: Instruction with signed/unsigned suffix (e.g., "s8", 302// "u8", "p8"). 303// IOpInst: Instruction with generic integer suffix (e.g., "i8"). 304// WOpInst: Instruction with bit size only suffix (e.g., "8"). 305// LOpInst: Logical instruction with no bit size suffix. 306// NoTestOpInst: Intrinsic that has no corresponding instruction. 307class SOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 308class IOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 309class WOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 310class LOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 311class NoTestOpInst<string n, string p, string t, Operation o> : Inst<n, p, t, o> {} 312 313//===----------------------------------------------------------------------===// 314// Operations 315//===----------------------------------------------------------------------===// 316 317def OP_ADD : Op<(op "+", $p0, $p1)>; 318def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>; 319def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0), 320 (call "vmovl_high", $p1))>; 321def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>; 322def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>; 323def OP_SUB : Op<(op "-", $p0, $p1)>; 324def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>; 325def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0), 326 (call "vmovl_high", $p1))>; 327def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>; 328def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>; 329def OP_MUL : Op<(op "*", $p0, $p1)>; 330def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>; 331def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>; 332def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0), 333 (call "vget_high", $p1))>; 334def OP_MULLHi_P64 : Op<(call "vmull", 335 (cast "poly64_t", (call "vget_high", $p0)), 336 (cast "poly64_t", (call "vget_high", $p1)))>; 337def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>; 338def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1), 339 (call "vget_high", $p2))>; 340def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>; 341def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>; 342def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>; 343def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1), 344 (call "vget_high", $p2))>; 345def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 346def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>; 347def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>; 348def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>; 349def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>; 350def OP_FMLS_N : Op<(call "vfms", $p0, $p1, (dup $p2))>; 351def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>; 352def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>; 353def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>; 354def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>; 355def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>; 356def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>; 357def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>; 358def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>; 359def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 360def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1), 361 (splat $p2, $p3)))>; 362def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 363def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1), 364 (splat $p2, $p3)))>; 365def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>; 366def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0), 367 (splat $p1, $p2))>; 368def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (splat $p2, $p3))>; 369def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 370 (splat $p2, $p3))>; 371def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>; 372def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 373 (splat $p2, $p3))>; 374def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>; 375def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>; 376def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>; 377def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>; 378def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>; 379def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>; 380def OP_FMS_LN : Op<(call "vfma_lane", $p0, $p1, (op "-", $p2), $p3)>; 381def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, $p1, (op "-", $p2), $p3)>; 382def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2), 383 (decimate mask1, 2)))>; 384def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>; 385def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2), 386 (decimate mask1, 2)))>; 387def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave 388 (decimate (rotl mask0, 1), 2), 389 (decimate (rotl mask1, 1), 2)))>; 390def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>; 391def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2), 392 (decimate (rotl mask1, 1), 2)))>; 393def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>; 394def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>; 395def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>; 396def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>; 397def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>; 398def OP_NEG : Op<(op "-", $p0)>; 399def OP_NOT : Op<(op "~", $p0)>; 400def OP_AND : Op<(op "&", $p0, $p1)>; 401def OP_OR : Op<(op "|", $p0, $p1)>; 402def OP_XOR : Op<(op "^", $p0, $p1)>; 403def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>; 404def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>; 405def OP_CAST : Op<(cast "R", $p0)>; 406def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>; 407def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>; 408def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>; 409def OP_DUP : Op<(dup $p0)>; 410def OP_DUP_LN : Op<(splat $p0, $p1)>; 411def OP_SEL : Op<(cast "R", (op "|", 412 (op "&", $p0, (cast $p0, $p1)), 413 (op "&", (op "~", $p0), (cast $p0, $p2))))>; 414def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>; 415def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>; 416def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>; 417def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>; 418def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0), 419 (call "vqmovun", $p1))>; 420def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>; 421def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16_f32", $p1))>; 422def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>; 423def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>; 424def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>; 425def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>; 426def OP_REINT : Op<(cast "R", $p0)>; 427def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>; 428def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>; 429def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>; 430def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>; 431def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U", 432 (call "vabd", $p0, $p1))))>; 433def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0), 434 (call "vget_high", $p1))>; 435def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>; 436def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>; 437def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1), 438 (call "vget_high", $p2))>; 439def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0), 440 (call "vget_high", $p1))>; 441def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>; 442def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 443 (call "vget_high", $p2))>; 444def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>; 445def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 446 (call "vget_high", $p2))>; 447def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 448def OP_DIV : Op<(op "/", $p0, $p1)>; 449def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"), 450 (call "vget_high", $p0), $p1))>; 451def OP_NARROW_HI : Op<(cast "R", (call "vcombine", 452 (cast "R", "H", $p0), 453 (cast "R", "H", 454 (call (name_replace "_high_", "_"), 455 $p1, $p2))))>; 456def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)), 457 (cast "R", 458 (call "vshll_n", $a1, (literal "int32_t", "0")))]>; 459def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>; 460def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>; 461def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>; 462def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0, 463 (literal "int32_t", "0"))), 464 (save_temp $y, (call "vget_lane", $p1, $p2)), 465 (save_temp $z, (call "vmulx", $x, $y)), 466 (call "vset_lane", $z, $p0, $p2)]>; 467def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0, 468 (literal "int32_t", "0"))), 469 (save_temp $y, (call "vget_lane", $p1, $p2)), 470 (save_temp $z, (call "vmulx", $x, $y)), 471 (call "vset_lane", $z, $p0, (literal "int32_t", 472 "0"))]>; 473class ScalarMulOp<string opname> : 474 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>; 475 476def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">; 477def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">; 478def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">; 479 480def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, 481 (call "vget_lane", $p2, $p3)))>; 482def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, 483 (call "vget_lane", $p2, $p3)))>; 484 485def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t", 486 (call "vget_lane", 487 (bitcast "int16x4_t", $p0), $p1))>; 488def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t", 489 (call "vget_lane", 490 (bitcast "int16x8_t", $p0), $p1))>; 491def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t", 492 (call "vset_lane", 493 (bitcast "int16_t", $p0), 494 (bitcast "int16x4_t", $p1), $p2))>; 495def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t", 496 (call "vset_lane", 497 (bitcast "int16_t", $p0), 498 (bitcast "int16x8_t", $p1), $p2))>; 499 500//===----------------------------------------------------------------------===// 501// Instructions 502//===----------------------------------------------------------------------===// 503 504//////////////////////////////////////////////////////////////////////////////// 505// E.3.1 Addition 506def VADD : IOpInst<"vadd", "ddd", 507 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 508def VADDL : SOpInst<"vaddl", "wdd", "csiUcUsUi", OP_ADDL>; 509def VADDW : SOpInst<"vaddw", "wwd", "csiUcUsUi", OP_ADDW>; 510def VHADD : SInst<"vhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 511def VRHADD : SInst<"vrhadd", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 512def VQADD : SInst<"vqadd", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 513def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">; 514def VRADDHN : IInst<"vraddhn", "hkk", "silUsUiUl">; 515 516//////////////////////////////////////////////////////////////////////////////// 517// E.3.2 Multiplication 518def VMUL : IOpInst<"vmul", "ddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 519def VMULP : SInst<"vmul", "ddd", "PcQPc">; 520def VMLA : IOpInst<"vmla", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 521def VMLAL : SOpInst<"vmlal", "wwdd", "csiUcUsUi", OP_MLAL>; 522def VMLS : IOpInst<"vmls", "dddd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 523def VMLSL : SOpInst<"vmlsl", "wwdd", "csiUcUsUi", OP_MLSL>; 524def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">; 525def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">; 526 527let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in { 528def VQRDMLAH : SOpInst<"vqrdmlah", "dddd", "siQsQi", OP_QRDMLAH>; 529def VQRDMLSH : SOpInst<"vqrdmlsh", "dddd", "siQsQi", OP_QRDMLSH>; 530} 531 532def VQDMLAL : SInst<"vqdmlal", "wwdd", "si">; 533def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">; 534def VMULL : SInst<"vmull", "wdd", "csiUcUsUiPc">; 535def VQDMULL : SInst<"vqdmull", "wdd", "si">; 536 537//////////////////////////////////////////////////////////////////////////////// 538// E.3.3 Subtraction 539def VSUB : IOpInst<"vsub", "ddd", 540 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 541def VSUBL : SOpInst<"vsubl", "wdd", "csiUcUsUi", OP_SUBL>; 542def VSUBW : SOpInst<"vsubw", "wwd", "csiUcUsUi", OP_SUBW>; 543def VQSUB : SInst<"vqsub", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 544def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">; 545def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">; 546def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">; 547 548//////////////////////////////////////////////////////////////////////////////// 549// E.3.4 Comparison 550def VCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 551def VCGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 552let InstName = "vcge" in 553def VCLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 554def VCGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 555let InstName = "vcgt" in 556def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 557let InstName = "vacge" in { 558def VCAGE : IInst<"vcage", "udd", "fQf">; 559def VCALE : IInst<"vcale", "udd", "fQf">; 560} 561let InstName = "vacgt" in { 562def VCAGT : IInst<"vcagt", "udd", "fQf">; 563def VCALT : IInst<"vcalt", "udd", "fQf">; 564} 565def VTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">; 566 567//////////////////////////////////////////////////////////////////////////////// 568// E.3.5 Absolute Difference 569def VABD : SInst<"vabd", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 570def VABDL : SOpInst<"vabdl", "wdd", "csiUcUsUi", OP_ABDL>; 571def VABA : SOpInst<"vaba", "dddd", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 572def VABAL : SOpInst<"vabal", "wwdd", "csiUcUsUi", OP_ABAL>; 573 574//////////////////////////////////////////////////////////////////////////////// 575// E.3.6 Max/Min 576def VMAX : SInst<"vmax", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 577def VMIN : SInst<"vmin", "ddd", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 578 579//////////////////////////////////////////////////////////////////////////////// 580// E.3.7 Pairwise Addition 581def VPADD : IInst<"vpadd", "ddd", "csiUcUsUif">; 582def VPADDL : SInst<"vpaddl", "nd", "csiUcUsUiQcQsQiQUcQUsQUi">; 583def VPADAL : SInst<"vpadal", "nnd", "csiUcUsUiQcQsQiQUcQUsQUi">; 584 585//////////////////////////////////////////////////////////////////////////////// 586// E.3.8-9 Folding Max/Min 587def VPMAX : SInst<"vpmax", "ddd", "csiUcUsUif">; 588def VPMIN : SInst<"vpmin", "ddd", "csiUcUsUif">; 589 590//////////////////////////////////////////////////////////////////////////////// 591// E.3.10 Reciprocal/Sqrt 592def VRECPS : IInst<"vrecps", "ddd", "fQf">; 593def VRSQRTS : IInst<"vrsqrts", "ddd", "fQf">; 594 595//////////////////////////////////////////////////////////////////////////////// 596// E.3.11 Shifts by signed variable 597def VSHL : SInst<"vshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 598def VQSHL : SInst<"vqshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 599def VRSHL : SInst<"vrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 600def VQRSHL : SInst<"vqrshl", "ddx", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 601 602//////////////////////////////////////////////////////////////////////////////// 603// E.3.12 Shifts by constant 604let isShift = 1 in { 605def VSHR_N : SInst<"vshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 606def VSHL_N : IInst<"vshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 607def VRSHR_N : SInst<"vrshr_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 608def VSRA_N : SInst<"vsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 609def VRSRA_N : SInst<"vrsra_n", "dddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 610def VQSHL_N : SInst<"vqshl_n", "ddi", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 611def VQSHLU_N : SInst<"vqshlu_n", "udi", "csilQcQsQiQl">; 612def VSHRN_N : IInst<"vshrn_n", "hki", "silUsUiUl">; 613def VQSHRUN_N : SInst<"vqshrun_n", "eki", "sil">; 614def VQRSHRUN_N : SInst<"vqrshrun_n", "eki", "sil">; 615def VQSHRN_N : SInst<"vqshrn_n", "hki", "silUsUiUl">; 616def VRSHRN_N : IInst<"vrshrn_n", "hki", "silUsUiUl">; 617def VQRSHRN_N : SInst<"vqrshrn_n", "hki", "silUsUiUl">; 618def VSHLL_N : SInst<"vshll_n", "wdi", "csiUcUsUi">; 619 620//////////////////////////////////////////////////////////////////////////////// 621// E.3.13 Shifts with insert 622def VSRI_N : WInst<"vsri_n", "dddi", 623 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 624def VSLI_N : WInst<"vsli_n", "dddi", 625 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 626} 627 628//////////////////////////////////////////////////////////////////////////////// 629// E.3.14 Loads and stores of a single vector 630def VLD1 : WInst<"vld1", "dc", 631 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 632def VLD1_LANE : WInst<"vld1_lane", "dcdi", 633 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 634def VLD1_DUP : WInst<"vld1_dup", "dc", 635 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 636def VST1 : WInst<"vst1", "vpd", 637 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 638def VST1_LANE : WInst<"vst1_lane", "vpdi", 639 "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 640 641//////////////////////////////////////////////////////////////////////////////// 642// E.3.15 Loads and stores of an N-element structure 643def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 644def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 645def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 646def VLD2_DUP : WInst<"vld2_dup", "2c", "UcUsUiUlcsilhfPcPs">; 647def VLD3_DUP : WInst<"vld3_dup", "3c", "UcUsUiUlcsilhfPcPs">; 648def VLD4_DUP : WInst<"vld4_dup", "4c", "UcUsUiUlcsilhfPcPs">; 649def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 650def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 651def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 652def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 653def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 654def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">; 655def VST2_LANE : WInst<"vst2_lane", "vp2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 656def VST3_LANE : WInst<"vst3_lane", "vp3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 657def VST4_LANE : WInst<"vst4_lane", "vp4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">; 658 659//////////////////////////////////////////////////////////////////////////////// 660// E.3.16 Extract lanes from a vector 661let InstName = "vmov" in 662def VGET_LANE : IInst<"vget_lane", "sdi", 663 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 664 665//////////////////////////////////////////////////////////////////////////////// 666// E.3.17 Set lanes within a vector 667let InstName = "vmov" in 668def VSET_LANE : IInst<"vset_lane", "dsdi", 669 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 670 671//////////////////////////////////////////////////////////////////////////////// 672// E.3.18 Initialize a vector from bit pattern 673def VCREATE : NoTestOpInst<"vcreate", "dl", "csihfUcUsUiUlPcPsl", OP_CAST> { 674 let BigEndianSafe = 1; 675} 676 677//////////////////////////////////////////////////////////////////////////////// 678// E.3.19 Set all lanes to same value 679let InstName = "vmov" in { 680def VDUP_N : WOpInst<"vdup_n", "ds", 681 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 682 OP_DUP>; 683def VMOV_N : WOpInst<"vmov_n", "ds", 684 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 685 OP_DUP>; 686} 687let InstName = "" in 688def VDUP_LANE: WOpInst<"vdup_lane", "dgi", 689 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 690 OP_DUP_LN>; 691 692//////////////////////////////////////////////////////////////////////////////// 693// E.3.20 Combining vectors 694def VCOMBINE : NoTestOpInst<"vcombine", "kdd", "csilhfUcUsUiUlPcPs", OP_CONC>; 695 696//////////////////////////////////////////////////////////////////////////////// 697// E.3.21 Splitting vectors 698let InstName = "vmov" in { 699def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>; 700def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>; 701} 702 703//////////////////////////////////////////////////////////////////////////////// 704// E.3.22 Converting vectors 705 706def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "md", "Hf">; 707def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "wd", "h">; 708 709def VCVT_S32 : SInst<"vcvt_s32", "xd", "fQf">; 710def VCVT_U32 : SInst<"vcvt_u32", "ud", "fQf">; 711def VCVT_F32 : SInst<"vcvt_f32", "fd", "iUiQiQUi">; 712let isVCVT_N = 1 in { 713def VCVT_N_S32 : SInst<"vcvt_n_s32", "xdi", "fQf">; 714def VCVT_N_U32 : SInst<"vcvt_n_u32", "udi", "fQf">; 715def VCVT_N_F32 : SInst<"vcvt_n_f32", "fdi", "iUiQiQUi">; 716} 717 718def VMOVN : IInst<"vmovn", "hk", "silUsUiUl">; 719def VMOVL : SInst<"vmovl", "wd", "csiUcUsUi">; 720def VQMOVN : SInst<"vqmovn", "hk", "silUsUiUl">; 721def VQMOVUN : SInst<"vqmovun", "ek", "sil">; 722 723//////////////////////////////////////////////////////////////////////////////// 724// E.3.23-24 Table lookup, Extended table lookup 725let InstName = "vtbl" in { 726def VTBL1 : WInst<"vtbl1", "ddt", "UccPc">; 727def VTBL2 : WInst<"vtbl2", "d2t", "UccPc">; 728def VTBL3 : WInst<"vtbl3", "d3t", "UccPc">; 729def VTBL4 : WInst<"vtbl4", "d4t", "UccPc">; 730} 731let InstName = "vtbx" in { 732def VTBX1 : WInst<"vtbx1", "dddt", "UccPc">; 733def VTBX2 : WInst<"vtbx2", "dd2t", "UccPc">; 734def VTBX3 : WInst<"vtbx3", "dd3t", "UccPc">; 735def VTBX4 : WInst<"vtbx4", "dd4t", "UccPc">; 736} 737 738//////////////////////////////////////////////////////////////////////////////// 739// E.3.25 Operations with a scalar value 740def VMLA_LANE : IOpInst<"vmla_lane", "dddgi", 741 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 742def VMLAL_LANE : SOpInst<"vmlal_lane", "wwddi", "siUsUi", OP_MLAL_LN>; 743def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "wwddi", "si", OP_QDMLAL_LN>; 744def VMLS_LANE : IOpInst<"vmls_lane", "dddgi", 745 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 746def VMLSL_LANE : SOpInst<"vmlsl_lane", "wwddi", "siUsUi", OP_MLSL_LN>; 747def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "wwddi", "si", OP_QDMLSL_LN>; 748def VMUL_N : IOpInst<"vmul_n", "dds", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 749def VMUL_LANE : IOpInst<"vmul_lane", "ddgi", 750 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 751def VMULL_N : SInst<"vmull_n", "wda", "siUsUi">; 752def VMULL_LANE : SOpInst<"vmull_lane", "wddi", "siUsUi", OP_MULL_LN>; 753def VQDMULL_N : SInst<"vqdmull_n", "wda", "si">; 754def VQDMULL_LANE : SOpInst<"vqdmull_lane", "wddi", "si", OP_QDMULL_LN>; 755def VQDMULH_N : SInst<"vqdmulh_n", "dda", "siQsQi">; 756def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "ddgi", "siQsQi", OP_QDMULH_LN>; 757def VQRDMULH_N : SInst<"vqrdmulh_n", "dda", "siQsQi">; 758def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ddgi", "siQsQi", OP_QRDMULH_LN>; 759 760let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in { 761def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "dddgi", "siQsQi", OP_QRDMLAH_LN>; 762def VQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "dddgi", "siQsQi", OP_QRDMLSH_LN>; 763} 764 765def VMLA_N : IOpInst<"vmla_n", "ddda", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 766def VMLAL_N : SOpInst<"vmlal_n", "wwda", "siUsUi", OP_MLAL_N>; 767def VQDMLAL_N : SInst<"vqdmlal_n", "wwda", "si">; 768def VMLS_N : IOpInst<"vmls_n", "ddds", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 769def VMLSL_N : SOpInst<"vmlsl_n", "wwda", "siUsUi", OP_MLSL_N>; 770def VQDMLSL_N : SInst<"vqdmlsl_n", "wwda", "si">; 771 772//////////////////////////////////////////////////////////////////////////////// 773// E.3.26 Vector Extract 774def VEXT : WInst<"vext", "dddi", 775 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 776 777//////////////////////////////////////////////////////////////////////////////// 778// E.3.27 Reverse vector elements 779def VREV64 : WOpInst<"vrev64", "dd", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 780 OP_REV64>; 781def VREV32 : WOpInst<"vrev32", "dd", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 782def VREV16 : WOpInst<"vrev16", "dd", "cUcPcQcQUcQPc", OP_REV16>; 783 784//////////////////////////////////////////////////////////////////////////////// 785// E.3.28 Other single operand arithmetic 786def VABS : SInst<"vabs", "dd", "csifQcQsQiQf">; 787def VQABS : SInst<"vqabs", "dd", "csiQcQsQi">; 788def VNEG : SOpInst<"vneg", "dd", "csifQcQsQiQf", OP_NEG>; 789def VQNEG : SInst<"vqneg", "dd", "csiQcQsQi">; 790def VCLS : SInst<"vcls", "dd", "csiQcQsQi">; 791def VCLZ : IInst<"vclz", "dd", "csiUcUsUiQcQsQiQUcQUsQUi">; 792def VCNT : WInst<"vcnt", "dd", "UccPcQUcQcQPc">; 793def VRECPE : SInst<"vrecpe", "dd", "fUiQfQUi">; 794def VRSQRTE : SInst<"vrsqrte", "dd", "fUiQfQUi">; 795 796//////////////////////////////////////////////////////////////////////////////// 797// E.3.29 Logical operations 798def VMVN : LOpInst<"vmvn", "dd", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 799def VAND : LOpInst<"vand", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 800def VORR : LOpInst<"vorr", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 801def VEOR : LOpInst<"veor", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 802def VBIC : LOpInst<"vbic", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 803def VORN : LOpInst<"vorn", "ddd", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 804let isHiddenLInst = 1 in 805def VBSL : SInst<"vbsl", "dudd", 806 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 807 808//////////////////////////////////////////////////////////////////////////////// 809// E.3.30 Transposition operations 810def VTRN : WInst<"vtrn", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 811def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 812def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 813 814//////////////////////////////////////////////////////////////////////////////// 815// E.3.31 Vector reinterpret cast operations 816def VREINTERPRET 817 : NoTestOpInst<"vreinterpret", "dd", 818 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> { 819 let CartesianProductOfTypes = 1; 820 let ArchGuard = "!defined(__aarch64__)"; 821 let BigEndianSafe = 1; 822} 823 824//////////////////////////////////////////////////////////////////////////////// 825// Vector fused multiply-add operations 826 827def VFMA : SInst<"vfma", "dddd", "fQf">; 828 829//////////////////////////////////////////////////////////////////////////////// 830// fp16 vector operations 831def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "sdi", "h", OP_SCALAR_HALF_GET_LN>; 832def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", "dsdi", "h", OP_SCALAR_HALF_SET_LN>; 833def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "sdi", "Qh", OP_SCALAR_HALF_GET_LNQ>; 834def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", "dsdi", "Qh", OP_SCALAR_HALF_SET_LNQ>; 835 836//////////////////////////////////////////////////////////////////////////////// 837// AArch64 Intrinsics 838 839let ArchGuard = "defined(__aarch64__)" in { 840 841//////////////////////////////////////////////////////////////////////////////// 842// Load/Store 843def LD1 : WInst<"vld1", "dc", "dQdPlQPl">; 844def LD2 : WInst<"vld2", "2c", "QUlQldQdPlQPl">; 845def LD3 : WInst<"vld3", "3c", "QUlQldQdPlQPl">; 846def LD4 : WInst<"vld4", "4c", "QUlQldQdPlQPl">; 847def ST1 : WInst<"vst1", "vpd", "dQdPlQPl">; 848def ST2 : WInst<"vst2", "vp2", "QUlQldQdPlQPl">; 849def ST3 : WInst<"vst3", "vp3", "QUlQldQdPlQPl">; 850def ST4 : WInst<"vst4", "vp4", "QUlQldQdPlQPl">; 851 852def LD1_X2 : WInst<"vld1_x2", "2c", 853 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 854def LD3_x3 : WInst<"vld1_x3", "3c", 855 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 856def LD4_x4 : WInst<"vld1_x4", "4c", 857 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 858 859def ST1_X2 : WInst<"vst1_x2", "vp2", 860 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 861def ST1_X3 : WInst<"vst1_x3", "vp3", 862 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 863def ST1_X4 : WInst<"vst1_x4", "vp4", 864 "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPsQUlQldQdPlQPl">; 865 866def LD1_LANE : WInst<"vld1_lane", "dcdi", "dQdPlQPl">; 867def LD2_LANE : WInst<"vld2_lane", "2c2i", "lUlQcQUcQPcQlQUldQdPlQPl">; 868def LD3_LANE : WInst<"vld3_lane", "3c3i", "lUlQcQUcQPcQlQUldQdPlQPl">; 869def LD4_LANE : WInst<"vld4_lane", "4c4i", "lUlQcQUcQPcQlQUldQdPlQPl">; 870def ST1_LANE : WInst<"vst1_lane", "vpdi", "dQdPlQPl">; 871def ST2_LANE : WInst<"vst2_lane", "vp2i", "lUlQcQUcQPcQlQUldQdPlQPl">; 872def ST3_LANE : WInst<"vst3_lane", "vp3i", "lUlQcQUcQPcQlQUldQdPlQPl">; 873def ST4_LANE : WInst<"vst4_lane", "vp4i", "lUlQcQUcQPcQlQUldQdPlQPl">; 874 875def LD1_DUP : WInst<"vld1_dup", "dc", "dQdPlQPl">; 876def LD2_DUP : WInst<"vld2_dup", "2c", 877 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 878def LD3_DUP : WInst<"vld3_dup", "3c", 879 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 880def LD4_DUP : WInst<"vld4_dup", "4c", 881 "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPldPl">; 882 883def VLDRQ : WInst<"vldrq", "sc", "Pk">; 884def VSTRQ : WInst<"vstrq", "vps", "Pk">; 885 886//////////////////////////////////////////////////////////////////////////////// 887// Addition 888def ADD : IOpInst<"vadd", "ddd", "dQd", OP_ADD>; 889 890//////////////////////////////////////////////////////////////////////////////// 891// Subtraction 892def SUB : IOpInst<"vsub", "ddd", "dQd", OP_SUB>; 893 894//////////////////////////////////////////////////////////////////////////////// 895// Multiplication 896def MUL : IOpInst<"vmul", "ddd", "dQd", OP_MUL>; 897def MLA : IOpInst<"vmla", "dddd", "dQd", OP_MLA>; 898def MLS : IOpInst<"vmls", "dddd", "dQd", OP_MLS>; 899 900//////////////////////////////////////////////////////////////////////////////// 901// Multiplication Extended 902def MULX : SInst<"vmulx", "ddd", "fdQfQd">; 903 904//////////////////////////////////////////////////////////////////////////////// 905// Division 906def FDIV : IOpInst<"vdiv", "ddd", "fdQfQd", OP_DIV>; 907 908//////////////////////////////////////////////////////////////////////////////// 909// Vector fused multiply-add operations 910def FMLA : SInst<"vfma", "dddd", "dQd">; 911def FMLS : SInst<"vfms", "dddd", "fdQfQd">; 912 913//////////////////////////////////////////////////////////////////////////////// 914// MUL, MLA, MLS, FMA, FMS definitions with scalar argument 915def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>; 916 917def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>; 918def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>; 919 920def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>; 921def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>; 922 923//////////////////////////////////////////////////////////////////////////////// 924// Logical operations 925def BSL : SInst<"vbsl", "dudd", "dPlQdQPl">; 926 927//////////////////////////////////////////////////////////////////////////////// 928// Absolute Difference 929def ABD : SInst<"vabd", "ddd", "dQd">; 930 931//////////////////////////////////////////////////////////////////////////////// 932// saturating absolute/negate 933def ABS : SInst<"vabs", "dd", "dQdlQl">; 934def QABS : SInst<"vqabs", "dd", "lQl">; 935def NEG : SOpInst<"vneg", "dd", "dlQdQl", OP_NEG>; 936def QNEG : SInst<"vqneg", "dd", "lQl">; 937 938//////////////////////////////////////////////////////////////////////////////// 939// Signed Saturating Accumulated of Unsigned Value 940def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">; 941 942//////////////////////////////////////////////////////////////////////////////// 943// Unsigned Saturating Accumulated of Signed Value 944def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">; 945 946//////////////////////////////////////////////////////////////////////////////// 947// Reciprocal/Sqrt 948def FRECPS : IInst<"vrecps", "ddd", "dQd">; 949def FRSQRTS : IInst<"vrsqrts", "ddd", "dQd">; 950def FRECPE : SInst<"vrecpe", "dd", "dQd">; 951def FRSQRTE : SInst<"vrsqrte", "dd", "dQd">; 952def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; 953 954//////////////////////////////////////////////////////////////////////////////// 955// bitwise reverse 956def RBIT : IInst<"vrbit", "dd", "cUcPcQcQUcQPc">; 957 958//////////////////////////////////////////////////////////////////////////////// 959// Integer extract and narrow to high 960def XTN2 : SOpInst<"vmovn_high", "qhk", "silUsUiUl", OP_XTN>; 961 962//////////////////////////////////////////////////////////////////////////////// 963// Signed integer saturating extract and unsigned narrow to high 964def SQXTUN2 : SOpInst<"vqmovun_high", "qhk", "sil", OP_SQXTUN>; 965 966//////////////////////////////////////////////////////////////////////////////// 967// Integer saturating extract and narrow to high 968def QXTN2 : SOpInst<"vqmovn_high", "qhk", "silUsUiUl", OP_QXTN>; 969 970//////////////////////////////////////////////////////////////////////////////// 971// Converting vectors 972 973def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "md", "Qd">; 974def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "wd", "f">; 975 976def VCVT_S64 : SInst<"vcvt_s64", "xd", "dQd">; 977def VCVT_U64 : SInst<"vcvt_u64", "ud", "dQd">; 978def VCVT_F64 : SInst<"vcvt_f64", "Fd", "lUlQlQUl">; 979 980def VCVT_HIGH_F16_F32 : SOpInst<"vcvt_high_f16", "hmj", "Hf", OP_VCVT_NA_HI_F16>; 981def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "wk", "h", OP_VCVT_EX_HI_F32>; 982def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "qfj", "d", OP_VCVT_NA_HI_F32>; 983def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "wj", "f", OP_VCVT_EX_HI_F64>; 984 985def VCVTX_F32_F64 : SInst<"vcvtx_f32", "fj", "d">; 986def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "qfj", "d", OP_VCVTX_HI>; 987 988//////////////////////////////////////////////////////////////////////////////// 989// Comparison 990def FCAGE : IInst<"vcage", "udd", "dQd">; 991def FCAGT : IInst<"vcagt", "udd", "dQd">; 992def FCALE : IInst<"vcale", "udd", "dQd">; 993def FCALT : IInst<"vcalt", "udd", "dQd">; 994def CMTST : WInst<"vtst", "udd", "lUlPlQlQUlQPl">; 995def CFMEQ : SOpInst<"vceq", "udd", "lUldQdQlQUlPlQPl", OP_EQ>; 996def CFMGE : SOpInst<"vcge", "udd", "lUldQdQlQUl", OP_GE>; 997def CFMLE : SOpInst<"vcle", "udd", "lUldQdQlQUl", OP_LE>; 998def CFMGT : SOpInst<"vcgt", "udd", "lUldQdQlQUl", OP_GT>; 999def CFMLT : SOpInst<"vclt", "udd", "lUldQdQlQUl", OP_LT>; 1000 1001def CMEQ : SInst<"vceqz", "ud", 1002 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; 1003def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">; 1004def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">; 1005def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">; 1006def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">; 1007 1008//////////////////////////////////////////////////////////////////////////////// 1009// Max/Min Integer 1010def MAX : SInst<"vmax", "ddd", "dQd">; 1011def MIN : SInst<"vmin", "ddd", "dQd">; 1012 1013//////////////////////////////////////////////////////////////////////////////// 1014// Pairwise Max/Min 1015def MAXP : SInst<"vpmax", "ddd", "QcQsQiQUcQUsQUiQfQd">; 1016def MINP : SInst<"vpmin", "ddd", "QcQsQiQUcQUsQUiQfQd">; 1017 1018//////////////////////////////////////////////////////////////////////////////// 1019// Pairwise MaxNum/MinNum Floating Point 1020def FMAXNMP : SInst<"vpmaxnm", "ddd", "fQfQd">; 1021def FMINNMP : SInst<"vpminnm", "ddd", "fQfQd">; 1022 1023//////////////////////////////////////////////////////////////////////////////// 1024// Pairwise Addition 1025def ADDP : IInst<"vpadd", "ddd", "QcQsQiQlQUcQUsQUiQUlQfQd">; 1026 1027//////////////////////////////////////////////////////////////////////////////// 1028// Shifts by constant 1029let isShift = 1 in { 1030// Left shift long high 1031def SHLL_HIGH_N : SOpInst<"vshll_high_n", "ndi", "HcHsHiHUcHUsHUi", 1032 OP_LONG_HI>; 1033 1034//////////////////////////////////////////////////////////////////////////////// 1035def SRI_N : WInst<"vsri_n", "dddi", "PlQPl">; 1036def SLI_N : WInst<"vsli_n", "dddi", "PlQPl">; 1037 1038// Right shift narrow high 1039def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "hmdi", 1040 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1041def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "hmdi", 1042 "HsHiHl", OP_NARROW_HI>; 1043def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "hmdi", 1044 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1045def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "hmdi", 1046 "HsHiHl", OP_NARROW_HI>; 1047def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "hmdi", 1048 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1049def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "hmdi", 1050 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 1051} 1052 1053//////////////////////////////////////////////////////////////////////////////// 1054// Converting vectors 1055def VMOVL_HIGH : SOpInst<"vmovl_high", "nd", "HcHsHiHUcHUsHUi", OP_MOVL_HI>; 1056 1057let isVCVT_N = 1 in { 1058def CVTF_N_F64 : SInst<"vcvt_n_f64", "Fdi", "lUlQlQUl">; 1059def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "xdi", "dQd">; 1060def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "udi", "dQd">; 1061} 1062 1063//////////////////////////////////////////////////////////////////////////////// 1064// 3VDiff class using high 64-bit in operands 1065def VADDL_HIGH : SOpInst<"vaddl_high", "wkk", "csiUcUsUi", OP_ADDLHi>; 1066def VADDW_HIGH : SOpInst<"vaddw_high", "wwk", "csiUcUsUi", OP_ADDWHi>; 1067def VSUBL_HIGH : SOpInst<"vsubl_high", "wkk", "csiUcUsUi", OP_SUBLHi>; 1068def VSUBW_HIGH : SOpInst<"vsubw_high", "wwk", "csiUcUsUi", OP_SUBWHi>; 1069 1070def VABDL_HIGH : SOpInst<"vabdl_high", "wkk", "csiUcUsUi", OP_ABDLHi>; 1071def VABAL_HIGH : SOpInst<"vabal_high", "wwkk", "csiUcUsUi", OP_ABALHi>; 1072 1073def VMULL_HIGH : SOpInst<"vmull_high", "wkk", "csiUcUsUiPc", OP_MULLHi>; 1074def VMULL_HIGH_N : SOpInst<"vmull_high_n", "wks", "siUsUi", OP_MULLHi_N>; 1075def VMLAL_HIGH : SOpInst<"vmlal_high", "wwkk", "csiUcUsUi", OP_MLALHi>; 1076def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "wwks", "siUsUi", OP_MLALHi_N>; 1077def VMLSL_HIGH : SOpInst<"vmlsl_high", "wwkk", "csiUcUsUi", OP_MLSLHi>; 1078def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "wwks", "siUsUi", OP_MLSLHi_N>; 1079 1080def VADDHN_HIGH : SOpInst<"vaddhn_high", "qhkk", "silUsUiUl", OP_ADDHNHi>; 1081def VRADDHN_HIGH : SOpInst<"vraddhn_high", "qhkk", "silUsUiUl", OP_RADDHNHi>; 1082def VSUBHN_HIGH : SOpInst<"vsubhn_high", "qhkk", "silUsUiUl", OP_SUBHNHi>; 1083def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "qhkk", "silUsUiUl", OP_RSUBHNHi>; 1084 1085def VQDMULL_HIGH : SOpInst<"vqdmull_high", "wkk", "si", OP_QDMULLHi>; 1086def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "wks", "si", OP_QDMULLHi_N>; 1087def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "wwkk", "si", OP_QDMLALHi>; 1088def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "wwks", "si", OP_QDMLALHi_N>; 1089def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "wwkk", "si", OP_QDMLSLHi>; 1090def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "wwks", "si", OP_QDMLSLHi_N>; 1091def VMULL_P64 : SInst<"vmull", "rss", "Pl">; 1092def VMULL_HIGH_P64 : SOpInst<"vmull_high", "rdd", "HPl", OP_MULLHi_P64>; 1093 1094 1095//////////////////////////////////////////////////////////////////////////////// 1096// Extract or insert element from vector 1097def GET_LANE : IInst<"vget_lane", "sdi", "dQdPlQPl">; 1098def SET_LANE : IInst<"vset_lane", "dsdi", "dQdPlQPl">; 1099def COPY_LANE : IOpInst<"vcopy_lane", "ddidi", 1100 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>; 1101def COPYQ_LANE : IOpInst<"vcopy_lane", "ddigi", 1102 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 1103def COPY_LANEQ : IOpInst<"vcopy_laneq", "ddiki", 1104 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>; 1105def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "ddidi", 1106 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 1107 1108//////////////////////////////////////////////////////////////////////////////// 1109// Set all lanes to same value 1110def VDUP_LANE1: WOpInst<"vdup_lane", "dgi", "hdQhQdPlQPl", OP_DUP_LN>; 1111def VDUP_LANE2: WOpInst<"vdup_laneq", "dji", 1112 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 1113 OP_DUP_LN>; 1114def DUP_N : WOpInst<"vdup_n", "ds", "dQdPlQPl", OP_DUP>; 1115def MOV_N : WOpInst<"vmov_n", "ds", "dQdPlQPl", OP_DUP>; 1116 1117//////////////////////////////////////////////////////////////////////////////// 1118def COMBINE : NoTestOpInst<"vcombine", "kdd", "dPl", OP_CONC>; 1119 1120//////////////////////////////////////////////////////////////////////////////// 1121//Initialize a vector from bit pattern 1122def CREATE : NoTestOpInst<"vcreate", "dl", "dPl", OP_CAST> { 1123 let BigEndianSafe = 1; 1124} 1125 1126//////////////////////////////////////////////////////////////////////////////// 1127 1128def VMLA_LANEQ : IOpInst<"vmla_laneq", "dddji", 1129 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 1130def VMLS_LANEQ : IOpInst<"vmls_laneq", "dddji", 1131 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 1132 1133def VFMA_LANE : IInst<"vfma_lane", "dddgi", "fdQfQd">; 1134def VFMA_LANEQ : IInst<"vfma_laneq", "dddji", "fdQfQd"> { 1135 let isLaneQ = 1; 1136} 1137def VFMS_LANE : IOpInst<"vfms_lane", "dddgi", "fdQfQd", OP_FMS_LN>; 1138def VFMS_LANEQ : IOpInst<"vfms_laneq", "dddji", "fdQfQd", OP_FMS_LNQ>; 1139 1140def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "wwdki", "siUsUi", OP_MLAL_LN>; 1141def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "wwkdi", "siUsUi", 1142 OP_MLALHi_LN>; 1143def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "wwkki", "siUsUi", 1144 OP_MLALHi_LN>; 1145def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "wwdki", "siUsUi", OP_MLSL_LN>; 1146def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "wwkdi", "siUsUi", 1147 OP_MLSLHi_LN>; 1148def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "wwkki", "siUsUi", 1149 OP_MLSLHi_LN>; 1150 1151def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "wwdki", "si", OP_QDMLAL_LN>; 1152def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "wwkdi", "si", 1153 OP_QDMLALHi_LN>; 1154def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "wwkki", "si", 1155 OP_QDMLALHi_LN>; 1156def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "wwdki", "si", OP_QDMLSL_LN>; 1157def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "wwkdi", "si", 1158 OP_QDMLSLHi_LN>; 1159def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "wwkki", "si", 1160 OP_QDMLSLHi_LN>; 1161 1162// Newly add double parameter for vmul_lane in aarch64 1163// Note: d type is handled by SCALAR_VMUL_LANE 1164def VMUL_LANE_A64 : IOpInst<"vmul_lane", "ddgi", "Qd", OP_MUL_LN>; 1165 1166// Note: d type is handled by SCALAR_VMUL_LANEQ 1167def VMUL_LANEQ : IOpInst<"vmul_laneq", "ddji", 1168 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>; 1169def VMULL_LANEQ : SOpInst<"vmull_laneq", "wdki", "siUsUi", OP_MULL_LN>; 1170def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "wkdi", "siUsUi", 1171 OP_MULLHi_LN>; 1172def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "wkki", "siUsUi", 1173 OP_MULLHi_LN>; 1174 1175def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "wdki", "si", OP_QDMULL_LN>; 1176def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "wkdi", "si", 1177 OP_QDMULLHi_LN>; 1178def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "wkki", "si", 1179 OP_QDMULLHi_LN>; 1180 1181def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ddji", "siQsQi", OP_QDMULH_LN>; 1182def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ddji", "siQsQi", OP_QRDMULH_LN>; 1183 1184let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1185def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "dddji", "siQsQi", OP_QRDMLAH_LN>; 1186def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "dddji", "siQsQi", OP_QRDMLSH_LN>; 1187} 1188 1189// Note: d type implemented by SCALAR_VMULX_LANE 1190def VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "fQfQd", OP_MULX_LN>; 1191// Note: d type is implemented by SCALAR_VMULX_LANEQ 1192def VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "fQfQd", OP_MULX_LN>; 1193 1194//////////////////////////////////////////////////////////////////////////////// 1195// Across vectors class 1196def VADDLV : SInst<"vaddlv", "rd", "csiUcUsUiQcQsQiQUcQUsQUi">; 1197def VMAXV : SInst<"vmaxv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 1198def VMINV : SInst<"vminv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 1199def VADDV : SInst<"vaddv", "sd", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">; 1200def FMAXNMV : SInst<"vmaxnmv", "sd", "fQfQd">; 1201def FMINNMV : SInst<"vminnmv", "sd", "fQfQd">; 1202 1203//////////////////////////////////////////////////////////////////////////////// 1204// Newly added Vector Extract for f64 1205def VEXT_A64 : WInst<"vext", "dddi", "dQdPlQPl">; 1206 1207//////////////////////////////////////////////////////////////////////////////// 1208// Crypto 1209let ArchGuard = "__ARM_FEATURE_CRYPTO" in { 1210def AESE : SInst<"vaese", "ddd", "QUc">; 1211def AESD : SInst<"vaesd", "ddd", "QUc">; 1212def AESMC : SInst<"vaesmc", "dd", "QUc">; 1213def AESIMC : SInst<"vaesimc", "dd", "QUc">; 1214 1215def SHA1H : SInst<"vsha1h", "ss", "Ui">; 1216def SHA1SU1 : SInst<"vsha1su1", "ddd", "QUi">; 1217def SHA256SU0 : SInst<"vsha256su0", "ddd", "QUi">; 1218 1219def SHA1C : SInst<"vsha1c", "ddsd", "QUi">; 1220def SHA1P : SInst<"vsha1p", "ddsd", "QUi">; 1221def SHA1M : SInst<"vsha1m", "ddsd", "QUi">; 1222def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">; 1223def SHA256H : SInst<"vsha256h", "dddd", "QUi">; 1224def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">; 1225def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">; 1226} 1227 1228//////////////////////////////////////////////////////////////////////////////// 1229// Float -> Int conversions with explicit rounding mode 1230 1231let ArchGuard = "__ARM_ARCH >= 8" in { 1232def FCVTNS_S32 : SInst<"vcvtn_s32", "xd", "fQf">; 1233def FCVTNU_S32 : SInst<"vcvtn_u32", "ud", "fQf">; 1234def FCVTPS_S32 : SInst<"vcvtp_s32", "xd", "fQf">; 1235def FCVTPU_S32 : SInst<"vcvtp_u32", "ud", "fQf">; 1236def FCVTMS_S32 : SInst<"vcvtm_s32", "xd", "fQf">; 1237def FCVTMU_S32 : SInst<"vcvtm_u32", "ud", "fQf">; 1238def FCVTAS_S32 : SInst<"vcvta_s32", "xd", "fQf">; 1239def FCVTAU_S32 : SInst<"vcvta_u32", "ud", "fQf">; 1240} 1241 1242let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in { 1243def FCVTNS_S64 : SInst<"vcvtn_s64", "xd", "dQd">; 1244def FCVTNU_S64 : SInst<"vcvtn_u64", "ud", "dQd">; 1245def FCVTPS_S64 : SInst<"vcvtp_s64", "xd", "dQd">; 1246def FCVTPU_S64 : SInst<"vcvtp_u64", "ud", "dQd">; 1247def FCVTMS_S64 : SInst<"vcvtm_s64", "xd", "dQd">; 1248def FCVTMU_S64 : SInst<"vcvtm_u64", "ud", "dQd">; 1249def FCVTAS_S64 : SInst<"vcvta_s64", "xd", "dQd">; 1250def FCVTAU_S64 : SInst<"vcvta_u64", "ud", "dQd">; 1251} 1252 1253//////////////////////////////////////////////////////////////////////////////// 1254// Round to Integral 1255 1256let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1257def FRINTN_S32 : SInst<"vrndn", "dd", "fQf">; 1258def FRINTA_S32 : SInst<"vrnda", "dd", "fQf">; 1259def FRINTP_S32 : SInst<"vrndp", "dd", "fQf">; 1260def FRINTM_S32 : SInst<"vrndm", "dd", "fQf">; 1261def FRINTX_S32 : SInst<"vrndx", "dd", "fQf">; 1262def FRINTZ_S32 : SInst<"vrnd", "dd", "fQf">; 1263} 1264 1265let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1266def FRINTN_S64 : SInst<"vrndn", "dd", "dQd">; 1267def FRINTA_S64 : SInst<"vrnda", "dd", "dQd">; 1268def FRINTP_S64 : SInst<"vrndp", "dd", "dQd">; 1269def FRINTM_S64 : SInst<"vrndm", "dd", "dQd">; 1270def FRINTX_S64 : SInst<"vrndx", "dd", "dQd">; 1271def FRINTZ_S64 : SInst<"vrnd", "dd", "dQd">; 1272def FRINTI_S64 : SInst<"vrndi", "dd", "fdQfQd">; 1273} 1274 1275//////////////////////////////////////////////////////////////////////////////// 1276// MaxNum/MinNum Floating Point 1277 1278let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in { 1279def FMAXNM_S32 : SInst<"vmaxnm", "ddd", "fQf">; 1280def FMINNM_S32 : SInst<"vminnm", "ddd", "fQf">; 1281} 1282 1283let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in { 1284def FMAXNM_S64 : SInst<"vmaxnm", "ddd", "dQd">; 1285def FMINNM_S64 : SInst<"vminnm", "ddd", "dQd">; 1286} 1287 1288//////////////////////////////////////////////////////////////////////////////// 1289// Permutation 1290def VTRN1 : SOpInst<"vtrn1", "ddd", 1291 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>; 1292def VZIP1 : SOpInst<"vzip1", "ddd", 1293 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>; 1294def VUZP1 : SOpInst<"vuzp1", "ddd", 1295 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>; 1296def VTRN2 : SOpInst<"vtrn2", "ddd", 1297 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>; 1298def VZIP2 : SOpInst<"vzip2", "ddd", 1299 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>; 1300def VUZP2 : SOpInst<"vuzp2", "ddd", 1301 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>; 1302 1303//////////////////////////////////////////////////////////////////////////////// 1304// Table lookup 1305let InstName = "vtbl" in { 1306def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">; 1307def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">; 1308def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">; 1309def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">; 1310} 1311let InstName = "vtbx" in { 1312def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">; 1313def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">; 1314def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">; 1315def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">; 1316} 1317 1318//////////////////////////////////////////////////////////////////////////////// 1319// Vector reinterpret cast operations 1320 1321// NeonEmitter implicitly takes the cartesian product of the type string with 1322// itself during generation so, unlike all other intrinsics, this one should 1323// include *all* types, not just additional ones. 1324def VVREINTERPRET 1325 : NoTestOpInst<"vreinterpret", "dd", 1326 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", OP_REINT> { 1327 let CartesianProductOfTypes = 1; 1328 let BigEndianSafe = 1; 1329 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)"; 1330} 1331 1332//////////////////////////////////////////////////////////////////////////////// 1333// Scalar Intrinsics 1334// Scalar Arithmetic 1335 1336// Scalar Addition 1337def SCALAR_ADD : SInst<"vadd", "sss", "SlSUl">; 1338// Scalar Saturating Add 1339def SCALAR_QADD : SInst<"vqadd", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1340 1341// Scalar Subtraction 1342def SCALAR_SUB : SInst<"vsub", "sss", "SlSUl">; 1343// Scalar Saturating Sub 1344def SCALAR_QSUB : SInst<"vqsub", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1345 1346let InstName = "vmov" in { 1347def VGET_HIGH_A64 : NoTestOpInst<"vget_high", "dk", "dPl", OP_HI>; 1348def VGET_LOW_A64 : NoTestOpInst<"vget_low", "dk", "dPl", OP_LO>; 1349} 1350 1351//////////////////////////////////////////////////////////////////////////////// 1352// Scalar Shift 1353// Scalar Shift Left 1354def SCALAR_SHL: SInst<"vshl", "sss", "SlSUl">; 1355// Scalar Saturating Shift Left 1356def SCALAR_QSHL: SInst<"vqshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1357// Scalar Saturating Rounding Shift Left 1358def SCALAR_QRSHL: SInst<"vqrshl", "sss", "ScSsSiSlSUcSUsSUiSUl">; 1359// Scalar Shift Rouding Left 1360def SCALAR_RSHL: SInst<"vrshl", "sss", "SlSUl">; 1361 1362//////////////////////////////////////////////////////////////////////////////// 1363// Scalar Shift (Immediate) 1364let isScalarShift = 1 in { 1365// Signed/Unsigned Shift Right (Immediate) 1366def SCALAR_SSHR_N: SInst<"vshr_n", "ssi", "SlSUl">; 1367// Signed/Unsigned Rounding Shift Right (Immediate) 1368def SCALAR_SRSHR_N: SInst<"vrshr_n", "ssi", "SlSUl">; 1369 1370// Signed/Unsigned Shift Right and Accumulate (Immediate) 1371def SCALAR_SSRA_N: SInst<"vsra_n", "sssi", "SlSUl">; 1372// Signed/Unsigned Rounding Shift Right and Accumulate (Immediate) 1373def SCALAR_SRSRA_N: SInst<"vrsra_n", "sssi", "SlSUl">; 1374 1375// Shift Left (Immediate) 1376def SCALAR_SHL_N: SInst<"vshl_n", "ssi", "SlSUl">; 1377// Signed/Unsigned Saturating Shift Left (Immediate) 1378def SCALAR_SQSHL_N: SInst<"vqshl_n", "ssi", "ScSsSiSlSUcSUsSUiSUl">; 1379// Signed Saturating Shift Left Unsigned (Immediate) 1380def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "ssi", "ScSsSiSl">; 1381 1382// Shift Right And Insert (Immediate) 1383def SCALAR_SRI_N: SInst<"vsri_n", "sssi", "SlSUl">; 1384// Shift Left And Insert (Immediate) 1385def SCALAR_SLI_N: SInst<"vsli_n", "sssi", "SlSUl">; 1386 1387let isScalarNarrowShift = 1 in { 1388 // Signed/Unsigned Saturating Shift Right Narrow (Immediate) 1389 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1390 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) 1391 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "zsi", "SsSiSlSUsSUiSUl">; 1392 // Signed Saturating Shift Right Unsigned Narrow (Immediate) 1393 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "zsi", "SsSiSl">; 1394 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) 1395 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "zsi", "SsSiSl">; 1396} 1397 1398//////////////////////////////////////////////////////////////////////////////// 1399// Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) 1400def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "ysi", "SiSUi">; 1401def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "osi", "SlSUl">; 1402 1403//////////////////////////////////////////////////////////////////////////////// 1404// Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) 1405def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "$si", "Sf">; 1406def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "bsi", "Sf">; 1407def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "$si", "Sd">; 1408def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "bsi", "Sd">; 1409} 1410 1411//////////////////////////////////////////////////////////////////////////////// 1412// Scalar Reduce Pairwise Addition (Scalar and Floating Point) 1413def SCALAR_ADDP : SInst<"vpadd", "sd", "SfSHlSHdSHUl">; 1414 1415//////////////////////////////////////////////////////////////////////////////// 1416// Scalar Reduce Floating Point Pairwise Max/Min 1417def SCALAR_FMAXP : SInst<"vpmax", "sd", "SfSQd">; 1418 1419def SCALAR_FMINP : SInst<"vpmin", "sd", "SfSQd">; 1420 1421//////////////////////////////////////////////////////////////////////////////// 1422// Scalar Reduce Floating Point Pairwise maxNum/minNum 1423def SCALAR_FMAXNMP : SInst<"vpmaxnm", "sd", "SfSQd">; 1424def SCALAR_FMINNMP : SInst<"vpminnm", "sd", "SfSQd">; 1425 1426//////////////////////////////////////////////////////////////////////////////// 1427// Scalar Integer Saturating Doubling Multiply Half High 1428def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">; 1429 1430//////////////////////////////////////////////////////////////////////////////// 1431// Scalar Integer Saturating Rounding Doubling Multiply Half High 1432def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">; 1433 1434let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1435//////////////////////////////////////////////////////////////////////////////// 1436// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half 1437def SCALAR_SQRDMLAH : SOpInst<"vqrdmlah", "ssss", "SsSi", OP_QRDMLAH>; 1438 1439//////////////////////////////////////////////////////////////////////////////// 1440// Signed Saturating Rounding Doubling Multiply Subtract Returning High Half 1441def SCALAR_SQRDMLSH : SOpInst<"vqrdmlsh", "ssss", "SsSi", OP_QRDMLSH>; 1442} 1443 1444//////////////////////////////////////////////////////////////////////////////// 1445// Scalar Floating-point Multiply Extended 1446def SCALAR_FMULX : IInst<"vmulx", "sss", "SfSd">; 1447 1448//////////////////////////////////////////////////////////////////////////////// 1449// Scalar Floating-point Reciprocal Step 1450def SCALAR_FRECPS : IInst<"vrecps", "sss", "SfSd">; 1451 1452//////////////////////////////////////////////////////////////////////////////// 1453// Scalar Floating-point Reciprocal Square Root Step 1454def SCALAR_FRSQRTS : IInst<"vrsqrts", "sss", "SfSd">; 1455 1456//////////////////////////////////////////////////////////////////////////////// 1457// Scalar Signed Integer Convert To Floating-point 1458def SCALAR_SCVTFS : SInst<"vcvt_f32", "ys", "Si">; 1459def SCALAR_SCVTFD : SInst<"vcvt_f64", "os", "Sl">; 1460 1461//////////////////////////////////////////////////////////////////////////////// 1462// Scalar Unsigned Integer Convert To Floating-point 1463def SCALAR_UCVTFS : SInst<"vcvt_f32", "ys", "SUi">; 1464def SCALAR_UCVTFD : SInst<"vcvt_f64", "os", "SUl">; 1465 1466//////////////////////////////////////////////////////////////////////////////// 1467// Scalar Floating-point Converts 1468def SCALAR_FCVTXN : IInst<"vcvtx_f32", "ys", "Sd">; 1469def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "$s", "Sf">; 1470def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "bs", "Sf">; 1471def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "$s", "Sd">; 1472def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "bs", "Sd">; 1473def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "$s", "Sf">; 1474def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "bs", "Sf">; 1475def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "$s", "Sd">; 1476def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "bs", "Sd">; 1477def SCALAR_FCVTASS : SInst<"vcvta_s32", "$s", "Sf">; 1478def SCALAR_FCVTAUS : SInst<"vcvta_u32", "bs", "Sf">; 1479def SCALAR_FCVTASD : SInst<"vcvta_s64", "$s", "Sd">; 1480def SCALAR_FCVTAUD : SInst<"vcvta_u64", "bs", "Sd">; 1481def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "$s", "Sf">; 1482def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "bs", "Sf">; 1483def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "$s", "Sd">; 1484def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "bs", "Sd">; 1485def SCALAR_FCVTZSS : SInst<"vcvt_s32", "$s", "Sf">; 1486def SCALAR_FCVTZUS : SInst<"vcvt_u32", "bs", "Sf">; 1487def SCALAR_FCVTZSD : SInst<"vcvt_s64", "$s", "Sd">; 1488def SCALAR_FCVTZUD : SInst<"vcvt_u64", "bs", "Sd">; 1489 1490//////////////////////////////////////////////////////////////////////////////// 1491// Scalar Floating-point Reciprocal Estimate 1492def SCALAR_FRECPE : IInst<"vrecpe", "ss", "SfSd">; 1493 1494//////////////////////////////////////////////////////////////////////////////// 1495// Scalar Floating-point Reciprocal Exponent 1496def SCALAR_FRECPX : IInst<"vrecpx", "ss", "SfSd">; 1497 1498//////////////////////////////////////////////////////////////////////////////// 1499// Scalar Floating-point Reciprocal Square Root Estimate 1500def SCALAR_FRSQRTE : IInst<"vrsqrte", "ss", "SfSd">; 1501 1502//////////////////////////////////////////////////////////////////////////////// 1503// Scalar Integer Comparison 1504def SCALAR_CMEQ : SInst<"vceq", "sss", "SlSUl">; 1505def SCALAR_CMEQZ : SInst<"vceqz", "ss", "SlSUl">; 1506def SCALAR_CMGE : SInst<"vcge", "sss", "Sl">; 1507def SCALAR_CMGEZ : SInst<"vcgez", "ss", "Sl">; 1508def SCALAR_CMHS : SInst<"vcge", "sss", "SUl">; 1509def SCALAR_CMLE : SInst<"vcle", "sss", "SlSUl">; 1510def SCALAR_CMLEZ : SInst<"vclez", "ss", "Sl">; 1511def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">; 1512def SCALAR_CMLTZ : SInst<"vcltz", "ss", "Sl">; 1513def SCALAR_CMGT : SInst<"vcgt", "sss", "Sl">; 1514def SCALAR_CMGTZ : SInst<"vcgtz", "ss", "Sl">; 1515def SCALAR_CMHI : SInst<"vcgt", "sss", "SUl">; 1516def SCALAR_CMTST : SInst<"vtst", "sss", "SlSUl">; 1517 1518//////////////////////////////////////////////////////////////////////////////// 1519// Scalar Floating-point Comparison 1520def SCALAR_FCMEQ : IInst<"vceq", "bss", "SfSd">; 1521def SCALAR_FCMEQZ : IInst<"vceqz", "bs", "SfSd">; 1522def SCALAR_FCMGE : IInst<"vcge", "bss", "SfSd">; 1523def SCALAR_FCMGEZ : IInst<"vcgez", "bs", "SfSd">; 1524def SCALAR_FCMGT : IInst<"vcgt", "bss", "SfSd">; 1525def SCALAR_FCMGTZ : IInst<"vcgtz", "bs", "SfSd">; 1526def SCALAR_FCMLE : IInst<"vcle", "bss", "SfSd">; 1527def SCALAR_FCMLEZ : IInst<"vclez", "bs", "SfSd">; 1528def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">; 1529def SCALAR_FCMLTZ : IInst<"vcltz", "bs", "SfSd">; 1530 1531//////////////////////////////////////////////////////////////////////////////// 1532// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal 1533def SCALAR_FACGE : IInst<"vcage", "bss", "SfSd">; 1534def SCALAR_FACLE : IInst<"vcale", "bss", "SfSd">; 1535 1536//////////////////////////////////////////////////////////////////////////////// 1537// Scalar Floating-point Absolute Compare Mask Greater Than 1538def SCALAR_FACGT : IInst<"vcagt", "bss", "SfSd">; 1539def SCALAR_FACLT : IInst<"vcalt", "bss", "SfSd">; 1540 1541//////////////////////////////////////////////////////////////////////////////// 1542// Scalar Absolute Value 1543def SCALAR_ABS : SInst<"vabs", "ss", "Sl">; 1544 1545//////////////////////////////////////////////////////////////////////////////// 1546// Scalar Absolute Difference 1547def SCALAR_ABD : IInst<"vabd", "sss", "SfSd">; 1548 1549//////////////////////////////////////////////////////////////////////////////// 1550// Scalar Signed Saturating Absolute Value 1551def SCALAR_SQABS : SInst<"vqabs", "ss", "ScSsSiSl">; 1552 1553//////////////////////////////////////////////////////////////////////////////// 1554// Scalar Negate 1555def SCALAR_NEG : SInst<"vneg", "ss", "Sl">; 1556 1557//////////////////////////////////////////////////////////////////////////////// 1558// Scalar Signed Saturating Negate 1559def SCALAR_SQNEG : SInst<"vqneg", "ss", "ScSsSiSl">; 1560 1561//////////////////////////////////////////////////////////////////////////////// 1562// Scalar Signed Saturating Accumulated of Unsigned Value 1563def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">; 1564 1565//////////////////////////////////////////////////////////////////////////////// 1566// Scalar Unsigned Saturating Accumulated of Signed Value 1567def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">; 1568 1569//////////////////////////////////////////////////////////////////////////////// 1570// Signed Saturating Doubling Multiply-Add Long 1571def SCALAR_SQDMLAL : SInst<"vqdmlal", "rrss", "SsSi">; 1572 1573//////////////////////////////////////////////////////////////////////////////// 1574// Signed Saturating Doubling Multiply-Subtract Long 1575def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">; 1576 1577//////////////////////////////////////////////////////////////////////////////// 1578// Signed Saturating Doubling Multiply Long 1579def SCALAR_SQDMULL : SInst<"vqdmull", "rss", "SsSi">; 1580 1581//////////////////////////////////////////////////////////////////////////////// 1582// Scalar Signed Saturating Extract Unsigned Narrow 1583def SCALAR_SQXTUN : SInst<"vqmovun", "zs", "SsSiSl">; 1584 1585//////////////////////////////////////////////////////////////////////////////// 1586// Scalar Signed Saturating Extract Narrow 1587def SCALAR_SQXTN : SInst<"vqmovn", "zs", "SsSiSl">; 1588 1589//////////////////////////////////////////////////////////////////////////////// 1590// Scalar Unsigned Saturating Extract Narrow 1591def SCALAR_UQXTN : SInst<"vqmovn", "zs", "SUsSUiSUl">; 1592 1593// Scalar Floating Point multiply (scalar, by element) 1594def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "ssdi", "SfSd", OP_SCALAR_MUL_LN>; 1595def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "ssji", "SfSd", OP_SCALAR_MUL_LN>; 1596 1597// Scalar Floating Point multiply extended (scalar, by element) 1598def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "ssdi", "SfSd", OP_SCALAR_MULX_LN>; 1599def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "ssji", "SfSd", OP_SCALAR_MULX_LN>; 1600 1601def SCALAR_VMUL_N : IInst<"vmul_n", "dds", "d">; 1602 1603// VMUL_LANE_A64 d type implemented using scalar mul lane 1604def SCALAR_VMUL_LANE : IInst<"vmul_lane", "ddgi", "d">; 1605 1606// VMUL_LANEQ d type implemented using scalar mul lane 1607def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "ddji", "d"> { 1608 let isLaneQ = 1; 1609} 1610 1611// VMULX_LANE d type implemented using scalar vmulx_lane 1612def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "ddgi", "d", OP_SCALAR_VMULX_LN>; 1613 1614// VMULX_LANEQ d type implemented using scalar vmulx_laneq 1615def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "ddji", "d", OP_SCALAR_VMULX_LNQ>; 1616 1617// Scalar Floating Point fused multiply-add (scalar, by element) 1618def SCALAR_FMLA_LANE : IInst<"vfma_lane", "sssdi", "SfSd">; 1619def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "sssji", "SfSd">; 1620 1621// Scalar Floating Point fused multiply-subtract (scalar, by element) 1622def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "sssdi", "SfSd", OP_FMS_LN>; 1623def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "sssji", "SfSd", OP_FMS_LNQ>; 1624 1625// Signed Saturating Doubling Multiply Long (scalar by element) 1626def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "rsdi", "SsSi", OP_SCALAR_QDMULL_LN>; 1627def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "rsji", "SsSi", OP_SCALAR_QDMULL_LN>; 1628 1629// Signed Saturating Doubling Multiply-Add Long (scalar by element) 1630def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "rrsdi", "SsSi">; 1631def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "rrsji", "SsSi">; 1632 1633// Signed Saturating Doubling Multiply-Subtract Long (scalar by element) 1634def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "rrsdi", "SsSi">; 1635def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "rrsji", "SsSi">; 1636 1637// Scalar Integer Saturating Doubling Multiply Half High (scalar by element) 1638def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QDMULH_LN>; 1639def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QDMULH_LN>; 1640 1641// Scalar Integer Saturating Rounding Doubling Multiply Half High 1642def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "ssdi", "SsSi", OP_SCALAR_QRDMULH_LN>; 1643def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "ssji", "SsSi", OP_SCALAR_QRDMULH_LN>; 1644 1645let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1646// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half 1647def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "sssdi", "SsSi", OP_SCALAR_QRDMLAH_LN>; 1648def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "sssji", "SsSi", OP_SCALAR_QRDMLAH_LN>; 1649 1650// Signed Saturating Rounding Doubling Multiply Subtract Returning High Half 1651def SCALAR_SQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "sssdi", "SsSi", OP_SCALAR_QRDMLSH_LN>; 1652def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "sssji", "SsSi", OP_SCALAR_QRDMLSH_LN>; 1653} 1654 1655def SCALAR_VDUP_LANE : IInst<"vdup_lane", "sdi", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1656def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "sji", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1657} 1658