1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Hexagon uses to lower LLVM code
11 // into a selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "HexagonISelLowering.h"
16 #include "HexagonMachineFunctionInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/GlobalAlias.h"
32 #include "llvm/IR/GlobalVariable.h"
33 #include "llvm/IR/InlineAsm.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39
40 using namespace llvm;
41
42 #define DEBUG_TYPE "hexagon-lowering"
43
44 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
45 cl::init(true), cl::Hidden,
46 cl::desc("Control jump table emission on Hexagon target"));
47
48 static cl::opt<bool> EnableHexSDNodeSched("enable-hexagon-sdnode-sched",
49 cl::Hidden, cl::ZeroOrMore, cl::init(false),
50 cl::desc("Enable Hexagon SDNode scheduling"));
51
52 static cl::opt<bool> EnableFastMath("ffast-math",
53 cl::Hidden, cl::ZeroOrMore, cl::init(false),
54 cl::desc("Enable Fast Math processing"));
55
56 static cl::opt<int> MinimumJumpTables("minimum-jump-tables",
57 cl::Hidden, cl::ZeroOrMore, cl::init(5),
58 cl::desc("Set minimum jump tables"));
59
60 static cl::opt<int> MaxStoresPerMemcpyCL("max-store-memcpy",
61 cl::Hidden, cl::ZeroOrMore, cl::init(6),
62 cl::desc("Max #stores to inline memcpy"));
63
64 static cl::opt<int> MaxStoresPerMemcpyOptSizeCL("max-store-memcpy-Os",
65 cl::Hidden, cl::ZeroOrMore, cl::init(4),
66 cl::desc("Max #stores to inline memcpy"));
67
68 static cl::opt<int> MaxStoresPerMemmoveCL("max-store-memmove",
69 cl::Hidden, cl::ZeroOrMore, cl::init(6),
70 cl::desc("Max #stores to inline memmove"));
71
72 static cl::opt<int> MaxStoresPerMemmoveOptSizeCL("max-store-memmove-Os",
73 cl::Hidden, cl::ZeroOrMore, cl::init(4),
74 cl::desc("Max #stores to inline memmove"));
75
76 static cl::opt<int> MaxStoresPerMemsetCL("max-store-memset",
77 cl::Hidden, cl::ZeroOrMore, cl::init(8),
78 cl::desc("Max #stores to inline memset"));
79
80 static cl::opt<int> MaxStoresPerMemsetOptSizeCL("max-store-memset-Os",
81 cl::Hidden, cl::ZeroOrMore, cl::init(4),
82 cl::desc("Max #stores to inline memset"));
83
84
85 namespace {
86 class HexagonCCState : public CCState {
87 unsigned NumNamedVarArgParams;
88
89 public:
HexagonCCState(CallingConv::ID CC,bool isVarArg,MachineFunction & MF,SmallVectorImpl<CCValAssign> & locs,LLVMContext & C,int NumNamedVarArgParams)90 HexagonCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
91 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
92 int NumNamedVarArgParams)
93 : CCState(CC, isVarArg, MF, locs, C),
94 NumNamedVarArgParams(NumNamedVarArgParams) {}
95
getNumNamedVarArgParams() const96 unsigned getNumNamedVarArgParams() const { return NumNamedVarArgParams; }
97 };
98 }
99
100 // Implement calling convention for Hexagon.
101
102 static bool IsHvxVectorType(MVT ty);
103
104 static bool
105 CC_Hexagon(unsigned ValNo, MVT ValVT,
106 MVT LocVT, CCValAssign::LocInfo LocInfo,
107 ISD::ArgFlagsTy ArgFlags, CCState &State);
108
109 static bool
110 CC_Hexagon32(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
112 ISD::ArgFlagsTy ArgFlags, CCState &State);
113
114 static bool
115 CC_Hexagon64(unsigned ValNo, MVT ValVT,
116 MVT LocVT, CCValAssign::LocInfo LocInfo,
117 ISD::ArgFlagsTy ArgFlags, CCState &State);
118
119 static bool
120 CC_HexagonVector(unsigned ValNo, MVT ValVT,
121 MVT LocVT, CCValAssign::LocInfo LocInfo,
122 ISD::ArgFlagsTy ArgFlags, CCState &State);
123
124 static bool
125 RetCC_Hexagon(unsigned ValNo, MVT ValVT,
126 MVT LocVT, CCValAssign::LocInfo LocInfo,
127 ISD::ArgFlagsTy ArgFlags, CCState &State);
128
129 static bool
130 RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
131 MVT LocVT, CCValAssign::LocInfo LocInfo,
132 ISD::ArgFlagsTy ArgFlags, CCState &State);
133
134 static bool
135 RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
136 MVT LocVT, CCValAssign::LocInfo LocInfo,
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
138
139 static bool
140 RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
141 MVT LocVT, CCValAssign::LocInfo LocInfo,
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
143
144 static bool
CC_Hexagon_VarArg(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)145 CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT,
146 MVT LocVT, CCValAssign::LocInfo LocInfo,
147 ISD::ArgFlagsTy ArgFlags, CCState &State) {
148 HexagonCCState &HState = static_cast<HexagonCCState &>(State);
149
150 if (ValNo < HState.getNumNamedVarArgParams()) {
151 // Deal with named arguments.
152 return CC_Hexagon(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State);
153 }
154
155 // Deal with un-named arguments.
156 unsigned ofst;
157 if (ArgFlags.isByVal()) {
158 // If pass-by-value, the size allocated on stack is decided
159 // by ArgFlags.getByValSize(), not by the size of LocVT.
160 ofst = State.AllocateStack(ArgFlags.getByValSize(),
161 ArgFlags.getByValAlign());
162 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
163 return false;
164 }
165 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
166 LocVT = MVT::i32;
167 ValVT = MVT::i32;
168 if (ArgFlags.isSExt())
169 LocInfo = CCValAssign::SExt;
170 else if (ArgFlags.isZExt())
171 LocInfo = CCValAssign::ZExt;
172 else
173 LocInfo = CCValAssign::AExt;
174 }
175 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
176 ofst = State.AllocateStack(4, 4);
177 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
178 return false;
179 }
180 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
181 ofst = State.AllocateStack(8, 8);
182 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
183 return false;
184 }
185 if (LocVT == MVT::v2i64 || LocVT == MVT::v4i32 || LocVT == MVT::v8i16 ||
186 LocVT == MVT::v16i8) {
187 ofst = State.AllocateStack(16, 16);
188 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
189 return false;
190 }
191 if (LocVT == MVT::v4i64 || LocVT == MVT::v8i32 || LocVT == MVT::v16i16 ||
192 LocVT == MVT::v32i8) {
193 ofst = State.AllocateStack(32, 32);
194 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
195 return false;
196 }
197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
198 LocVT == MVT::v64i8 || LocVT == MVT::v512i1) {
199 ofst = State.AllocateStack(64, 64);
200 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
201 return false;
202 }
203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
204 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1) {
205 ofst = State.AllocateStack(128, 128);
206 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
207 return false;
208 }
209 if (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
210 LocVT == MVT::v256i8) {
211 ofst = State.AllocateStack(256, 256);
212 State.addLoc(CCValAssign::getMem(ValNo, ValVT, ofst, LocVT, LocInfo));
213 return false;
214 }
215
216 llvm_unreachable(nullptr);
217 }
218
219
CC_Hexagon(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)220 static bool CC_Hexagon (unsigned ValNo, MVT ValVT, MVT LocVT,
221 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
222 if (ArgFlags.isByVal()) {
223 // Passed on stack.
224 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(),
225 ArgFlags.getByValAlign());
226 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
227 return false;
228 }
229
230 if (LocVT == MVT::i1 || LocVT == MVT::i8 || LocVT == MVT::i16) {
231 LocVT = MVT::i32;
232 ValVT = MVT::i32;
233 if (ArgFlags.isSExt())
234 LocInfo = CCValAssign::SExt;
235 else if (ArgFlags.isZExt())
236 LocInfo = CCValAssign::ZExt;
237 else
238 LocInfo = CCValAssign::AExt;
239 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
240 LocVT = MVT::i32;
241 LocInfo = CCValAssign::BCvt;
242 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
243 LocVT = MVT::i64;
244 LocInfo = CCValAssign::BCvt;
245 }
246
247 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
248 if (!CC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
249 return false;
250 }
251
252 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
253 if (!CC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
254 return false;
255 }
256
257 if (LocVT == MVT::v8i32 || LocVT == MVT::v16i16 || LocVT == MVT::v32i8) {
258 unsigned Offset = State.AllocateStack(ArgFlags.getByValSize(), 32);
259 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
260 return false;
261 }
262
263 if (IsHvxVectorType(LocVT)) {
264 if (!CC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
265 return false;
266 }
267
268 return true; // CC didn't match.
269 }
270
271
CC_Hexagon32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)272 static bool CC_Hexagon32(unsigned ValNo, MVT ValVT,
273 MVT LocVT, CCValAssign::LocInfo LocInfo,
274 ISD::ArgFlagsTy ArgFlags, CCState &State) {
275
276 static const MCPhysReg RegList[] = {
277 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
278 Hexagon::R5
279 };
280 if (unsigned Reg = State.AllocateReg(RegList)) {
281 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
282 return false;
283 }
284
285 unsigned Offset = State.AllocateStack(4, 4);
286 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
287 return false;
288 }
289
CC_Hexagon64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)290 static bool CC_Hexagon64(unsigned ValNo, MVT ValVT,
291 MVT LocVT, CCValAssign::LocInfo LocInfo,
292 ISD::ArgFlagsTy ArgFlags, CCState &State) {
293
294 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
295 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
296 return false;
297 }
298
299 static const MCPhysReg RegList1[] = {
300 Hexagon::D1, Hexagon::D2
301 };
302 static const MCPhysReg RegList2[] = {
303 Hexagon::R1, Hexagon::R3
304 };
305 if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) {
306 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
307 return false;
308 }
309
310 unsigned Offset = State.AllocateStack(8, 8, Hexagon::D2);
311 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
312 return false;
313 }
314
CC_HexagonVector(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)315 static bool CC_HexagonVector(unsigned ValNo, MVT ValVT,
316 MVT LocVT, CCValAssign::LocInfo LocInfo,
317 ISD::ArgFlagsTy ArgFlags, CCState &State) {
318
319 static const MCPhysReg VecLstS[] = { Hexagon::V0, Hexagon::V1,
320 Hexagon::V2, Hexagon::V3,
321 Hexagon::V4, Hexagon::V5,
322 Hexagon::V6, Hexagon::V7,
323 Hexagon::V8, Hexagon::V9,
324 Hexagon::V10, Hexagon::V11,
325 Hexagon::V12, Hexagon::V13,
326 Hexagon::V14, Hexagon::V15};
327 static const MCPhysReg VecLstD[] = { Hexagon::W0, Hexagon::W1,
328 Hexagon::W2, Hexagon::W3,
329 Hexagon::W4, Hexagon::W5,
330 Hexagon::W6, Hexagon::W7};
331 auto &MF = State.getMachineFunction();
332 auto &HST = MF.getSubtarget<HexagonSubtarget>();
333 bool UseHVX = HST.useHVXOps();
334 bool UseHVXDbl = HST.useHVXDblOps();
335
336 if ((UseHVX && !UseHVXDbl) &&
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
338 LocVT == MVT::v64i8 || LocVT == MVT::v512i1)) {
339 if (unsigned Reg = State.AllocateReg(VecLstS)) {
340 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
341 return false;
342 }
343 unsigned Offset = State.AllocateStack(64, 64);
344 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
345 return false;
346 }
347 if ((UseHVX && !UseHVXDbl) &&
348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
349 LocVT == MVT::v128i8)) {
350 if (unsigned Reg = State.AllocateReg(VecLstD)) {
351 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
352 return false;
353 }
354 unsigned Offset = State.AllocateStack(128, 128);
355 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
356 return false;
357 }
358 // 128B Mode
359 if ((UseHVX && UseHVXDbl) &&
360 (LocVT == MVT::v32i64 || LocVT == MVT::v64i32 || LocVT == MVT::v128i16 ||
361 LocVT == MVT::v256i8)) {
362 if (unsigned Reg = State.AllocateReg(VecLstD)) {
363 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
364 return false;
365 }
366 unsigned Offset = State.AllocateStack(256, 256);
367 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
368 return false;
369 }
370 if ((UseHVX && UseHVXDbl) &&
371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 ||
372 LocVT == MVT::v128i8 || LocVT == MVT::v1024i1)) {
373 if (unsigned Reg = State.AllocateReg(VecLstS)) {
374 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
375 return false;
376 }
377 unsigned Offset = State.AllocateStack(128, 128);
378 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
379 return false;
380 }
381 return true;
382 }
383
RetCC_Hexagon(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)384 static bool RetCC_Hexagon(unsigned ValNo, MVT ValVT,
385 MVT LocVT, CCValAssign::LocInfo LocInfo,
386 ISD::ArgFlagsTy ArgFlags, CCState &State) {
387 auto &MF = State.getMachineFunction();
388 auto &HST = MF.getSubtarget<HexagonSubtarget>();
389 bool UseHVX = HST.useHVXOps();
390 bool UseHVXDbl = HST.useHVXDblOps();
391
392 if (LocVT == MVT::i1 ||
393 LocVT == MVT::i8 ||
394 LocVT == MVT::i16) {
395 LocVT = MVT::i32;
396 ValVT = MVT::i32;
397 if (ArgFlags.isSExt())
398 LocInfo = CCValAssign::SExt;
399 else if (ArgFlags.isZExt())
400 LocInfo = CCValAssign::ZExt;
401 else
402 LocInfo = CCValAssign::AExt;
403 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) {
404 LocVT = MVT::i32;
405 LocInfo = CCValAssign::BCvt;
406 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
407 LocVT = MVT::i64;
408 LocInfo = CCValAssign::BCvt;
409 } else if (LocVT == MVT::v64i8 || LocVT == MVT::v32i16 ||
410 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
411 LocVT == MVT::v512i1) {
412 LocVT = MVT::v16i32;
413 ValVT = MVT::v16i32;
414 LocInfo = CCValAssign::Full;
415 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 ||
416 LocVT == MVT::v32i32 || LocVT == MVT::v16i64 ||
417 (LocVT == MVT::v1024i1 && UseHVX && UseHVXDbl)) {
418 LocVT = MVT::v32i32;
419 ValVT = MVT::v32i32;
420 LocInfo = CCValAssign::Full;
421 } else if (LocVT == MVT::v256i8 || LocVT == MVT::v128i16 ||
422 LocVT == MVT::v64i32 || LocVT == MVT::v32i64) {
423 LocVT = MVT::v64i32;
424 ValVT = MVT::v64i32;
425 LocInfo = CCValAssign::Full;
426 }
427 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
428 if (!RetCC_Hexagon32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
429 return false;
430 }
431
432 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
433 if (!RetCC_Hexagon64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
434 return false;
435 }
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
437 if (!RetCC_HexagonVector(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
438 return false;
439 }
440 return true; // CC didn't match.
441 }
442
RetCC_Hexagon32(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)443 static bool RetCC_Hexagon32(unsigned ValNo, MVT ValVT,
444 MVT LocVT, CCValAssign::LocInfo LocInfo,
445 ISD::ArgFlagsTy ArgFlags, CCState &State) {
446
447 if (LocVT == MVT::i32 || LocVT == MVT::f32) {
448 if (unsigned Reg = State.AllocateReg(Hexagon::R0)) {
449 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
450 return false;
451 }
452 }
453
454 unsigned Offset = State.AllocateStack(4, 4);
455 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
456 return false;
457 }
458
RetCC_Hexagon64(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)459 static bool RetCC_Hexagon64(unsigned ValNo, MVT ValVT,
460 MVT LocVT, CCValAssign::LocInfo LocInfo,
461 ISD::ArgFlagsTy ArgFlags, CCState &State) {
462 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
463 if (unsigned Reg = State.AllocateReg(Hexagon::D0)) {
464 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
465 return false;
466 }
467 }
468
469 unsigned Offset = State.AllocateStack(8, 8);
470 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
471 return false;
472 }
473
RetCC_HexagonVector(unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State)474 static bool RetCC_HexagonVector(unsigned ValNo, MVT ValVT,
475 MVT LocVT, CCValAssign::LocInfo LocInfo,
476 ISD::ArgFlagsTy ArgFlags, CCState &State) {
477 auto &MF = State.getMachineFunction();
478 auto &HST = MF.getSubtarget<HexagonSubtarget>();
479 bool UseHVX = HST.useHVXOps();
480 bool UseHVXDbl = HST.useHVXDblOps();
481
482 unsigned OffSiz = 64;
483 if (LocVT == MVT::v16i32) {
484 if (unsigned Reg = State.AllocateReg(Hexagon::V0)) {
485 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
486 return false;
487 }
488 } else if (LocVT == MVT::v32i32) {
489 unsigned Req = (UseHVX && UseHVXDbl) ? Hexagon::V0 : Hexagon::W0;
490 if (unsigned Reg = State.AllocateReg(Req)) {
491 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
492 return false;
493 }
494 OffSiz = 128;
495 } else if (LocVT == MVT::v64i32) {
496 if (unsigned Reg = State.AllocateReg(Hexagon::W0)) {
497 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
498 return false;
499 }
500 OffSiz = 256;
501 }
502
503 unsigned Offset = State.AllocateStack(OffSiz, OffSiz);
504 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
505 return false;
506 }
507
promoteLdStType(EVT VT,EVT PromotedLdStVT)508 void HexagonTargetLowering::promoteLdStType(EVT VT, EVT PromotedLdStVT) {
509 if (VT != PromotedLdStVT) {
510 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
511 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(),
512 PromotedLdStVT.getSimpleVT());
513
514 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
515 AddPromotedToType(ISD::STORE, VT.getSimpleVT(),
516 PromotedLdStVT.getSimpleVT());
517 }
518 }
519
520 SDValue
LowerINTRINSIC_WO_CHAIN(SDValue Op,SelectionDAG & DAG) const521 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
522 const {
523 return SDValue();
524 }
525
526 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
527 /// by "Src" to address "Dst" of size "Size". Alignment information is
528 /// specified by the specific parameter attribute. The copy will be passed as
529 /// a byval function parameter. Sometimes what we are copying is the end of a
530 /// larger object, the part that does not fit in registers.
531 static SDValue
CreateCopyOfByValArgument(SDValue Src,SDValue Dst,SDValue Chain,ISD::ArgFlagsTy Flags,SelectionDAG & DAG,SDLoc dl)532 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
533 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
534 SDLoc dl) {
535
536 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
537 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
538 /*isVolatile=*/false, /*AlwaysInline=*/false,
539 /*isTailCall=*/false,
540 MachinePointerInfo(), MachinePointerInfo());
541 }
542
IsHvxVectorType(MVT ty)543 static bool IsHvxVectorType(MVT ty) {
544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 ||
545 ty == MVT::v64i8 ||
546 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 ||
547 ty == MVT::v128i8 ||
548 ty == MVT::v32i64 || ty == MVT::v64i32 || ty == MVT::v128i16 ||
549 ty == MVT::v256i8 ||
550 ty == MVT::v512i1 || ty == MVT::v1024i1);
551 }
552
553 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
554 // passed by value, the function prototype is modified to return void and
555 // the value is stored in memory pointed by a pointer passed by caller.
556 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc dl,SelectionDAG & DAG) const557 HexagonTargetLowering::LowerReturn(SDValue Chain,
558 CallingConv::ID CallConv, bool isVarArg,
559 const SmallVectorImpl<ISD::OutputArg> &Outs,
560 const SmallVectorImpl<SDValue> &OutVals,
561 SDLoc dl, SelectionDAG &DAG) const {
562
563 // CCValAssign - represent the assignment of the return value to locations.
564 SmallVector<CCValAssign, 16> RVLocs;
565
566 // CCState - Info about the registers and stack slot.
567 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
568 *DAG.getContext());
569
570 // Analyze return values of ISD::RET
571 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon);
572
573 SDValue Flag;
574 SmallVector<SDValue, 4> RetOps(1, Chain);
575
576 // Copy the result values into the output registers.
577 for (unsigned i = 0; i != RVLocs.size(); ++i) {
578 CCValAssign &VA = RVLocs[i];
579
580 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
581
582 // Guarantee that all emitted copies are stuck together with flags.
583 Flag = Chain.getValue(1);
584 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
585 }
586
587 RetOps[0] = Chain; // Update chain.
588
589 // Add the flag if we have it.
590 if (Flag.getNode())
591 RetOps.push_back(Flag);
592
593 return DAG.getNode(HexagonISD::RET_FLAG, dl, MVT::Other, RetOps);
594 }
595
mayBeEmittedAsTailCall(CallInst * CI) const596 bool HexagonTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
597 // If either no tail call or told not to tail call at all, don't.
598 auto Attr =
599 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
600 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
601 return false;
602
603 return true;
604 }
605
606 /// LowerCallResult - Lower the result values of an ISD::CALL into the
607 /// appropriate copies out of appropriate physical registers. This assumes that
608 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
609 /// being lowered. Returns a SDNode with the same number of values as the
610 /// ISD::CALL.
611 SDValue
LowerCallResult(SDValue Chain,SDValue InFlag,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals,const SmallVectorImpl<SDValue> & OutVals,SDValue Callee) const612 HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
613 CallingConv::ID CallConv, bool isVarArg,
614 const
615 SmallVectorImpl<ISD::InputArg> &Ins,
616 SDLoc dl, SelectionDAG &DAG,
617 SmallVectorImpl<SDValue> &InVals,
618 const SmallVectorImpl<SDValue> &OutVals,
619 SDValue Callee) const {
620
621 // Assign locations to each value returned by this call.
622 SmallVector<CCValAssign, 16> RVLocs;
623
624 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
625 *DAG.getContext());
626
627 CCInfo.AnalyzeCallResult(Ins, RetCC_Hexagon);
628
629 // Copy all of the result registers out of their specified physreg.
630 for (unsigned i = 0; i != RVLocs.size(); ++i) {
631 Chain = DAG.getCopyFromReg(Chain, dl,
632 RVLocs[i].getLocReg(),
633 RVLocs[i].getValVT(), InFlag).getValue(1);
634 InFlag = Chain.getValue(2);
635 InVals.push_back(Chain.getValue(0));
636 }
637
638 return Chain;
639 }
640
641 /// LowerCall - Functions arguments are copied from virtual regs to
642 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
643 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const644 HexagonTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
645 SmallVectorImpl<SDValue> &InVals) const {
646 SelectionDAG &DAG = CLI.DAG;
647 SDLoc &dl = CLI.DL;
648 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
649 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
650 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
651 SDValue Chain = CLI.Chain;
652 SDValue Callee = CLI.Callee;
653 bool &isTailCall = CLI.IsTailCall;
654 CallingConv::ID CallConv = CLI.CallConv;
655 bool isVarArg = CLI.IsVarArg;
656 bool doesNotReturn = CLI.DoesNotReturn;
657
658 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
659 MachineFunction &MF = DAG.getMachineFunction();
660 auto PtrVT = getPointerTy(MF.getDataLayout());
661
662 // Check for varargs.
663 int NumNamedVarArgParams = -1;
664 if (GlobalAddressSDNode *GAN = dyn_cast<GlobalAddressSDNode>(Callee)) {
665 const GlobalValue *GV = GAN->getGlobal();
666 Callee = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
667 if (const Function* F = dyn_cast<Function>(GV)) {
668 // If a function has zero args and is a vararg function, that's
669 // disallowed so it must be an undeclared function. Do not assume
670 // varargs if the callee is undefined.
671 if (F->isVarArg() && F->getFunctionType()->getNumParams() != 0)
672 NumNamedVarArgParams = F->getFunctionType()->getNumParams();
673 }
674 }
675
676 // Analyze operands of the call, assigning locations to each operand.
677 SmallVector<CCValAssign, 16> ArgLocs;
678 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
679 *DAG.getContext(), NumNamedVarArgParams);
680
681 if (isVarArg)
682 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg);
683 else
684 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon);
685
686 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
687 if (Attr.getValueAsString() == "true")
688 isTailCall = false;
689
690 if (isTailCall) {
691 bool StructAttrFlag = MF.getFunction()->hasStructRetAttr();
692 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
693 isVarArg, IsStructRet,
694 StructAttrFlag,
695 Outs, OutVals, Ins, DAG);
696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
697 CCValAssign &VA = ArgLocs[i];
698 if (VA.isMemLoc()) {
699 isTailCall = false;
700 break;
701 }
702 }
703 DEBUG(dbgs() << (isTailCall ? "Eligible for Tail Call\n"
704 : "Argument must be passed on stack. "
705 "Not eligible for Tail Call\n"));
706 }
707 // Get a count of how many bytes are to be pushed on the stack.
708 unsigned NumBytes = CCInfo.getNextStackOffset();
709 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
710 SmallVector<SDValue, 8> MemOpChains;
711
712 auto &HRI = *Subtarget.getRegisterInfo();
713 SDValue StackPtr =
714 DAG.getCopyFromReg(Chain, dl, HRI.getStackRegister(), PtrVT);
715
716 bool NeedsArgAlign = false;
717 unsigned LargestAlignSeen = 0;
718 // Walk the register/memloc assignments, inserting copies/loads.
719 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
720 CCValAssign &VA = ArgLocs[i];
721 SDValue Arg = OutVals[i];
722 ISD::ArgFlagsTy Flags = Outs[i].Flags;
723 // Record if we need > 8 byte alignment on an argument.
724 bool ArgAlign = IsHvxVectorType(VA.getValVT());
725 NeedsArgAlign |= ArgAlign;
726
727 // Promote the value if needed.
728 switch (VA.getLocInfo()) {
729 default:
730 // Loc info must be one of Full, SExt, ZExt, or AExt.
731 llvm_unreachable("Unknown loc info!");
732 case CCValAssign::BCvt:
733 case CCValAssign::Full:
734 break;
735 case CCValAssign::SExt:
736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
737 break;
738 case CCValAssign::ZExt:
739 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
740 break;
741 case CCValAssign::AExt:
742 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
743 break;
744 }
745
746 if (VA.isMemLoc()) {
747 unsigned LocMemOffset = VA.getLocMemOffset();
748 SDValue MemAddr = DAG.getConstant(LocMemOffset, dl,
749 StackPtr.getValueType());
750 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
751 if (ArgAlign)
752 LargestAlignSeen = std::max(LargestAlignSeen,
753 VA.getLocVT().getStoreSizeInBits() >> 3);
754 if (Flags.isByVal()) {
755 // The argument is a struct passed by value. According to LLVM, "Arg"
756 // is is pointer.
757 MemOpChains.push_back(CreateCopyOfByValArgument(Arg, MemAddr, Chain,
758 Flags, DAG, dl));
759 } else {
760 MachinePointerInfo LocPI = MachinePointerInfo::getStack(
761 DAG.getMachineFunction(), LocMemOffset);
762 SDValue S = DAG.getStore(Chain, dl, Arg, MemAddr, LocPI, false,
763 false, 0);
764 MemOpChains.push_back(S);
765 }
766 continue;
767 }
768
769 // Arguments that can be passed on register must be kept at RegsToPass
770 // vector.
771 if (VA.isRegLoc())
772 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
773 }
774
775 if (NeedsArgAlign && Subtarget.hasV60TOps()) {
776 DEBUG(dbgs() << "Function needs byte stack align due to call args\n");
777 MachineFrameInfo* MFI = DAG.getMachineFunction().getFrameInfo();
778 // V6 vectors passed by value have 64 or 128 byte alignment depending
779 // on whether we are 64 byte vector mode or 128 byte.
780 bool UseHVXDbl = Subtarget.useHVXDblOps();
781 assert(Subtarget.useHVXOps());
782 const unsigned ObjAlign = UseHVXDbl ? 128 : 64;
783 LargestAlignSeen = std::max(LargestAlignSeen, ObjAlign);
784 MFI->ensureMaxAlignment(LargestAlignSeen);
785 }
786 // Transform all store nodes into one single node because all store
787 // nodes are independent of each other.
788 if (!MemOpChains.empty())
789 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
790
791 if (!isTailCall) {
792 SDValue C = DAG.getConstant(NumBytes, dl, PtrVT, true);
793 Chain = DAG.getCALLSEQ_START(Chain, C, dl);
794 }
795
796 // Build a sequence of copy-to-reg nodes chained together with token
797 // chain and flag operands which copy the outgoing args into registers.
798 // The InFlag in necessary since all emitted instructions must be
799 // stuck together.
800 SDValue InFlag;
801 if (!isTailCall) {
802 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
803 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
804 RegsToPass[i].second, InFlag);
805 InFlag = Chain.getValue(1);
806 }
807 } else {
808 // For tail calls lower the arguments to the 'real' stack slot.
809 //
810 // Force all the incoming stack arguments to be loaded from the stack
811 // before any new outgoing arguments are stored to the stack, because the
812 // outgoing stack slots may alias the incoming argument stack slots, and
813 // the alias isn't otherwise explicit. This is slightly more conservative
814 // than necessary, because it means that each store effectively depends
815 // on every argument instead of just those arguments it would clobber.
816 //
817 // Do not flag preceding copytoreg stuff together with the following stuff.
818 InFlag = SDValue();
819 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
820 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
821 RegsToPass[i].second, InFlag);
822 InFlag = Chain.getValue(1);
823 }
824 InFlag = SDValue();
825 }
826
827 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
828 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
829 // node so that legalize doesn't hack it.
830 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
831 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, PtrVT);
832 } else if (ExternalSymbolSDNode *S =
833 dyn_cast<ExternalSymbolSDNode>(Callee)) {
834 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT);
835 }
836
837 // Returns a chain & a flag for retval copy to use.
838 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
839 SmallVector<SDValue, 8> Ops;
840 Ops.push_back(Chain);
841 Ops.push_back(Callee);
842
843 // Add argument registers to the end of the list so that they are
844 // known live into the call.
845 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
846 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
847 RegsToPass[i].second.getValueType()));
848 }
849
850 if (InFlag.getNode())
851 Ops.push_back(InFlag);
852
853 if (isTailCall) {
854 MF.getFrameInfo()->setHasTailCall();
855 return DAG.getNode(HexagonISD::TC_RETURN, dl, NodeTys, Ops);
856 }
857
858 int OpCode = doesNotReturn ? HexagonISD::CALLv3nr : HexagonISD::CALLv3;
859 Chain = DAG.getNode(OpCode, dl, NodeTys, Ops);
860 InFlag = Chain.getValue(1);
861
862 // Create the CALLSEQ_END node.
863 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
864 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
865 InFlag = Chain.getValue(1);
866
867 // Handle result values, copying them out of physregs into vregs that we
868 // return.
869 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
870 InVals, OutVals, Callee);
871 }
872
getIndexedAddressParts(SDNode * Ptr,EVT VT,bool isSEXTLoad,SDValue & Base,SDValue & Offset,bool & isInc,SelectionDAG & DAG)873 static bool getIndexedAddressParts(SDNode *Ptr, EVT VT,
874 bool isSEXTLoad, SDValue &Base,
875 SDValue &Offset, bool &isInc,
876 SelectionDAG &DAG) {
877 if (Ptr->getOpcode() != ISD::ADD)
878 return false;
879
880 auto &HST = static_cast<const HexagonSubtarget&>(DAG.getSubtarget());
881 bool UseHVX = HST.useHVXOps();
882 bool UseHVXDbl = HST.useHVXDblOps();
883
884 bool ValidHVXDblType =
885 (UseHVX && UseHVXDbl) && (VT == MVT::v32i32 || VT == MVT::v16i64 ||
886 VT == MVT::v64i16 || VT == MVT::v128i8);
887 bool ValidHVXType =
888 UseHVX && !UseHVXDbl && (VT == MVT::v16i32 || VT == MVT::v8i64 ||
889 VT == MVT::v32i16 || VT == MVT::v64i8);
890
891 if (ValidHVXDblType || ValidHVXType ||
892 VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
893 isInc = (Ptr->getOpcode() == ISD::ADD);
894 Base = Ptr->getOperand(0);
895 Offset = Ptr->getOperand(1);
896 // Ensure that Offset is a constant.
897 return (isa<ConstantSDNode>(Offset));
898 }
899
900 return false;
901 }
902
903 /// getPostIndexedAddressParts - returns true by value, base pointer and
904 /// offset pointer and addressing mode by reference if this node can be
905 /// combined with a load / store to form a post-indexed load / store.
getPostIndexedAddressParts(SDNode * N,SDNode * Op,SDValue & Base,SDValue & Offset,ISD::MemIndexedMode & AM,SelectionDAG & DAG) const906 bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
907 SDValue &Base,
908 SDValue &Offset,
909 ISD::MemIndexedMode &AM,
910 SelectionDAG &DAG) const
911 {
912 EVT VT;
913 SDValue Ptr;
914 bool isSEXTLoad = false;
915
916 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
917 VT = LD->getMemoryVT();
918 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
919 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
920 VT = ST->getMemoryVT();
921 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
922 return false;
923 }
924 } else {
925 return false;
926 }
927
928 bool isInc = false;
929 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
930 isInc, DAG);
931 if (isLegal) {
932 auto &HII = *Subtarget.getInstrInfo();
933 int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
934 if (HII.isValidAutoIncImm(VT, OffsetVal)) {
935 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
936 return true;
937 }
938 }
939
940 return false;
941 }
942
943 SDValue
LowerINLINEASM(SDValue Op,SelectionDAG & DAG) const944 HexagonTargetLowering::LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const {
945 SDNode *Node = Op.getNode();
946 MachineFunction &MF = DAG.getMachineFunction();
947 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
948 switch (Node->getOpcode()) {
949 case ISD::INLINEASM: {
950 unsigned NumOps = Node->getNumOperands();
951 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
952 --NumOps; // Ignore the flag operand.
953
954 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
955 if (FuncInfo.hasClobberLR())
956 break;
957 unsigned Flags =
958 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
959 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
960 ++i; // Skip the ID value.
961
962 switch (InlineAsm::getKind(Flags)) {
963 default: llvm_unreachable("Bad flags!");
964 case InlineAsm::Kind_RegDef:
965 case InlineAsm::Kind_RegUse:
966 case InlineAsm::Kind_Imm:
967 case InlineAsm::Kind_Clobber:
968 case InlineAsm::Kind_Mem: {
969 for (; NumVals; --NumVals, ++i) {}
970 break;
971 }
972 case InlineAsm::Kind_RegDefEarlyClobber: {
973 for (; NumVals; --NumVals, ++i) {
974 unsigned Reg =
975 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
976
977 // Check it to be lr
978 const HexagonRegisterInfo *QRI = Subtarget.getRegisterInfo();
979 if (Reg == QRI->getRARegister()) {
980 FuncInfo.setHasClobberLR(true);
981 break;
982 }
983 }
984 break;
985 }
986 }
987 }
988 }
989 } // Node->getOpcode
990 return Op;
991 }
992
993 SDValue
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG) const994 HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
995 SelectionDAG &DAG) const {
996 SDValue Chain = Op.getOperand(0);
997 SDValue Size = Op.getOperand(1);
998 SDValue Align = Op.getOperand(2);
999 SDLoc dl(Op);
1000
1001 ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
1002 assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
1003
1004 unsigned A = AlignConst->getSExtValue();
1005 auto &HFI = *Subtarget.getFrameLowering();
1006 // "Zero" means natural stack alignment.
1007 if (A == 0)
1008 A = HFI.getStackAlignment();
1009
1010 DEBUG({
1011 dbgs () << LLVM_FUNCTION_NAME << " Align: " << A << " Size: ";
1012 Size.getNode()->dump(&DAG);
1013 dbgs() << "\n";
1014 });
1015
1016 SDValue AC = DAG.getConstant(A, dl, MVT::i32);
1017 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1018 SDValue AA = DAG.getNode(HexagonISD::ALLOCA, dl, VTs, Chain, Size, AC);
1019 if (Op.getNode()->getHasDebugValue())
1020 DAG.TransferDbgValues(Op, AA);
1021 return AA;
1022 }
1023
1024 SDValue
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const1025 HexagonTargetLowering::LowerFormalArguments(SDValue Chain,
1026 CallingConv::ID CallConv,
1027 bool isVarArg,
1028 const
1029 SmallVectorImpl<ISD::InputArg> &Ins,
1030 SDLoc dl, SelectionDAG &DAG,
1031 SmallVectorImpl<SDValue> &InVals)
1032 const {
1033
1034 MachineFunction &MF = DAG.getMachineFunction();
1035 MachineFrameInfo *MFI = MF.getFrameInfo();
1036 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1037 auto &FuncInfo = *MF.getInfo<HexagonMachineFunctionInfo>();
1038
1039 // Assign locations to all of the incoming arguments.
1040 SmallVector<CCValAssign, 16> ArgLocs;
1041 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1042 *DAG.getContext());
1043
1044 CCInfo.AnalyzeFormalArguments(Ins, CC_Hexagon);
1045
1046 // For LLVM, in the case when returning a struct by value (>8byte),
1047 // the first argument is a pointer that points to the location on caller's
1048 // stack where the return value will be stored. For Hexagon, the location on
1049 // caller's stack is passed only when the struct size is smaller than (and
1050 // equal to) 8 bytes. If not, no address will be passed into callee and
1051 // callee return the result direclty through R0/R1.
1052
1053 SmallVector<SDValue, 8> MemOps;
1054 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
1055
1056 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1057 CCValAssign &VA = ArgLocs[i];
1058 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1059 unsigned ObjSize;
1060 unsigned StackLocation;
1061 int FI;
1062
1063 if ( (VA.isRegLoc() && !Flags.isByVal())
1064 || (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() > 8)) {
1065 // Arguments passed in registers
1066 // 1. int, long long, ptr args that get allocated in register.
1067 // 2. Large struct that gets an register to put its address in.
1068 EVT RegVT = VA.getLocVT();
1069 if (RegVT == MVT::i8 || RegVT == MVT::i16 ||
1070 RegVT == MVT::i32 || RegVT == MVT::f32) {
1071 unsigned VReg =
1072 RegInfo.createVirtualRegister(&Hexagon::IntRegsRegClass);
1073 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1074 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1075 } else if (RegVT == MVT::i64 || RegVT == MVT::f64) {
1076 unsigned VReg =
1077 RegInfo.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
1078 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1079 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1080
1081 // Single Vector
1082 } else if ((RegVT == MVT::v8i64 || RegVT == MVT::v16i32 ||
1083 RegVT == MVT::v32i16 || RegVT == MVT::v64i8)) {
1084 unsigned VReg =
1085 RegInfo.createVirtualRegister(&Hexagon::VectorRegsRegClass);
1086 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1087 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1088 } else if (UseHVX && UseHVXDbl &&
1089 ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1090 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) {
1091 unsigned VReg =
1092 RegInfo.createVirtualRegister(&Hexagon::VectorRegs128BRegClass);
1093 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1094 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1095
1096 // Double Vector
1097 } else if ((RegVT == MVT::v16i64 || RegVT == MVT::v32i32 ||
1098 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) {
1099 unsigned VReg =
1100 RegInfo.createVirtualRegister(&Hexagon::VecDblRegsRegClass);
1101 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1102 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1103 } else if (UseHVX && UseHVXDbl &&
1104 ((RegVT == MVT::v32i64 || RegVT == MVT::v64i32 ||
1105 RegVT == MVT::v128i16 || RegVT == MVT::v256i8))) {
1106 unsigned VReg =
1107 RegInfo.createVirtualRegister(&Hexagon::VecDblRegs128BRegClass);
1108 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1109 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1110 } else if (RegVT == MVT::v512i1 || RegVT == MVT::v1024i1) {
1111 assert(0 && "need to support VecPred regs");
1112 unsigned VReg =
1113 RegInfo.createVirtualRegister(&Hexagon::VecPredRegsRegClass);
1114 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1115 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1116 } else {
1117 assert (0);
1118 }
1119 } else if (VA.isRegLoc() && Flags.isByVal() && Flags.getByValSize() <= 8) {
1120 assert (0 && "ByValSize must be bigger than 8 bytes");
1121 } else {
1122 // Sanity check.
1123 assert(VA.isMemLoc());
1124
1125 if (Flags.isByVal()) {
1126 // If it's a byval parameter, then we need to compute the
1127 // "real" size, not the size of the pointer.
1128 ObjSize = Flags.getByValSize();
1129 } else {
1130 ObjSize = VA.getLocVT().getStoreSizeInBits() >> 3;
1131 }
1132
1133 StackLocation = HEXAGON_LRFP_SIZE + VA.getLocMemOffset();
1134 // Create the frame index object for this incoming parameter...
1135 FI = MFI->CreateFixedObject(ObjSize, StackLocation, true);
1136
1137 // Create the SelectionDAG nodes cordl, responding to a load
1138 // from this parameter.
1139 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1140
1141 if (Flags.isByVal()) {
1142 // If it's a pass-by-value aggregate, then do not dereference the stack
1143 // location. Instead, we should generate a reference to the stack
1144 // location.
1145 InVals.push_back(FIN);
1146 } else {
1147 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1148 MachinePointerInfo(), false, false,
1149 false, 0));
1150 }
1151 }
1152 }
1153
1154 if (!MemOps.empty())
1155 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1156
1157 if (isVarArg) {
1158 // This will point to the next argument passed via stack.
1159 int FrameIndex = MFI->CreateFixedObject(Hexagon_PointerSize,
1160 HEXAGON_LRFP_SIZE +
1161 CCInfo.getNextStackOffset(),
1162 true);
1163 FuncInfo.setVarArgsFrameIndex(FrameIndex);
1164 }
1165
1166 return Chain;
1167 }
1168
1169 SDValue
LowerVASTART(SDValue Op,SelectionDAG & DAG) const1170 HexagonTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
1171 // VASTART stores the address of the VarArgsFrameIndex slot into the
1172 // memory location argument.
1173 MachineFunction &MF = DAG.getMachineFunction();
1174 HexagonMachineFunctionInfo *QFI = MF.getInfo<HexagonMachineFunctionInfo>();
1175 SDValue Addr = DAG.getFrameIndex(QFI->getVarArgsFrameIndex(), MVT::i32);
1176 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1177 return DAG.getStore(Op.getOperand(0), SDLoc(Op), Addr,
1178 Op.getOperand(1), MachinePointerInfo(SV), false,
1179 false, 0);
1180 }
1181
1182 // Creates a SPLAT instruction for a constant value VAL.
createSplat(SelectionDAG & DAG,SDLoc dl,EVT VT,SDValue Val)1183 static SDValue createSplat(SelectionDAG &DAG, SDLoc dl, EVT VT, SDValue Val) {
1184 if (VT.getSimpleVT() == MVT::v4i8)
1185 return DAG.getNode(HexagonISD::VSPLATB, dl, VT, Val);
1186
1187 if (VT.getSimpleVT() == MVT::v4i16)
1188 return DAG.getNode(HexagonISD::VSPLATH, dl, VT, Val);
1189
1190 return SDValue();
1191 }
1192
isSExtFree(SDValue N)1193 static bool isSExtFree(SDValue N) {
1194 // A sign-extend of a truncate of a sign-extend is free.
1195 if (N.getOpcode() == ISD::TRUNCATE &&
1196 N.getOperand(0).getOpcode() == ISD::AssertSext)
1197 return true;
1198 // We have sign-extended loads.
1199 if (N.getOpcode() == ISD::LOAD)
1200 return true;
1201 return false;
1202 }
1203
LowerCTPOP(SDValue Op,SelectionDAG & DAG) const1204 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
1205 SDLoc dl(Op);
1206 SDValue InpVal = Op.getOperand(0);
1207 if (isa<ConstantSDNode>(InpVal)) {
1208 uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
1209 return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
1210 }
1211 SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
1212 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1213 }
1214
LowerSETCC(SDValue Op,SelectionDAG & DAG) const1215 SDValue HexagonTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1216 SDLoc dl(Op);
1217
1218 SDValue LHS = Op.getOperand(0);
1219 SDValue RHS = Op.getOperand(1);
1220 SDValue Cmp = Op.getOperand(2);
1221 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1222
1223 EVT VT = Op.getValueType();
1224 EVT LHSVT = LHS.getValueType();
1225 EVT RHSVT = RHS.getValueType();
1226
1227 if (LHSVT == MVT::v2i16) {
1228 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1229 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1230 : ISD::ZERO_EXTEND;
1231 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS);
1232 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS);
1233 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1234 return SC;
1235 }
1236
1237 // Treat all other vector types as legal.
1238 if (VT.isVector())
1239 return Op;
1240
1241 // Equals and not equals should use sign-extend, not zero-extend, since
1242 // we can represent small negative values in the compare instructions.
1243 // The LLVM default is to use zero-extend arbitrarily in these cases.
1244 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1245 (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
1246 (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
1247 ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
1248 if (C && C->getAPIntValue().isNegative()) {
1249 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1250 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1251 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1252 LHS, RHS, Op.getOperand(2));
1253 }
1254 if (isSExtFree(LHS) || isSExtFree(RHS)) {
1255 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1256 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1257 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1258 LHS, RHS, Op.getOperand(2));
1259 }
1260 }
1261 return SDValue();
1262 }
1263
1264 SDValue
LowerVSELECT(SDValue Op,SelectionDAG & DAG) const1265 HexagonTargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
1266 SDValue PredOp = Op.getOperand(0);
1267 SDValue Op1 = Op.getOperand(1), Op2 = Op.getOperand(2);
1268 EVT OpVT = Op1.getValueType();
1269 SDLoc DL(Op);
1270
1271 if (OpVT == MVT::v2i16) {
1272 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1273 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1274 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1275 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1276 return TR;
1277 }
1278
1279 return SDValue();
1280 }
1281
1282 // Handle only specific vector loads.
LowerLOAD(SDValue Op,SelectionDAG & DAG) const1283 SDValue HexagonTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1284 EVT VT = Op.getValueType();
1285 SDLoc DL(Op);
1286 LoadSDNode *LoadNode = cast<LoadSDNode>(Op);
1287 SDValue Chain = LoadNode->getChain();
1288 SDValue Ptr = Op.getOperand(1);
1289 SDValue LoweredLoad;
1290 SDValue Result;
1291 SDValue Base = LoadNode->getBasePtr();
1292 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1293 unsigned Alignment = LoadNode->getAlignment();
1294 SDValue LoadChain;
1295
1296 if(Ext == ISD::NON_EXTLOAD)
1297 Ext = ISD::ZEXTLOAD;
1298
1299 if (VT == MVT::v4i16) {
1300 if (Alignment == 2) {
1301 SDValue Loads[4];
1302 // Base load.
1303 Loads[0] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Base,
1304 LoadNode->getPointerInfo(), MVT::i16,
1305 LoadNode->isVolatile(),
1306 LoadNode->isNonTemporal(),
1307 LoadNode->isInvariant(),
1308 Alignment);
1309 // Base+2 load.
1310 SDValue Increment = DAG.getConstant(2, DL, MVT::i32);
1311 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1312 Loads[1] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1313 LoadNode->getPointerInfo(), MVT::i16,
1314 LoadNode->isVolatile(),
1315 LoadNode->isNonTemporal(),
1316 LoadNode->isInvariant(),
1317 Alignment);
1318 // SHL 16, then OR base and base+2.
1319 SDValue ShiftAmount = DAG.getConstant(16, DL, MVT::i32);
1320 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1321 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1322 // Base + 4.
1323 Increment = DAG.getConstant(4, DL, MVT::i32);
1324 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1325 Loads[2] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1326 LoadNode->getPointerInfo(), MVT::i16,
1327 LoadNode->isVolatile(),
1328 LoadNode->isNonTemporal(),
1329 LoadNode->isInvariant(),
1330 Alignment);
1331 // Base + 6.
1332 Increment = DAG.getConstant(6, DL, MVT::i32);
1333 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1334 Loads[3] = DAG.getExtLoad(Ext, DL, MVT::i32, Chain, Ptr,
1335 LoadNode->getPointerInfo(), MVT::i16,
1336 LoadNode->isVolatile(),
1337 LoadNode->isNonTemporal(),
1338 LoadNode->isInvariant(),
1339 Alignment);
1340 // SHL 16, then OR base+4 and base+6.
1341 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1342 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1343 // Combine to i64. This could be optimised out later if we can
1344 // affect reg allocation of this code.
1345 Result = DAG.getNode(HexagonISD::COMBINE, DL, MVT::i64, Tmp4, Tmp2);
1346 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1347 Loads[0].getValue(1), Loads[1].getValue(1),
1348 Loads[2].getValue(1), Loads[3].getValue(1));
1349 } else {
1350 // Perform default type expansion.
1351 Result = DAG.getLoad(MVT::i64, DL, Chain, Ptr, LoadNode->getPointerInfo(),
1352 LoadNode->isVolatile(), LoadNode->isNonTemporal(),
1353 LoadNode->isInvariant(), LoadNode->getAlignment());
1354 LoadChain = Result.getValue(1);
1355 }
1356 } else
1357 llvm_unreachable("Custom lowering unsupported load");
1358
1359 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1360 // Since we pretend to lower a load, we need the original chain
1361 // info attached to the result.
1362 SDValue Ops[] = { Result, LoadChain };
1363
1364 return DAG.getMergeValues(Ops, DL);
1365 }
1366
1367
1368 SDValue
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const1369 HexagonTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
1370 EVT ValTy = Op.getValueType();
1371 ConstantPoolSDNode *CPN = cast<ConstantPoolSDNode>(Op);
1372 unsigned Align = CPN->getAlignment();
1373 Reloc::Model RM = HTM.getRelocationModel();
1374 unsigned char TF = (RM == Reloc::PIC_) ? HexagonII::MO_PCREL : 0;
1375
1376 SDValue T;
1377 if (CPN->isMachineConstantPoolEntry())
1378 T = DAG.getTargetConstantPool(CPN->getMachineCPVal(), ValTy, Align, TF);
1379 else
1380 T = DAG.getTargetConstantPool(CPN->getConstVal(), ValTy, Align, TF);
1381 if (RM == Reloc::PIC_)
1382 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), ValTy, T);
1383 return DAG.getNode(HexagonISD::CP, SDLoc(Op), ValTy, T);
1384 }
1385
1386 SDValue
LowerJumpTable(SDValue Op,SelectionDAG & DAG) const1387 HexagonTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1388 EVT VT = Op.getValueType();
1389 int Idx = cast<JumpTableSDNode>(Op)->getIndex();
1390 Reloc::Model RM = HTM.getRelocationModel();
1391 if (RM == Reloc::PIC_) {
1392 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
1393 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), VT, T);
1394 }
1395
1396 SDValue T = DAG.getTargetJumpTable(Idx, VT);
1397 return DAG.getNode(HexagonISD::JT, SDLoc(Op), VT, T);
1398 }
1399
1400 SDValue
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG) const1401 HexagonTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
1402 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1403 MachineFunction &MF = DAG.getMachineFunction();
1404 MachineFrameInfo &MFI = *MF.getFrameInfo();
1405 MFI.setReturnAddressIsTaken(true);
1406
1407 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
1408 return SDValue();
1409
1410 EVT VT = Op.getValueType();
1411 SDLoc dl(Op);
1412 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1413 if (Depth) {
1414 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
1415 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
1416 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
1417 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1418 MachinePointerInfo(), false, false, false, 0);
1419 }
1420
1421 // Return LR, which contains the return address. Mark it an implicit live-in.
1422 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32));
1423 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
1424 }
1425
1426 SDValue
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG) const1427 HexagonTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
1428 const HexagonRegisterInfo &HRI = *Subtarget.getRegisterInfo();
1429 MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
1430 MFI.setFrameAddressIsTaken(true);
1431
1432 EVT VT = Op.getValueType();
1433 SDLoc dl(Op);
1434 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1435 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
1436 HRI.getFrameRegister(), VT);
1437 while (Depth--)
1438 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
1439 MachinePointerInfo(),
1440 false, false, false, 0);
1441 return FrameAddr;
1442 }
1443
1444 SDValue
LowerATOMIC_FENCE(SDValue Op,SelectionDAG & DAG) const1445 HexagonTargetLowering::LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const {
1446 SDLoc dl(Op);
1447 return DAG.getNode(HexagonISD::BARRIER, dl, MVT::Other, Op.getOperand(0));
1448 }
1449
1450
1451 SDValue
LowerGLOBALADDRESS(SDValue Op,SelectionDAG & DAG) const1452 HexagonTargetLowering::LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const {
1453 SDLoc dl(Op);
1454 auto *GAN = cast<GlobalAddressSDNode>(Op);
1455 auto PtrVT = getPointerTy(DAG.getDataLayout());
1456 auto *GV = GAN->getGlobal();
1457 int64_t Offset = GAN->getOffset();
1458
1459 auto &HLOF = *HTM.getObjFileLowering();
1460 Reloc::Model RM = HTM.getRelocationModel();
1461
1462 if (RM == Reloc::Static) {
1463 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset);
1464 if (HLOF.IsGlobalInSmallSection(GV, HTM))
1465 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, GA);
1466 return DAG.getNode(HexagonISD::CONST32, dl, PtrVT, GA);
1467 }
1468
1469 bool UsePCRel = GV->hasInternalLinkage() || GV->hasHiddenVisibility() ||
1470 (GV->hasLocalLinkage() && !isa<Function>(GV));
1471 if (UsePCRel) {
1472 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, Offset,
1473 HexagonII::MO_PCREL);
1474 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, GA);
1475 }
1476
1477 // Use GOT index.
1478 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1479 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, HexagonII::MO_GOT);
1480 SDValue Off = DAG.getConstant(Offset, dl, MVT::i32);
1481 return DAG.getNode(HexagonISD::AT_GOT, dl, PtrVT, GOT, GA, Off);
1482 }
1483
1484 // Specifies that for loads and stores VT can be promoted to PromotedLdStVT.
1485 SDValue
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1486 HexagonTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const {
1487 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1488 SDLoc dl(Op);
1489 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1490
1491 Reloc::Model RM = HTM.getRelocationModel();
1492 if (RM == Reloc::Static) {
1493 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT);
1494 return DAG.getNode(HexagonISD::CONST32_GP, dl, PtrVT, A);
1495 }
1496
1497 SDValue A = DAG.getTargetBlockAddress(BA, PtrVT, 0, HexagonII::MO_PCREL);
1498 return DAG.getNode(HexagonISD::AT_PCREL, dl, PtrVT, A);
1499 }
1500
1501 SDValue
LowerGLOBAL_OFFSET_TABLE(SDValue Op,SelectionDAG & DAG) const1502 HexagonTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG)
1503 const {
1504 EVT PtrVT = getPointerTy(DAG.getDataLayout());
1505 SDValue GOTSym = DAG.getTargetExternalSymbol(HEXAGON_GOT_SYM_NAME, PtrVT,
1506 HexagonII::MO_PCREL);
1507 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Op), PtrVT, GOTSym);
1508 }
1509
1510 //===----------------------------------------------------------------------===//
1511 // TargetLowering Implementation
1512 //===----------------------------------------------------------------------===//
1513
HexagonTargetLowering(const TargetMachine & TM,const HexagonSubtarget & ST)1514 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
1515 const HexagonSubtarget &ST)
1516 : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
1517 Subtarget(ST) {
1518 bool IsV4 = !Subtarget.hasV5TOps();
1519 auto &HRI = *Subtarget.getRegisterInfo();
1520 bool UseHVX = Subtarget.useHVXOps();
1521 bool UseHVXSgl = Subtarget.useHVXSglOps();
1522 bool UseHVXDbl = Subtarget.useHVXDblOps();
1523
1524 setPrefLoopAlignment(4);
1525 setPrefFunctionAlignment(4);
1526 setMinFunctionAlignment(2);
1527 setInsertFencesForAtomic(false);
1528 setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
1529
1530 if (EnableHexSDNodeSched)
1531 setSchedulingPreference(Sched::VLIW);
1532 else
1533 setSchedulingPreference(Sched::Source);
1534
1535 // Limits for inline expansion of memcpy/memmove
1536 MaxStoresPerMemcpy = MaxStoresPerMemcpyCL;
1537 MaxStoresPerMemcpyOptSize = MaxStoresPerMemcpyOptSizeCL;
1538 MaxStoresPerMemmove = MaxStoresPerMemmoveCL;
1539 MaxStoresPerMemmoveOptSize = MaxStoresPerMemmoveOptSizeCL;
1540 MaxStoresPerMemset = MaxStoresPerMemsetCL;
1541 MaxStoresPerMemsetOptSize = MaxStoresPerMemsetOptSizeCL;
1542
1543 //
1544 // Set up register classes.
1545 //
1546
1547 addRegisterClass(MVT::i1, &Hexagon::PredRegsRegClass);
1548 addRegisterClass(MVT::v2i1, &Hexagon::PredRegsRegClass); // bbbbaaaa
1549 addRegisterClass(MVT::v4i1, &Hexagon::PredRegsRegClass); // ddccbbaa
1550 addRegisterClass(MVT::v8i1, &Hexagon::PredRegsRegClass); // hgfedcba
1551 addRegisterClass(MVT::i32, &Hexagon::IntRegsRegClass);
1552 addRegisterClass(MVT::v4i8, &Hexagon::IntRegsRegClass);
1553 addRegisterClass(MVT::v2i16, &Hexagon::IntRegsRegClass);
1554 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1555 addRegisterClass(MVT::v8i8, &Hexagon::DoubleRegsRegClass);
1556 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass);
1557 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass);
1558
1559 if (Subtarget.hasV5TOps()) {
1560 addRegisterClass(MVT::f32, &Hexagon::IntRegsRegClass);
1561 addRegisterClass(MVT::f64, &Hexagon::DoubleRegsRegClass);
1562 }
1563
1564 if (Subtarget.hasV60TOps()) {
1565 if (Subtarget.useHVXSglOps()) {
1566 addRegisterClass(MVT::v64i8, &Hexagon::VectorRegsRegClass);
1567 addRegisterClass(MVT::v32i16, &Hexagon::VectorRegsRegClass);
1568 addRegisterClass(MVT::v16i32, &Hexagon::VectorRegsRegClass);
1569 addRegisterClass(MVT::v8i64, &Hexagon::VectorRegsRegClass);
1570 addRegisterClass(MVT::v128i8, &Hexagon::VecDblRegsRegClass);
1571 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass);
1572 addRegisterClass(MVT::v32i32, &Hexagon::VecDblRegsRegClass);
1573 addRegisterClass(MVT::v16i64, &Hexagon::VecDblRegsRegClass);
1574 addRegisterClass(MVT::v512i1, &Hexagon::VecPredRegsRegClass);
1575 } else if (Subtarget.useHVXDblOps()) {
1576 addRegisterClass(MVT::v128i8, &Hexagon::VectorRegs128BRegClass);
1577 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass);
1578 addRegisterClass(MVT::v32i32, &Hexagon::VectorRegs128BRegClass);
1579 addRegisterClass(MVT::v16i64, &Hexagon::VectorRegs128BRegClass);
1580 addRegisterClass(MVT::v256i8, &Hexagon::VecDblRegs128BRegClass);
1581 addRegisterClass(MVT::v128i16, &Hexagon::VecDblRegs128BRegClass);
1582 addRegisterClass(MVT::v64i32, &Hexagon::VecDblRegs128BRegClass);
1583 addRegisterClass(MVT::v32i64, &Hexagon::VecDblRegs128BRegClass);
1584 addRegisterClass(MVT::v1024i1, &Hexagon::VecPredRegs128BRegClass);
1585 }
1586
1587 }
1588
1589 //
1590 // Handling of scalar operations.
1591 //
1592 // All operations default to "legal", except:
1593 // - indexed loads and stores (pre-/post-incremented),
1594 // - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
1595 // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1596 // FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1597 // FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1598 // which default to "expand" for at least one type.
1599
1600 // Misc operations.
1601 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1602 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1603
1604 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1605 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1606 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1608 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1609 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1610 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1611 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1612
1613 // Custom legalize GlobalAddress nodes into CONST32.
1614 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1615 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1616 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1617
1618 // Hexagon needs to optimize cases with negative constants.
1619 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1620 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1621
1622 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1623 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1624 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1625 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1626
1627 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1628 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1629 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1630
1631 if (EmitJumpTables)
1632 setMinimumJumpTableEntries(2);
1633 else
1634 setMinimumJumpTableEntries(MinimumJumpTables);
1635 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1636
1637 // Hexagon has instructions for add/sub with carry. The problem with
1638 // modeling these instructions is that they produce 2 results: Rdd and Px.
1639 // To model the update of Px, we will have to use Defs[p0..p3] which will
1640 // cause any predicate live range to spill. So, we pretend we dont't have
1641 // these instructions.
1642 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1643 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1644 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1645 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1646 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1647 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1648 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1649 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1650 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1651 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1652 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1653 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1654 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1655 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1656 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1657 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1658
1659 // Only add and sub that detect overflow are the saturating ones.
1660 for (MVT VT : MVT::integer_valuetypes()) {
1661 setOperationAction(ISD::UADDO, VT, Expand);
1662 setOperationAction(ISD::SADDO, VT, Expand);
1663 setOperationAction(ISD::USUBO, VT, Expand);
1664 setOperationAction(ISD::SSUBO, VT, Expand);
1665 }
1666
1667 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1668 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1669 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1670 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1671 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Promote);
1672 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
1673 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Promote);
1674 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
1675
1676 // In V5, popcount can count # of 1s in i64 but returns i32.
1677 // On V4 it will be expanded (set later).
1678 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1679 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1680 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1681 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
1682
1683 // We custom lower i64 to i64 mul, so that it is not considered as a legal
1684 // operation. There is a pattern that will match i64 mul and transform it
1685 // to a series of instructions.
1686 setOperationAction(ISD::MUL, MVT::i64, Expand);
1687 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1688
1689 for (unsigned IntExpOp :
1690 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1691 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1692 ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1693 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1694 setOperationAction(IntExpOp, MVT::i32, Expand);
1695 setOperationAction(IntExpOp, MVT::i64, Expand);
1696 }
1697
1698 for (unsigned FPExpOp :
1699 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1700 ISD::FPOW, ISD::FCOPYSIGN}) {
1701 setOperationAction(FPExpOp, MVT::f32, Expand);
1702 setOperationAction(FPExpOp, MVT::f64, Expand);
1703 }
1704
1705 // No extending loads from i32.
1706 for (MVT VT : MVT::integer_valuetypes()) {
1707 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1708 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1709 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1710 }
1711 // Turn FP truncstore into trunc + store.
1712 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1713 // Turn FP extload into load/fextend.
1714 for (MVT VT : MVT::fp_valuetypes())
1715 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1716
1717 // Expand BR_CC and SELECT_CC for all integer and fp types.
1718 for (MVT VT : MVT::integer_valuetypes()) {
1719 setOperationAction(ISD::BR_CC, VT, Expand);
1720 setOperationAction(ISD::SELECT_CC, VT, Expand);
1721 }
1722 for (MVT VT : MVT::fp_valuetypes()) {
1723 setOperationAction(ISD::BR_CC, VT, Expand);
1724 setOperationAction(ISD::SELECT_CC, VT, Expand);
1725 }
1726 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1727
1728 //
1729 // Handling of vector operations.
1730 //
1731
1732 // Custom lower v4i16 load only. Let v4i16 store to be
1733 // promoted for now.
1734 promoteLdStType(MVT::v4i8, MVT::i32);
1735 promoteLdStType(MVT::v2i16, MVT::i32);
1736 promoteLdStType(MVT::v8i8, MVT::i64);
1737 promoteLdStType(MVT::v2i32, MVT::i64);
1738
1739 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1740 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1741 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1742 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1743
1744 // Set the action for vector operations to "expand", then override it with
1745 // either "custom" or "legal" for specific cases.
1746 static const unsigned VectExpOps[] = {
1747 // Integer arithmetic:
1748 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1749 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1750 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1751 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1752 // Logical/bit:
1753 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1754 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF,
1755 ISD::CTTZ_ZERO_UNDEF,
1756 // Floating point arithmetic/math functions:
1757 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1758 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1759 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1760 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1761 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1762 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1763 // Misc:
1764 ISD::SELECT, ISD::ConstantPool,
1765 // Vector:
1766 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1767 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1768 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1769 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1770 };
1771
1772 for (MVT VT : MVT::vector_valuetypes()) {
1773 for (unsigned VectExpOp : VectExpOps)
1774 setOperationAction(VectExpOp, VT, Expand);
1775
1776 // Expand all extended loads and truncating stores:
1777 for (MVT TargetVT : MVT::vector_valuetypes()) {
1778 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1779 setTruncStoreAction(VT, TargetVT, Expand);
1780 }
1781
1782 setOperationAction(ISD::SRA, VT, Custom);
1783 setOperationAction(ISD::SHL, VT, Custom);
1784 setOperationAction(ISD::SRL, VT, Custom);
1785 }
1786
1787 // Types natively supported:
1788 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1,
1789 MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v1i32,
1790 MVT::v2i32, MVT::v1i64}) {
1791 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1793 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1794 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1795 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1796 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1797
1798 setOperationAction(ISD::ADD, NativeVT, Legal);
1799 setOperationAction(ISD::SUB, NativeVT, Legal);
1800 setOperationAction(ISD::MUL, NativeVT, Legal);
1801 setOperationAction(ISD::AND, NativeVT, Legal);
1802 setOperationAction(ISD::OR, NativeVT, Legal);
1803 setOperationAction(ISD::XOR, NativeVT, Legal);
1804 }
1805
1806 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1807 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1808 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1809 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1810 if (UseHVX) {
1811 if (UseHVXSgl) {
1812 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
1813 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
1814 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
1815 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
1816 } else if (UseHVXDbl) {
1817 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
1818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
1819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
1820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
1821 } else {
1822 llvm_unreachable("Unrecognized HVX mode");
1823 }
1824 }
1825 // Subtarget-specific operation actions.
1826 //
1827 if (Subtarget.hasV5TOps()) {
1828 setOperationAction(ISD::FMA, MVT::f64, Expand);
1829 setOperationAction(ISD::FADD, MVT::f64, Expand);
1830 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1831 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1832
1833 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1834 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1835 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1836 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1837 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1838 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1839 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1840 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1841 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1842 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1843 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1844 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1845
1846 } else { // V4
1847 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1848 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
1849 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1850 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
1851 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1852 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1853 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1854 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1855 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1856
1857 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
1858 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
1859 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1860 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1861
1862 // Expand these operations for both f32 and f64:
1863 for (unsigned FPExpOpV4 :
1864 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
1865 setOperationAction(FPExpOpV4, MVT::f32, Expand);
1866 setOperationAction(FPExpOpV4, MVT::f64, Expand);
1867 }
1868
1869 for (ISD::CondCode FPExpCCV4 :
1870 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
1871 ISD::SETUO, ISD::SETO}) {
1872 setCondCodeAction(FPExpCCV4, MVT::f32, Expand);
1873 setCondCodeAction(FPExpCCV4, MVT::f64, Expand);
1874 }
1875 }
1876
1877 // Handling of indexed loads/stores: default is "expand".
1878 //
1879 for (MVT LSXTy : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
1880 setIndexedLoadAction(ISD::POST_INC, LSXTy, Legal);
1881 setIndexedStoreAction(ISD::POST_INC, LSXTy, Legal);
1882 }
1883
1884 if (UseHVXDbl) {
1885 for (MVT VT : {MVT::v128i8, MVT::v64i16, MVT::v32i32, MVT::v16i64}) {
1886 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
1887 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
1888 }
1889 }
1890
1891 computeRegisterProperties(&HRI);
1892
1893 //
1894 // Library calls for unsupported operations
1895 //
1896 bool FastMath = EnableFastMath;
1897
1898 setLibcallName(RTLIB::SDIV_I32, "__hexagon_divsi3");
1899 setLibcallName(RTLIB::SDIV_I64, "__hexagon_divdi3");
1900 setLibcallName(RTLIB::UDIV_I32, "__hexagon_udivsi3");
1901 setLibcallName(RTLIB::UDIV_I64, "__hexagon_udivdi3");
1902 setLibcallName(RTLIB::SREM_I32, "__hexagon_modsi3");
1903 setLibcallName(RTLIB::SREM_I64, "__hexagon_moddi3");
1904 setLibcallName(RTLIB::UREM_I32, "__hexagon_umodsi3");
1905 setLibcallName(RTLIB::UREM_I64, "__hexagon_umoddi3");
1906
1907 setLibcallName(RTLIB::SINTTOFP_I128_F64, "__hexagon_floattidf");
1908 setLibcallName(RTLIB::SINTTOFP_I128_F32, "__hexagon_floattisf");
1909 setLibcallName(RTLIB::FPTOUINT_F32_I128, "__hexagon_fixunssfti");
1910 setLibcallName(RTLIB::FPTOUINT_F64_I128, "__hexagon_fixunsdfti");
1911 setLibcallName(RTLIB::FPTOSINT_F32_I128, "__hexagon_fixsfti");
1912 setLibcallName(RTLIB::FPTOSINT_F64_I128, "__hexagon_fixdfti");
1913
1914 if (IsV4) {
1915 // Handle single-precision floating point operations on V4.
1916 if (FastMath) {
1917 setLibcallName(RTLIB::ADD_F32, "__hexagon_fast_addsf3");
1918 setLibcallName(RTLIB::SUB_F32, "__hexagon_fast_subsf3");
1919 setLibcallName(RTLIB::MUL_F32, "__hexagon_fast_mulsf3");
1920 setLibcallName(RTLIB::OGT_F32, "__hexagon_fast_gtsf2");
1921 setLibcallName(RTLIB::OLT_F32, "__hexagon_fast_ltsf2");
1922 // Double-precision compares.
1923 setLibcallName(RTLIB::OGT_F64, "__hexagon_fast_gtdf2");
1924 setLibcallName(RTLIB::OLT_F64, "__hexagon_fast_ltdf2");
1925 } else {
1926 setLibcallName(RTLIB::ADD_F32, "__hexagon_addsf3");
1927 setLibcallName(RTLIB::SUB_F32, "__hexagon_subsf3");
1928 setLibcallName(RTLIB::MUL_F32, "__hexagon_mulsf3");
1929 setLibcallName(RTLIB::OGT_F32, "__hexagon_gtsf2");
1930 setLibcallName(RTLIB::OLT_F32, "__hexagon_ltsf2");
1931 // Double-precision compares.
1932 setLibcallName(RTLIB::OGT_F64, "__hexagon_gtdf2");
1933 setLibcallName(RTLIB::OLT_F64, "__hexagon_ltdf2");
1934 }
1935 }
1936
1937 // This is the only fast library function for sqrtd.
1938 if (FastMath)
1939 setLibcallName(RTLIB::SQRT_F64, "__hexagon_fast2_sqrtdf2");
1940
1941 // Prefix is: nothing for "slow-math",
1942 // "fast2_" for V4 fast-math and V5+ fast-math double-precision
1943 // (actually, keep fast-math and fast-math2 separate for now)
1944 if (FastMath) {
1945 setLibcallName(RTLIB::ADD_F64, "__hexagon_fast_adddf3");
1946 setLibcallName(RTLIB::SUB_F64, "__hexagon_fast_subdf3");
1947 setLibcallName(RTLIB::MUL_F64, "__hexagon_fast_muldf3");
1948 setLibcallName(RTLIB::DIV_F64, "__hexagon_fast_divdf3");
1949 // Calling __hexagon_fast2_divsf3 with fast-math on V5 (ok).
1950 setLibcallName(RTLIB::DIV_F32, "__hexagon_fast_divsf3");
1951 } else {
1952 setLibcallName(RTLIB::ADD_F64, "__hexagon_adddf3");
1953 setLibcallName(RTLIB::SUB_F64, "__hexagon_subdf3");
1954 setLibcallName(RTLIB::MUL_F64, "__hexagon_muldf3");
1955 setLibcallName(RTLIB::DIV_F64, "__hexagon_divdf3");
1956 setLibcallName(RTLIB::DIV_F32, "__hexagon_divsf3");
1957 }
1958
1959 if (Subtarget.hasV5TOps()) {
1960 if (FastMath)
1961 setLibcallName(RTLIB::SQRT_F32, "__hexagon_fast2_sqrtf");
1962 else
1963 setLibcallName(RTLIB::SQRT_F32, "__hexagon_sqrtf");
1964 } else {
1965 // V4
1966 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__hexagon_floatsisf");
1967 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__hexagon_floatsidf");
1968 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__hexagon_floatdisf");
1969 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__hexagon_floatdidf");
1970 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__hexagon_floatunsisf");
1971 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__hexagon_floatunsidf");
1972 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__hexagon_floatundisf");
1973 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__hexagon_floatundidf");
1974 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__hexagon_fixunssfsi");
1975 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__hexagon_fixunssfdi");
1976 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__hexagon_fixunsdfsi");
1977 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__hexagon_fixunsdfdi");
1978 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__hexagon_fixsfsi");
1979 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__hexagon_fixsfdi");
1980 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__hexagon_fixdfsi");
1981 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__hexagon_fixdfdi");
1982 setLibcallName(RTLIB::FPEXT_F32_F64, "__hexagon_extendsfdf2");
1983 setLibcallName(RTLIB::FPROUND_F64_F32, "__hexagon_truncdfsf2");
1984 setLibcallName(RTLIB::OEQ_F32, "__hexagon_eqsf2");
1985 setLibcallName(RTLIB::OEQ_F64, "__hexagon_eqdf2");
1986 setLibcallName(RTLIB::OGE_F32, "__hexagon_gesf2");
1987 setLibcallName(RTLIB::OGE_F64, "__hexagon_gedf2");
1988 setLibcallName(RTLIB::OLE_F32, "__hexagon_lesf2");
1989 setLibcallName(RTLIB::OLE_F64, "__hexagon_ledf2");
1990 setLibcallName(RTLIB::UNE_F32, "__hexagon_nesf2");
1991 setLibcallName(RTLIB::UNE_F64, "__hexagon_nedf2");
1992 setLibcallName(RTLIB::UO_F32, "__hexagon_unordsf2");
1993 setLibcallName(RTLIB::UO_F64, "__hexagon_unorddf2");
1994 setLibcallName(RTLIB::O_F32, "__hexagon_unordsf2");
1995 setLibcallName(RTLIB::O_F64, "__hexagon_unorddf2");
1996 }
1997
1998 // These cause problems when the shift amount is non-constant.
1999 setLibcallName(RTLIB::SHL_I128, nullptr);
2000 setLibcallName(RTLIB::SRL_I128, nullptr);
2001 setLibcallName(RTLIB::SRA_I128, nullptr);
2002 }
2003
2004
getTargetNodeName(unsigned Opcode) const2005 const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
2006 switch ((HexagonISD::NodeType)Opcode) {
2007 case HexagonISD::ALLOCA: return "HexagonISD::ALLOCA";
2008 case HexagonISD::ARGEXTEND: return "HexagonISD::ARGEXTEND";
2009 case HexagonISD::AT_GOT: return "HexagonISD::AT_GOT";
2010 case HexagonISD::AT_PCREL: return "HexagonISD::AT_PCREL";
2011 case HexagonISD::BARRIER: return "HexagonISD::BARRIER";
2012 case HexagonISD::CALLR: return "HexagonISD::CALLR";
2013 case HexagonISD::CALLv3nr: return "HexagonISD::CALLv3nr";
2014 case HexagonISD::CALLv3: return "HexagonISD::CALLv3";
2015 case HexagonISD::COMBINE: return "HexagonISD::COMBINE";
2016 case HexagonISD::CONST32_GP: return "HexagonISD::CONST32_GP";
2017 case HexagonISD::CONST32: return "HexagonISD::CONST32";
2018 case HexagonISD::CP: return "HexagonISD::CP";
2019 case HexagonISD::DCFETCH: return "HexagonISD::DCFETCH";
2020 case HexagonISD::EH_RETURN: return "HexagonISD::EH_RETURN";
2021 case HexagonISD::EXTRACTU: return "HexagonISD::EXTRACTU";
2022 case HexagonISD::EXTRACTURP: return "HexagonISD::EXTRACTURP";
2023 case HexagonISD::FCONST32: return "HexagonISD::FCONST32";
2024 case HexagonISD::INSERT: return "HexagonISD::INSERT";
2025 case HexagonISD::INSERTRP: return "HexagonISD::INSERTRP";
2026 case HexagonISD::JT: return "HexagonISD::JT";
2027 case HexagonISD::PACKHL: return "HexagonISD::PACKHL";
2028 case HexagonISD::POPCOUNT: return "HexagonISD::POPCOUNT";
2029 case HexagonISD::RET_FLAG: return "HexagonISD::RET_FLAG";
2030 case HexagonISD::SHUFFEB: return "HexagonISD::SHUFFEB";
2031 case HexagonISD::SHUFFEH: return "HexagonISD::SHUFFEH";
2032 case HexagonISD::SHUFFOB: return "HexagonISD::SHUFFOB";
2033 case HexagonISD::SHUFFOH: return "HexagonISD::SHUFFOH";
2034 case HexagonISD::TC_RETURN: return "HexagonISD::TC_RETURN";
2035 case HexagonISD::VCMPBEQ: return "HexagonISD::VCMPBEQ";
2036 case HexagonISD::VCMPBGT: return "HexagonISD::VCMPBGT";
2037 case HexagonISD::VCMPBGTU: return "HexagonISD::VCMPBGTU";
2038 case HexagonISD::VCMPHEQ: return "HexagonISD::VCMPHEQ";
2039 case HexagonISD::VCMPHGT: return "HexagonISD::VCMPHGT";
2040 case HexagonISD::VCMPHGTU: return "HexagonISD::VCMPHGTU";
2041 case HexagonISD::VCMPWEQ: return "HexagonISD::VCMPWEQ";
2042 case HexagonISD::VCMPWGT: return "HexagonISD::VCMPWGT";
2043 case HexagonISD::VCMPWGTU: return "HexagonISD::VCMPWGTU";
2044 case HexagonISD::VCOMBINE: return "HexagonISD::VCOMBINE";
2045 case HexagonISD::VSHLH: return "HexagonISD::VSHLH";
2046 case HexagonISD::VSHLW: return "HexagonISD::VSHLW";
2047 case HexagonISD::VSPLATB: return "HexagonISD::VSPLTB";
2048 case HexagonISD::VSPLATH: return "HexagonISD::VSPLATH";
2049 case HexagonISD::VSRAH: return "HexagonISD::VSRAH";
2050 case HexagonISD::VSRAW: return "HexagonISD::VSRAW";
2051 case HexagonISD::VSRLH: return "HexagonISD::VSRLH";
2052 case HexagonISD::VSRLW: return "HexagonISD::VSRLW";
2053 case HexagonISD::VSXTBH: return "HexagonISD::VSXTBH";
2054 case HexagonISD::VSXTBW: return "HexagonISD::VSXTBW";
2055 case HexagonISD::OP_END: break;
2056 }
2057 return nullptr;
2058 }
2059
isTruncateFree(Type * Ty1,Type * Ty2) const2060 bool HexagonTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
2061 EVT MTy1 = EVT::getEVT(Ty1);
2062 EVT MTy2 = EVT::getEVT(Ty2);
2063 if (!MTy1.isSimple() || !MTy2.isSimple())
2064 return false;
2065 return (MTy1.getSimpleVT() == MVT::i64) && (MTy2.getSimpleVT() == MVT::i32);
2066 }
2067
isTruncateFree(EVT VT1,EVT VT2) const2068 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
2069 if (!VT1.isSimple() || !VT2.isSimple())
2070 return false;
2071 return (VT1.getSimpleVT() == MVT::i64) && (VT2.getSimpleVT() == MVT::i32);
2072 }
2073
2074 // shouldExpandBuildVectorWithShuffles
2075 // Should we expand the build vector with shuffles?
2076 bool
shouldExpandBuildVectorWithShuffles(EVT VT,unsigned DefinedValues) const2077 HexagonTargetLowering::shouldExpandBuildVectorWithShuffles(EVT VT,
2078 unsigned DefinedValues) const {
2079
2080 // Hexagon vector shuffle operates on element sizes of bytes or halfwords
2081 EVT EltVT = VT.getVectorElementType();
2082 int EltBits = EltVT.getSizeInBits();
2083 if ((EltBits != 8) && (EltBits != 16))
2084 return false;
2085
2086 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
2087 }
2088
2089 // LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3). V1 and
2090 // V2 are the two vectors to select data from, V3 is the permutation.
LowerVECTOR_SHUFFLE(SDValue Op,SelectionDAG & DAG)2091 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2092 const ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op);
2093 SDValue V1 = Op.getOperand(0);
2094 SDValue V2 = Op.getOperand(1);
2095 SDLoc dl(Op);
2096 EVT VT = Op.getValueType();
2097
2098 if (V2.getOpcode() == ISD::UNDEF)
2099 V2 = V1;
2100
2101 if (SVN->isSplat()) {
2102 int Lane = SVN->getSplatIndex();
2103 if (Lane == -1) Lane = 0;
2104
2105 // Test if V1 is a SCALAR_TO_VECTOR.
2106 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2107 return createSplat(DAG, dl, VT, V1.getOperand(0));
2108
2109 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
2110 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
2111 // reaches it).
2112 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2113 !isa<ConstantSDNode>(V1.getOperand(0))) {
2114 bool IsScalarToVector = true;
2115 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
2116 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
2117 IsScalarToVector = false;
2118 break;
2119 }
2120 if (IsScalarToVector)
2121 return createSplat(DAG, dl, VT, V1.getOperand(0));
2122 }
2123 return createSplat(DAG, dl, VT, DAG.getConstant(Lane, dl, MVT::i32));
2124 }
2125
2126 // FIXME: We need to support more general vector shuffles. See
2127 // below the comment from the ARM backend that deals in the general
2128 // case with the vector shuffles. For now, let expand handle these.
2129 return SDValue();
2130
2131 // If the shuffle is not directly supported and it has 4 elements, use
2132 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2133 }
2134
2135 // If BUILD_VECTOR has same base element repeated several times,
2136 // report true.
isCommonSplatElement(BuildVectorSDNode * BVN)2137 static bool isCommonSplatElement(BuildVectorSDNode *BVN) {
2138 unsigned NElts = BVN->getNumOperands();
2139 SDValue V0 = BVN->getOperand(0);
2140
2141 for (unsigned i = 1, e = NElts; i != e; ++i) {
2142 if (BVN->getOperand(i) != V0)
2143 return false;
2144 }
2145 return true;
2146 }
2147
2148 // LowerVECTOR_SHIFT - Lower a vector shift. Try to convert
2149 // <VT> = SHL/SRA/SRL <VT> by <VT> to Hexagon specific
2150 // <VT> = SHL/SRA/SRL <VT> by <IT/i32>.
LowerVECTOR_SHIFT(SDValue Op,SelectionDAG & DAG)2151 static SDValue LowerVECTOR_SHIFT(SDValue Op, SelectionDAG &DAG) {
2152 BuildVectorSDNode *BVN = 0;
2153 SDValue V1 = Op.getOperand(0);
2154 SDValue V2 = Op.getOperand(1);
2155 SDValue V3;
2156 SDLoc dl(Op);
2157 EVT VT = Op.getValueType();
2158
2159 if ((BVN = dyn_cast<BuildVectorSDNode>(V1.getNode())) &&
2160 isCommonSplatElement(BVN))
2161 V3 = V2;
2162 else if ((BVN = dyn_cast<BuildVectorSDNode>(V2.getNode())) &&
2163 isCommonSplatElement(BVN))
2164 V3 = V1;
2165 else
2166 return SDValue();
2167
2168 SDValue CommonSplat = BVN->getOperand(0);
2169 SDValue Result;
2170
2171 if (VT.getSimpleVT() == MVT::v4i16) {
2172 switch (Op.getOpcode()) {
2173 case ISD::SRA:
2174 Result = DAG.getNode(HexagonISD::VSRAH, dl, VT, V3, CommonSplat);
2175 break;
2176 case ISD::SHL:
2177 Result = DAG.getNode(HexagonISD::VSHLH, dl, VT, V3, CommonSplat);
2178 break;
2179 case ISD::SRL:
2180 Result = DAG.getNode(HexagonISD::VSRLH, dl, VT, V3, CommonSplat);
2181 break;
2182 default:
2183 return SDValue();
2184 }
2185 } else if (VT.getSimpleVT() == MVT::v2i32) {
2186 switch (Op.getOpcode()) {
2187 case ISD::SRA:
2188 Result = DAG.getNode(HexagonISD::VSRAW, dl, VT, V3, CommonSplat);
2189 break;
2190 case ISD::SHL:
2191 Result = DAG.getNode(HexagonISD::VSHLW, dl, VT, V3, CommonSplat);
2192 break;
2193 case ISD::SRL:
2194 Result = DAG.getNode(HexagonISD::VSRLW, dl, VT, V3, CommonSplat);
2195 break;
2196 default:
2197 return SDValue();
2198 }
2199 } else {
2200 return SDValue();
2201 }
2202
2203 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2204 }
2205
2206 SDValue
LowerBUILD_VECTOR(SDValue Op,SelectionDAG & DAG) const2207 HexagonTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
2208 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2209 SDLoc dl(Op);
2210 EVT VT = Op.getValueType();
2211
2212 unsigned Size = VT.getSizeInBits();
2213
2214 // Only handle vectors of 64 bits or shorter.
2215 if (Size > 64)
2216 return SDValue();
2217
2218 APInt APSplatBits, APSplatUndef;
2219 unsigned SplatBitSize;
2220 bool HasAnyUndefs;
2221 unsigned NElts = BVN->getNumOperands();
2222
2223 // Try to generate a SPLAT instruction.
2224 if ((VT.getSimpleVT() == MVT::v4i8 || VT.getSimpleVT() == MVT::v4i16) &&
2225 (BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
2226 HasAnyUndefs, 0, true) && SplatBitSize <= 16)) {
2227 unsigned SplatBits = APSplatBits.getZExtValue();
2228 int32_t SextVal = ((int32_t) (SplatBits << (32 - SplatBitSize)) >>
2229 (32 - SplatBitSize));
2230 return createSplat(DAG, dl, VT, DAG.getConstant(SextVal, dl, MVT::i32));
2231 }
2232
2233 // Try to generate COMBINE to build v2i32 vectors.
2234 if (VT.getSimpleVT() == MVT::v2i32) {
2235 SDValue V0 = BVN->getOperand(0);
2236 SDValue V1 = BVN->getOperand(1);
2237
2238 if (V0.getOpcode() == ISD::UNDEF)
2239 V0 = DAG.getConstant(0, dl, MVT::i32);
2240 if (V1.getOpcode() == ISD::UNDEF)
2241 V1 = DAG.getConstant(0, dl, MVT::i32);
2242
2243 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
2244 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
2245 // If the element isn't a constant, it is in a register:
2246 // generate a COMBINE Register Register instruction.
2247 if (!C0 || !C1)
2248 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2249
2250 // If one of the operands is an 8 bit integer constant, generate
2251 // a COMBINE Immediate Immediate instruction.
2252 if (isInt<8>(C0->getSExtValue()) ||
2253 isInt<8>(C1->getSExtValue()))
2254 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0);
2255 }
2256
2257 // Try to generate a S2_packhl to build v2i16 vectors.
2258 if (VT.getSimpleVT() == MVT::v2i16) {
2259 for (unsigned i = 0, e = NElts; i != e; ++i) {
2260 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
2261 continue;
2262 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
2263 // If the element isn't a constant, it is in a register:
2264 // generate a S2_packhl instruction.
2265 if (!Cst) {
2266 SDValue pack = DAG.getNode(HexagonISD::PACKHL, dl, MVT::v4i16,
2267 BVN->getOperand(1), BVN->getOperand(0));
2268
2269 return DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::v2i16,
2270 pack);
2271 }
2272 }
2273 }
2274
2275 // In the general case, generate a CONST32 or a CONST64 for constant vectors,
2276 // and insert_vector_elt for all the other cases.
2277 uint64_t Res = 0;
2278 unsigned EltSize = Size / NElts;
2279 SDValue ConstVal;
2280 uint64_t Mask = ~uint64_t(0ULL) >> (64 - EltSize);
2281 bool HasNonConstantElements = false;
2282
2283 for (unsigned i = 0, e = NElts; i != e; ++i) {
2284 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon's
2285 // combine, const64, etc. are Big Endian.
2286 unsigned OpIdx = NElts - i - 1;
2287 SDValue Operand = BVN->getOperand(OpIdx);
2288 if (Operand.getOpcode() == ISD::UNDEF)
2289 continue;
2290
2291 int64_t Val = 0;
2292 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
2293 Val = Cst->getSExtValue();
2294 else
2295 HasNonConstantElements = true;
2296
2297 Val &= Mask;
2298 Res = (Res << EltSize) | Val;
2299 }
2300
2301 if (Size == 64)
2302 ConstVal = DAG.getConstant(Res, dl, MVT::i64);
2303 else
2304 ConstVal = DAG.getConstant(Res, dl, MVT::i32);
2305
2306 // When there are non constant operands, add them with INSERT_VECTOR_ELT to
2307 // ConstVal, the constant part of the vector.
2308 if (HasNonConstantElements) {
2309 EVT EltVT = VT.getVectorElementType();
2310 SDValue Width = DAG.getConstant(EltVT.getSizeInBits(), dl, MVT::i64);
2311 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2312 DAG.getConstant(32, dl, MVT::i64));
2313
2314 for (unsigned i = 0, e = NElts; i != e; ++i) {
2315 // LLVM's BUILD_VECTOR operands are in Little Endian mode, whereas Hexagon
2316 // is Big Endian.
2317 unsigned OpIdx = NElts - i - 1;
2318 SDValue Operand = BVN->getOperand(OpIdx);
2319 if (isa<ConstantSDNode>(Operand))
2320 // This operand is already in ConstVal.
2321 continue;
2322
2323 if (VT.getSizeInBits() == 64 &&
2324 Operand.getValueType().getSizeInBits() == 32) {
2325 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2326 Operand = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Operand);
2327 }
2328
2329 SDValue Idx = DAG.getConstant(OpIdx, dl, MVT::i64);
2330 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2331 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2332 const SDValue Ops[] = {ConstVal, Operand, Combined};
2333
2334 if (VT.getSizeInBits() == 32)
2335 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2336 else
2337 ConstVal = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2338 }
2339 }
2340
2341 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2342 }
2343
2344 SDValue
LowerCONCAT_VECTORS(SDValue Op,SelectionDAG & DAG) const2345 HexagonTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
2346 SelectionDAG &DAG) const {
2347 SDLoc dl(Op);
2348 bool UseHVX = Subtarget.useHVXOps();
2349 EVT VT = Op.getValueType();
2350 unsigned NElts = Op.getNumOperands();
2351 SDValue Vec0 = Op.getOperand(0);
2352 EVT VecVT = Vec0.getValueType();
2353 unsigned Width = VecVT.getSizeInBits();
2354
2355 if (NElts == 2) {
2356 MVT ST = VecVT.getSimpleVT();
2357 // We are trying to concat two v2i16 to a single v4i16, or two v4i8
2358 // into a single v8i8.
2359 if (ST == MVT::v2i16 || ST == MVT::v4i8)
2360 return DAG.getNode(HexagonISD::COMBINE, dl, VT, Op.getOperand(1), Vec0);
2361
2362 if (UseHVX) {
2363 assert((Width == 64*8 && Subtarget.useHVXSglOps()) ||
2364 (Width == 128*8 && Subtarget.useHVXDblOps()));
2365 SDValue Vec1 = Op.getOperand(1);
2366 MVT OpTy = Subtarget.useHVXSglOps() ? MVT::v16i32 : MVT::v32i32;
2367 MVT ReTy = Subtarget.useHVXSglOps() ? MVT::v32i32 : MVT::v64i32;
2368 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2369 SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2370 SDValue VC = DAG.getNode(HexagonISD::VCOMBINE, dl, ReTy, B1, B0);
2371 return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2372 }
2373 }
2374
2375 if (VT.getSizeInBits() != 32 && VT.getSizeInBits() != 64)
2376 return SDValue();
2377
2378 SDValue C0 = DAG.getConstant(0, dl, MVT::i64);
2379 SDValue C32 = DAG.getConstant(32, dl, MVT::i64);
2380 SDValue W = DAG.getConstant(Width, dl, MVT::i64);
2381 // Create the "width" part of the argument to insert_rp/insertp_rp.
2382 SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2383 SDValue V = C0;
2384
2385 for (unsigned i = 0, e = NElts; i != e; ++i) {
2386 unsigned N = NElts-i-1;
2387 SDValue OpN = Op.getOperand(N);
2388
2389 if (VT.getSizeInBits() == 64 && OpN.getValueType().getSizeInBits() == 32) {
2390 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2391 OpN = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, OpN);
2392 }
2393 SDValue Idx = DAG.getConstant(N, dl, MVT::i64);
2394 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2395 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2396 if (VT.getSizeInBits() == 32)
2397 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, {V, OpN, Or});
2398 else
2399 V = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, {V, OpN, Or});
2400 }
2401
2402 return DAG.getNode(ISD::BITCAST, dl, VT, V);
2403 }
2404
2405 SDValue
LowerEXTRACT_VECTOR(SDValue Op,SelectionDAG & DAG) const2406 HexagonTargetLowering::LowerEXTRACT_VECTOR(SDValue Op,
2407 SelectionDAG &DAG) const {
2408 EVT VT = Op.getValueType();
2409 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2410 SDLoc dl(Op);
2411 SDValue Idx = Op.getOperand(1);
2412 SDValue Vec = Op.getOperand(0);
2413 EVT VecVT = Vec.getValueType();
2414 EVT EltVT = VecVT.getVectorElementType();
2415 int EltSize = EltVT.getSizeInBits();
2416 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2417 EltSize : VTN * EltSize, dl, MVT::i64);
2418
2419 // Constant element number.
2420 if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
2421 uint64_t X = CI->getZExtValue();
2422 SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
2423 const SDValue Ops[] = {Vec, Width, Offset};
2424
2425 ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
2426 assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
2427
2428 SDValue N;
2429 MVT SVT = VecVT.getSimpleVT();
2430 uint64_t W = CW->getZExtValue();
2431
2432 if (W == 32) {
2433 // Translate this node into EXTRACT_SUBREG.
2434 unsigned Subreg = (X == 0) ? Hexagon::subreg_loreg : 0;
2435
2436 if (X == 0)
2437 Subreg = Hexagon::subreg_loreg;
2438 else if (SVT == MVT::v2i32 && X == 1)
2439 Subreg = Hexagon::subreg_hireg;
2440 else if (SVT == MVT::v4i16 && X == 2)
2441 Subreg = Hexagon::subreg_hireg;
2442 else if (SVT == MVT::v8i8 && X == 4)
2443 Subreg = Hexagon::subreg_hireg;
2444 else
2445 llvm_unreachable("Bad offset");
2446 N = DAG.getTargetExtractSubreg(Subreg, dl, MVT::i32, Vec);
2447
2448 } else if (VecVT.getSizeInBits() == 32) {
2449 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i32, Ops);
2450 } else {
2451 N = DAG.getNode(HexagonISD::EXTRACTU, dl, MVT::i64, Ops);
2452 if (VT.getSizeInBits() == 32)
2453 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2454 }
2455
2456 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2457 }
2458
2459 // Variable element number.
2460 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2461 DAG.getConstant(EltSize, dl, MVT::i32));
2462 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2463 DAG.getConstant(32, dl, MVT::i64));
2464 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2465
2466 const SDValue Ops[] = {Vec, Combined};
2467
2468 SDValue N;
2469 if (VecVT.getSizeInBits() == 32) {
2470 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i32, Ops);
2471 } else {
2472 N = DAG.getNode(HexagonISD::EXTRACTURP, dl, MVT::i64, Ops);
2473 if (VT.getSizeInBits() == 32)
2474 N = DAG.getTargetExtractSubreg(Hexagon::subreg_loreg, dl, MVT::i32, N);
2475 }
2476 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2477 }
2478
2479 SDValue
LowerINSERT_VECTOR(SDValue Op,SelectionDAG & DAG) const2480 HexagonTargetLowering::LowerINSERT_VECTOR(SDValue Op,
2481 SelectionDAG &DAG) const {
2482 EVT VT = Op.getValueType();
2483 int VTN = VT.isVector() ? VT.getVectorNumElements() : 1;
2484 SDLoc dl(Op);
2485 SDValue Vec = Op.getOperand(0);
2486 SDValue Val = Op.getOperand(1);
2487 SDValue Idx = Op.getOperand(2);
2488 EVT VecVT = Vec.getValueType();
2489 EVT EltVT = VecVT.getVectorElementType();
2490 int EltSize = EltVT.getSizeInBits();
2491 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2492 EltSize : VTN * EltSize, dl, MVT::i64);
2493
2494 if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
2495 SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
2496 const SDValue Ops[] = {Vec, Val, Width, Offset};
2497
2498 SDValue N;
2499 if (VT.getSizeInBits() == 32)
2500 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i32, Ops);
2501 else
2502 N = DAG.getNode(HexagonISD::INSERT, dl, MVT::i64, Ops);
2503
2504 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2505 }
2506
2507 // Variable element number.
2508 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2509 DAG.getConstant(EltSize, dl, MVT::i32));
2510 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2511 DAG.getConstant(32, dl, MVT::i64));
2512 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2513
2514 if (VT.getSizeInBits() == 64 &&
2515 Val.getValueType().getSizeInBits() == 32) {
2516 SDValue C = DAG.getConstant(0, dl, MVT::i32);
2517 Val = DAG.getNode(HexagonISD::COMBINE, dl, VT, C, Val);
2518 }
2519
2520 const SDValue Ops[] = {Vec, Val, Combined};
2521
2522 SDValue N;
2523 if (VT.getSizeInBits() == 32)
2524 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i32, Ops);
2525 else
2526 N = DAG.getNode(HexagonISD::INSERTRP, dl, MVT::i64, Ops);
2527
2528 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2529 }
2530
2531 bool
allowTruncateForTailCall(Type * Ty1,Type * Ty2) const2532 HexagonTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
2533 // Assuming the caller does not have either a signext or zeroext modifier, and
2534 // only one value is accepted, any reasonable truncation is allowed.
2535 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
2536 return false;
2537
2538 // FIXME: in principle up to 64-bit could be made safe, but it would be very
2539 // fragile at the moment: any support for multiple value returns would be
2540 // liable to disallow tail calls involving i64 -> iN truncation in many cases.
2541 return Ty1->getPrimitiveSizeInBits() <= 32;
2542 }
2543
2544 SDValue
LowerEH_RETURN(SDValue Op,SelectionDAG & DAG) const2545 HexagonTargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
2546 SDValue Chain = Op.getOperand(0);
2547 SDValue Offset = Op.getOperand(1);
2548 SDValue Handler = Op.getOperand(2);
2549 SDLoc dl(Op);
2550 auto PtrVT = getPointerTy(DAG.getDataLayout());
2551
2552 // Mark function as containing a call to EH_RETURN.
2553 HexagonMachineFunctionInfo *FuncInfo =
2554 DAG.getMachineFunction().getInfo<HexagonMachineFunctionInfo>();
2555 FuncInfo->setHasEHReturn();
2556
2557 unsigned OffsetReg = Hexagon::R28;
2558
2559 SDValue StoreAddr =
2560 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2561 DAG.getIntPtrConstant(4, dl));
2562 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),
2563 false, false, 0);
2564 Chain = DAG.getCopyToReg(Chain, dl, OffsetReg, Offset);
2565
2566 // Not needed we already use it as explict input to EH_RETURN.
2567 // MF.getRegInfo().addLiveOut(OffsetReg);
2568
2569 return DAG.getNode(HexagonISD::EH_RETURN, dl, MVT::Other, Chain);
2570 }
2571
2572 SDValue
LowerOperation(SDValue Op,SelectionDAG & DAG) const2573 HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2574 unsigned Opc = Op.getOpcode();
2575 switch (Opc) {
2576 default:
2577 #ifndef NDEBUG
2578 Op.getNode()->dumpr(&DAG);
2579 if (Opc > HexagonISD::OP_BEGIN && Opc < HexagonISD::OP_END)
2580 errs() << "Check for a non-legal type in this operation\n";
2581 #endif
2582 llvm_unreachable("Should not custom lower this!");
2583 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2584 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2585 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2586 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2587 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2588 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2589 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2590 case ISD::SRA:
2591 case ISD::SHL:
2592 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2593 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2594 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2595 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2596 // Frame & Return address. Currently unimplemented.
2597 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2598 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2599 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2600 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2601 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2602 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2603 case ISD::VASTART: return LowerVASTART(Op, DAG);
2604 // Custom lower some vector loads.
2605 case ISD::LOAD: return LowerLOAD(Op, DAG);
2606 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2607 case ISD::SETCC: return LowerSETCC(Op, DAG);
2608 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2609 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2610 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2611 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2612 }
2613 }
2614
2615 /// Returns relocation base for the given PIC jumptable.
2616 SDValue
getPICJumpTableRelocBase(SDValue Table,SelectionDAG & DAG) const2617 HexagonTargetLowering::getPICJumpTableRelocBase(SDValue Table,
2618 SelectionDAG &DAG) const {
2619 int Idx = cast<JumpTableSDNode>(Table)->getIndex();
2620 EVT VT = Table.getValueType();
2621 SDValue T = DAG.getTargetJumpTable(Idx, VT, HexagonII::MO_PCREL);
2622 return DAG.getNode(HexagonISD::AT_PCREL, SDLoc(Table), VT, T);
2623 }
2624
2625 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const2626 HexagonTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2627 MachineBasicBlock *BB)
2628 const {
2629 switch (MI->getOpcode()) {
2630 case Hexagon::ALLOCA: {
2631 MachineFunction *MF = BB->getParent();
2632 auto *FuncInfo = MF->getInfo<HexagonMachineFunctionInfo>();
2633 FuncInfo->addAllocaAdjustInst(MI);
2634 return BB;
2635 }
2636 default: llvm_unreachable("Unexpected instr type to insert");
2637 } // switch
2638 }
2639
2640 //===----------------------------------------------------------------------===//
2641 // Inline Assembly Support
2642 //===----------------------------------------------------------------------===//
2643
2644 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,StringRef Constraint,MVT VT) const2645 HexagonTargetLowering::getRegForInlineAsmConstraint(
2646 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
2647 bool UseHVX = Subtarget.useHVXOps(), UseHVXDbl = Subtarget.useHVXDblOps();
2648
2649 if (Constraint.size() == 1) {
2650 switch (Constraint[0]) {
2651 case 'r': // R0-R31
2652 switch (VT.SimpleTy) {
2653 default:
2654 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2655 case MVT::i32:
2656 case MVT::i16:
2657 case MVT::i8:
2658 case MVT::f32:
2659 return std::make_pair(0U, &Hexagon::IntRegsRegClass);
2660 case MVT::i64:
2661 case MVT::f64:
2662 return std::make_pair(0U, &Hexagon::DoubleRegsRegClass);
2663 }
2664 case 'q': // q0-q3
2665 switch (VT.SimpleTy) {
2666 default:
2667 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2668 case MVT::v1024i1:
2669 case MVT::v512i1:
2670 case MVT::v32i16:
2671 case MVT::v16i32:
2672 case MVT::v64i8:
2673 case MVT::v8i64:
2674 return std::make_pair(0U, &Hexagon::VecPredRegsRegClass);
2675 }
2676 case 'v': // V0-V31
2677 switch (VT.SimpleTy) {
2678 default:
2679 llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type");
2680 case MVT::v16i32:
2681 case MVT::v32i16:
2682 case MVT::v64i8:
2683 case MVT::v8i64:
2684 return std::make_pair(0U, &Hexagon::VectorRegsRegClass);
2685 case MVT::v32i32:
2686 case MVT::v64i16:
2687 case MVT::v16i64:
2688 case MVT::v128i8:
2689 if (Subtarget.hasV60TOps() && UseHVX && UseHVXDbl)
2690 return std::make_pair(0U, &Hexagon::VectorRegs128BRegClass);
2691 else
2692 return std::make_pair(0U, &Hexagon::VecDblRegsRegClass);
2693 case MVT::v256i8:
2694 case MVT::v128i16:
2695 case MVT::v64i32:
2696 case MVT::v32i64:
2697 return std::make_pair(0U, &Hexagon::VecDblRegs128BRegClass);
2698 }
2699
2700 default:
2701 llvm_unreachable("Unknown asm register class");
2702 }
2703 }
2704
2705 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
2706 }
2707
2708 /// isFPImmLegal - Returns true if the target can instruction select the
2709 /// specified FP immediate natively. If false, the legalizer will
2710 /// materialize the FP immediate as a load from a constant pool.
isFPImmLegal(const APFloat & Imm,EVT VT) const2711 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
2712 return Subtarget.hasV5TOps();
2713 }
2714
2715 /// isLegalAddressingMode - Return true if the addressing mode represented by
2716 /// AM is legal for this target, for a load/store of the specified type.
isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS) const2717 bool HexagonTargetLowering::isLegalAddressingMode(const DataLayout &DL,
2718 const AddrMode &AM, Type *Ty,
2719 unsigned AS) const {
2720 // Allows a signed-extended 11-bit immediate field.
2721 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1)
2722 return false;
2723
2724 // No global is ever allowed as a base.
2725 if (AM.BaseGV)
2726 return false;
2727
2728 int Scale = AM.Scale;
2729 if (Scale < 0) Scale = -Scale;
2730 switch (Scale) {
2731 case 0: // No scale reg, "r+i", "r", or just "i".
2732 break;
2733 default: // No scaled addressing mode.
2734 return false;
2735 }
2736 return true;
2737 }
2738
2739 /// Return true if folding a constant offset with the given GlobalAddress is
2740 /// legal. It is frequently not legal in PIC relocation models.
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const2741 bool HexagonTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA)
2742 const {
2743 return HTM.getRelocationModel() == Reloc::Static;
2744 }
2745
2746
2747 /// isLegalICmpImmediate - Return true if the specified immediate is legal
2748 /// icmp immediate, that is the target has icmp instructions which can compare
2749 /// a register against the immediate without having to materialize the
2750 /// immediate into a register.
isLegalICmpImmediate(int64_t Imm) const2751 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
2752 return Imm >= -512 && Imm <= 511;
2753 }
2754
2755 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2756 /// for tail call optimization. Targets which want to do tail call
2757 /// optimization should implement this function.
IsEligibleForTailCallOptimization(SDValue Callee,CallingConv::ID CalleeCC,bool isVarArg,bool isCalleeStructRet,bool isCallerStructRet,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SmallVectorImpl<ISD::InputArg> & Ins,SelectionDAG & DAG) const2758 bool HexagonTargetLowering::IsEligibleForTailCallOptimization(
2759 SDValue Callee,
2760 CallingConv::ID CalleeCC,
2761 bool isVarArg,
2762 bool isCalleeStructRet,
2763 bool isCallerStructRet,
2764 const SmallVectorImpl<ISD::OutputArg> &Outs,
2765 const SmallVectorImpl<SDValue> &OutVals,
2766 const SmallVectorImpl<ISD::InputArg> &Ins,
2767 SelectionDAG& DAG) const {
2768 const Function *CallerF = DAG.getMachineFunction().getFunction();
2769 CallingConv::ID CallerCC = CallerF->getCallingConv();
2770 bool CCMatch = CallerCC == CalleeCC;
2771
2772 // ***************************************************************************
2773 // Look for obvious safe cases to perform tail call optimization that do not
2774 // require ABI changes.
2775 // ***************************************************************************
2776
2777 // If this is a tail call via a function pointer, then don't do it!
2778 if (!(isa<GlobalAddressSDNode>(Callee)) &&
2779 !(isa<ExternalSymbolSDNode>(Callee))) {
2780 return false;
2781 }
2782
2783 // Do not optimize if the calling conventions do not match.
2784 if (!CCMatch)
2785 return false;
2786
2787 // Do not tail call optimize vararg calls.
2788 if (isVarArg)
2789 return false;
2790
2791 // Also avoid tail call optimization if either caller or callee uses struct
2792 // return semantics.
2793 if (isCalleeStructRet || isCallerStructRet)
2794 return false;
2795
2796 // In addition to the cases above, we also disable Tail Call Optimization if
2797 // the calling convention code that at least one outgoing argument needs to
2798 // go on the stack. We cannot check that here because at this point that
2799 // information is not available.
2800 return true;
2801 }
2802
2803 // Return true when the given node fits in a positive half word.
isPositiveHalfWord(SDNode * N)2804 bool llvm::isPositiveHalfWord(SDNode *N) {
2805 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
2806 if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
2807 return true;
2808
2809 switch (N->getOpcode()) {
2810 default:
2811 return false;
2812 case ISD::SIGN_EXTEND_INREG:
2813 return true;
2814 }
2815 }
2816
2817 std::pair<const TargetRegisterClass*, uint8_t>
findRepresentativeClass(const TargetRegisterInfo * TRI,MVT VT) const2818 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2819 MVT VT) const {
2820 const TargetRegisterClass *RRC = nullptr;
2821
2822 uint8_t Cost = 1;
2823 switch (VT.SimpleTy) {
2824 default:
2825 return TargetLowering::findRepresentativeClass(TRI, VT);
2826 case MVT::v64i8:
2827 case MVT::v32i16:
2828 case MVT::v16i32:
2829 case MVT::v8i64:
2830 RRC = &Hexagon::VectorRegsRegClass;
2831 break;
2832 case MVT::v128i8:
2833 case MVT::v64i16:
2834 case MVT::v32i32:
2835 case MVT::v16i64:
2836 if (Subtarget.hasV60TOps() && Subtarget.useHVXOps() &&
2837 Subtarget.useHVXDblOps())
2838 RRC = &Hexagon::VectorRegs128BRegClass;
2839 else
2840 RRC = &Hexagon::VecDblRegsRegClass;
2841 break;
2842 case MVT::v256i8:
2843 case MVT::v128i16:
2844 case MVT::v64i32:
2845 case MVT::v32i64:
2846 RRC = &Hexagon::VecDblRegs128BRegClass;
2847 break;
2848 }
2849 return std::make_pair(RRC, Cost);
2850 }
2851
emitLoadLinked(IRBuilder<> & Builder,Value * Addr,AtomicOrdering Ord) const2852 Value *HexagonTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
2853 AtomicOrdering Ord) const {
2854 BasicBlock *BB = Builder.GetInsertBlock();
2855 Module *M = BB->getParent()->getParent();
2856 Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
2857 unsigned SZ = Ty->getPrimitiveSizeInBits();
2858 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
2859 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
2860 : Intrinsic::hexagon_L4_loadd_locked;
2861 Value *Fn = Intrinsic::getDeclaration(M, IntID);
2862 return Builder.CreateCall(Fn, Addr, "larx");
2863 }
2864
2865 /// Perform a store-conditional operation to Addr. Return the status of the
2866 /// store. This should be 0 if the store succeeded, non-zero otherwise.
emitStoreConditional(IRBuilder<> & Builder,Value * Val,Value * Addr,AtomicOrdering Ord) const2867 Value *HexagonTargetLowering::emitStoreConditional(IRBuilder<> &Builder,
2868 Value *Val, Value *Addr, AtomicOrdering Ord) const {
2869 BasicBlock *BB = Builder.GetInsertBlock();
2870 Module *M = BB->getParent()->getParent();
2871 Type *Ty = Val->getType();
2872 unsigned SZ = Ty->getPrimitiveSizeInBits();
2873 assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
2874 Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
2875 : Intrinsic::hexagon_S4_stored_locked;
2876 Value *Fn = Intrinsic::getDeclaration(M, IntID);
2877 Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
2878 Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
2879 Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
2880 return Ext;
2881 }
2882
2883 TargetLowering::AtomicExpansionKind
shouldExpandAtomicLoadInIR(LoadInst * LI) const2884 HexagonTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
2885 // Do not expand loads and stores that don't exceed 64 bits.
2886 return LI->getType()->getPrimitiveSizeInBits() > 64
2887 ? AtomicExpansionKind::LLOnly
2888 : AtomicExpansionKind::None;
2889 }
2890
shouldExpandAtomicStoreInIR(StoreInst * SI) const2891 bool HexagonTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
2892 // Do not expand loads and stores that don't exceed 64 bits.
2893 return SI->getValueOperand()->getType()->getPrimitiveSizeInBits() > 64;
2894 }
2895