1//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes microMIPS32r6 instruction formats.
11//
12//===----------------------------------------------------------------------===//
13
14class MMR6Arch<string opstr> {
15  string Arch = "micromipsr6";
16  string BaseOpcode = opstr;
17}
18
19// Class used for microMIPS32r6 and microMIPS64r6 instructions.
20class MicroMipsR6Inst16 : PredicateControl {
21  string DecoderNamespace = "MicroMipsR6";
22  let InsnPredicates = [HasMicroMips32r6];
23}
24
25class BC16_FM_MM16R6 {
26  bits<10> offset;
27
28  bits<16> Inst;
29
30  let Inst{15-10} = 0x33;
31  let Inst{9-0}   = offset;
32}
33
34class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
35  bits<3> rs;
36  bits<7> offset;
37
38  bits<16> Inst;
39
40  let Inst{15-10} = op;
41  let Inst{9-7}   = rs;
42  let Inst{6-0}   = offset;
43}
44
45class POOL16C_JALRC_FM_MM16R6<bits<5> op> {
46  bits<5> rs;
47
48  bits<16> Inst;
49
50  let Inst{15-10} = 0x11;
51  let Inst{9-5}   = rs;
52  let Inst{4-0}   = op;
53}
54
55class POOL16C_JRCADDIUSP_FM_MM16R6<bits<5> op> {
56  bits<5> imm;
57
58  bits<16> Inst;
59
60  let Inst{15-10} = 0x11;
61  let Inst{9-5}   = imm;
62  let Inst{4-0}   = op;
63}
64
65class POOL16C_LWM_SWM_FM_MM16R6<bits<4> funct> {
66  bits<2> rt;
67  bits<4> addr;
68
69  bits<16> Inst;
70
71  let Inst{15-10} = 0x11;
72  let Inst{9-8}   = rt;
73  let Inst{7-4}   = addr;
74  let Inst{3-0}   = funct;
75}
76
77class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
78  bits<5> rd;
79  bits<5> rt;
80
81  bits<32> Inst;
82
83  let Inst{31-26} = 0b000000;
84  let Inst{25-21} = rt;
85  let Inst{20-16} = rd;
86  let Inst{15-12} = 0b0000;
87  let Inst{11-6} = funct;
88  let Inst{5-0} = 0b111100;
89}
90
91class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
92  bits<21> addr;
93  bits<5> hint;
94
95  bits<32> Inst;
96
97  let Inst{31-26} = opgroup;
98  let Inst{25-21} = hint;
99  let Inst{20-16} = addr{20-16};
100  let Inst{15-12} = funct;
101  let Inst{11-0}  = addr{11-0};
102}
103
104class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
105  bits<5> rd;
106  bits<5> rt;
107  bits<5> rs;
108
109  bits<32> Inst;
110
111  let Inst{31-26} = 0;
112  let Inst{25-21} = rt;
113  let Inst{20-16} = rs;
114  let Inst{15-11} = rd;
115  let Inst{10}    = 0;
116  let Inst{9-0}   = funct;
117}
118
119class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
120  bits<5>  rt;
121  bits<5>  rs;
122  bits<16> imm16;
123
124  bits<32> Inst;
125
126  let Inst{31-26} = op;
127  let Inst{25-21} = rt;
128  let Inst{20-16} = rs;
129  let Inst{15-0}  = imm16;
130}
131
132class POOL32C_ST_EVA_FM_MMR6<bits<6> op, bits<3> funct> : MipsR6Inst {
133  bits<21> addr;
134  bits<5> hint;
135  bits<5> base = addr{20-16};
136  bits<9> offset = addr{8-0};
137
138  bits<32> Inst;
139
140  let Inst{31-26} = op;
141  let Inst{25-21} = hint;
142  let Inst{20-16} = base;
143  let Inst{15-12} = 0b1010;
144  let Inst{11-9} = funct;
145  let Inst{8-0}  = offset;
146}
147
148class LB32_FM_MMR6 : MipsR6Inst {
149  bits<21> addr;
150  bits<5> rt;
151  bits<5> base = addr{20-16};
152  bits<16> offset = addr{15-0};
153
154  bits<32> Inst;
155
156  let Inst{31-26} = 0b000111;
157  let Inst{25-21} = rt;
158  let Inst{20-16} = base;
159  let Inst{15-0}  = offset;
160}
161
162class LBU32_FM_MMR6 : MipsR6Inst {
163  bits<21> addr;
164  bits<5> rt;
165  bits<5> base = addr{20-16};
166  bits<16> offset = addr{15-0};
167
168  bits<32> Inst;
169
170  let Inst{31-26} = 0b000101;
171  let Inst{25-21} = rt;
172  let Inst{20-16} = base;
173  let Inst{15-0}  = offset;
174}
175
176class POOL32C_LB_LBU_FM_MMR6<bits<3> funct> : MipsR6Inst {
177  bits<21> addr;
178  bits<5> rt;
179
180  bits<32> Inst;
181
182  let Inst{31-26} = 0b011000;
183  let Inst{25-21} = rt;
184  let Inst{20-16} = addr{20-16};
185  let Inst{15-12} = 0b0110;
186  let Inst{11-9} = funct;
187  let Inst{8-0}  = addr{8-0};
188}
189
190class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
191    : MMR6Arch<instr_asm> {
192  bits<5> rd;
193  bits<5> rt;
194
195  bits<32> Inst;
196
197  let Inst{31-26} = 0b000000;
198  let Inst{25-21} = rd;
199  let Inst{20-16} = rt;
200  let Inst{15-6}  = funct;
201  let Inst{5-0}   = 0b111100;
202}
203
204class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
205  bits<5> rt;
206  bits<19> imm;
207
208  bits<32> Inst;
209
210  let Inst{31-26} = 0b011110;
211  let Inst{25-21} = rt;
212  let Inst{20-19} = funct;
213  let Inst{18-0}  = imm;
214}
215
216class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
217  bits<5> rt;
218  bits<16> imm;
219
220  bits<32> Inst;
221
222  let Inst{31-26} = 0b011110;
223  let Inst{25-21} = rt;
224  let Inst{20-16} = funct;
225  let Inst{15-0}  = imm;
226}
227
228class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
229  bits<5> rd;
230  bits<5> rs;
231  bits<5> rt;
232
233  bits<32> Inst;
234
235  let Inst{31-26} = 0b000000;
236  let Inst{25-21} = rt;
237  let Inst{20-16} = rs;
238  let Inst{15-11} = rd;
239  let Inst{10}    = 0;
240  let Inst{9-0}   = funct;
241}
242
243class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
244  bits<32> Inst;
245
246  let Inst{31-26} = 0;
247  let Inst{25-21} = 0;
248  let Inst{20-16} = 0;
249  let Inst{15-11} = op;
250  let Inst{10-6} = 0;
251  let Inst{5-0} = 0;
252}
253
254class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
255  bits<5> rt;
256  bits<5> rd;
257  bits<32> Inst;
258
259  let Inst{31-26} = 0;
260  let Inst{25-21} = rt;
261  let Inst{20-16} = rd;
262  let Inst{15-6} = funct;
263  let Inst{5-0} = 0b111100;
264}
265
266class POOL32A_RDHWR_FM_MMR6 {
267  bits<5> rt;
268  bits<5> rs;
269  bits<3> sel;
270  bits<32> Inst;
271
272  let Inst{31-26} = 0;
273  let Inst{25-21} = rt;
274  let Inst{20-16} = rs;
275  let Inst{15-14} = 0;
276  let Inst{13-11} = sel;
277  let Inst{10} = 0;
278  let Inst{9-0} = 0b0111000000;
279}
280
281class POOL32A_SYNC_FM_MMR6 {
282  bits<5> stype;
283
284  bits<32> Inst;
285
286  let Inst{31-26} = 0;
287  let Inst{25-21} = 0;
288  let Inst{20-16} = stype;
289  let Inst{15-6}  = 0b0110101101;
290  let Inst{5-0}   = 0b111100;
291}
292
293class POOL32I_SYNCI_FM_MMR6 {
294  bits<21> addr;
295  bits<5> base = addr{20-16};
296  bits<16> immediate = addr{15-0};
297
298  bits<32> Inst;
299
300  let Inst{31-26} = 0b010000;
301  let Inst{25-21} = 0b01100;
302  let Inst{20-16} = base;
303  let Inst{15-0}  = immediate;
304}
305
306class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
307  bits<5> rs;
308  bits<5> rt;
309
310  bits<32> Inst;
311
312  let Inst{31-26} = 0b000000;
313  let Inst{25-21} = rt;
314  let Inst{20-16} = rs;
315  let Inst{15-6}  = funct;
316  let Inst{5-0}   = 0b111100;
317}
318
319class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
320  bits<5> rs;
321  bits<5> rt;
322
323  bits<32> Inst;
324
325  let Inst{31-26} = 0b000000;
326  let Inst{25-21} = rs;
327  let Inst{20-16} = 0b00000;
328  let Inst{15-11} = rt;
329  let Inst{10-6}  = 0b00001;
330  let Inst{5-0}   = funct;
331}
332
333class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
334  bits<5> rd;
335  bits<5> rs;
336  bits<5> rt;
337  bits<2> bp;
338
339  bits<32> Inst;
340
341  let Inst{31-26} = 0b000000;
342  let Inst{25-21} = rs;
343  let Inst{20-16} = rt;
344  let Inst{15-11} = rd;
345  let Inst{10-9}  = bp;
346  let Inst{8-6}   = 0b000;
347  let Inst{5-0}   = funct;
348}
349
350class AUI_FM_MMR6 : MipsR6Inst {
351  bits<5> rs;
352  bits<5> rt;
353  bits<16> imm;
354
355  bits<32> Inst;
356
357  let Inst{31-26} = 0b000100;
358  let Inst{25-21} = rt;
359  let Inst{20-16} = rs;
360  let Inst{15-0} = imm;
361}
362
363class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
364  bits<5> rd;
365  bits<5> rs;
366  bits<5> rt;
367  bits<2> imm2;
368
369  bits<32> Inst;
370
371  let Inst{31-26} = 0b000000;
372  let Inst{25-21} = rt;
373  let Inst{20-16} = rs;
374  let Inst{15-11} = rd;
375  let Inst{10-9}  = imm2;
376  let Inst{8-6}   = 0b000;
377  let Inst{5-0}   = funct;
378}
379
380class SB32_SH32_STORE_FM_MMR6<bits<6> op> {
381  bits<5> rt;
382  bits<21> addr;
383  bits<5> base = addr{20-16};
384  bits<16> offset = addr{15-0};
385
386  bits<32> Inst;
387
388  let Inst{31-26} = op;
389  let Inst{25-21} = rt;
390  let Inst{20-16} = base;
391  let Inst{15-0}  = offset;
392}
393
394class POOL32C_STORE_EVA_FM_MMR6<bits<3> funct> {
395  bits<5> rt;
396  bits<21> addr;
397  bits<5> base = addr{20-16};
398  bits<9> offset = addr{8-0};
399
400  bits<32> Inst;
401
402  let Inst{31-26} = 0b011000;
403  let Inst{25-21} = rt;
404  let Inst{20-16} = base;
405  let Inst{15-12} = 0b1010;
406  let Inst{11-9}  = funct;
407  let Inst{8-0}   = offset;
408}
409
410class LOAD_WORD_EVA_FM_MMR6<bits<3> funct> {
411  bits<5> rt;
412  bits<21> addr;
413  bits<5> base = addr{20-16};
414  bits<9> offset = addr{8-0};
415
416  bits<32> Inst;
417
418  let Inst{31-26} = 0b011000;
419  let Inst{25-21} = rt;
420  let Inst{20-16} = base;
421  let Inst{15-12} = 0b0110;
422  let Inst{11-9}  = funct;
423  let Inst{8-0}   = offset;
424}
425
426class LOAD_WORD_FM_MMR6 {
427  bits<5> rt;
428  bits<21> addr;
429  bits<5> base = addr{20-16};
430  bits<16> offset = addr{15-0};
431
432  bits<32> Inst;
433
434  let Inst{31-26} = 0b111111;
435  let Inst{25-21} = rt;
436  let Inst{20-16} = base;
437  let Inst{15-0}  = offset;
438}
439
440class LOAD_UPPER_IMM_FM_MMR6 {
441  bits<5> rt;
442  bits<16> imm16;
443
444  bits<32> Inst;
445
446  let Inst{31-26} = 0b000100;
447  let Inst{25-21} = rt;
448  let Inst{20-16} = 0;
449  let Inst{15-0}  = imm16;
450}
451
452class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
453  bits<5> rt;
454  bits<16> offset;
455
456  bits<32> Inst;
457
458  let Inst{31-26} = funct;
459  let Inst{25-21} = rt;
460  let Inst{20-16} = 0b00000;
461  let Inst{15-0}  = offset;
462}
463
464class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
465  bits<5> rt;
466  bits<16> offset;
467
468  bits<32> Inst;
469
470  let Inst{31-26} = funct;
471  let Inst{25-21} = rt;
472  let Inst{20-16} = rt;
473  let Inst{15-0}  = offset;
474}
475
476class POOL32A_ERET_FM_MMR6<string instr_asm, bits<10> funct>
477    : MMR6Arch<instr_asm> {
478  bits<32> Inst;
479
480  let Inst{31-26} = 0x00;
481  let Inst{25-16} = 0x00;
482  let Inst{15-6}  = funct;
483  let Inst{5-0}   = 0x3c;
484}
485
486class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
487  bits<32> Inst;
488
489  let Inst{31-26} = 0x00;
490  let Inst{25-17} = 0x00;
491  let Inst{16-16} = 0x01;
492  let Inst{15-6}  = 0x3cd;
493  let Inst{5-0}   = 0x3c;
494}
495
496class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
497  bits<10> code_1;
498  bits<10> code_2;
499  bits<32> Inst;
500  let Inst{31-26} = 0x0;
501  let Inst{25-16} = code_1;
502  let Inst{15-6}  = code_2;
503  let Inst{5-0}   = 0x07;
504}
505
506class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
507  bits<32> Inst;
508
509  let Inst{31-26} = 0x0;
510  let Inst{25-21} = 0x0;
511  let Inst{20-16} = 0x0;
512  let Inst{15-11} = op;
513  let Inst{10-6}  = 0x0;
514  let Inst{5-0}   = 0x0;
515}
516
517class POOL32A_EIDI_MMR6_ENC<string instr_asm, bits<10> funct>
518    : MMR6Arch<instr_asm> {
519  bits<32> Inst;
520  bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
521
522  let Inst{31-26} = 0x00;
523  let Inst{25-21} = 0x00;
524  let Inst{20-16} = rt;
525  let Inst{15-6}  = funct;
526  let Inst{5-0}   = 0x3c;
527}
528
529class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
530  bits<5> rd;
531  bits<5> rt;
532  bits<5> shamt;
533
534  bits<32> Inst;
535
536  let Inst{31-26} = 0;
537  let Inst{25-21} = rd;
538  let Inst{20-16} = rt;
539  let Inst{15-11} = shamt;
540  let Inst{10}    = rotate;
541  let Inst{9-0}   = funct;
542}
543
544class SW32_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
545  bits<5> rt;
546  bits<21> addr;
547
548  bits<32> Inst;
549
550  let Inst{31-26} = op;
551  let Inst{25-21} = rt;
552  let Inst{20-16} = addr{20-16};
553  let Inst{15-0}  = addr{15-0};
554}
555
556class POOL32C_SWE_FM_MMR6<string instr_asm, bits<6> op, bits<4> fmt,
557    bits<3> funct> : MMR6Arch<instr_asm> {
558  bits<5> rt;
559  bits<21> addr;
560  bits<5> base = addr{20-16};
561  bits<9> offset = addr{8-0};
562
563  bits<32> Inst;
564
565  let Inst{31-26} = op;
566  let Inst{25-21} = rt;
567  let Inst{20-16} = base;
568  let Inst{15-12} = fmt;
569  let Inst{11-9} = funct;
570  let Inst{8-0}  = offset;
571}
572
573class POOL32F_ARITH_FM_MMR6<string instr_asm, bits<2> fmt, bits<8> funct>
574    : MMR6Arch<instr_asm>, MipsR6Inst {
575  bits<5> ft;
576  bits<5> fs;
577  bits<5> fd;
578
579  bits<32> Inst;
580
581  let Inst{31-26} = 0b010101;
582  let Inst{25-21} = ft;
583  let Inst{20-16} = fs;
584  let Inst{15-11} = fd;
585  let Inst{10}    = 0;
586  let Inst{9-8}   = fmt;
587  let Inst{7-0}   = funct;
588}
589
590class POOL32F_ARITHF_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
591    : MMR6Arch<instr_asm>, MipsR6Inst {
592  bits<5> ft;
593  bits<5> fs;
594  bits<5> fd;
595
596  bits<32> Inst;
597
598  let Inst{31-26} = 0b010101;
599  let Inst{25-21} = ft;
600  let Inst{20-16} = fs;
601  let Inst{15-11} = fd;
602  let Inst{10-9}  = fmt;
603  let Inst{8-0}   = funct;
604}
605
606class POOL32F_MOV_NEG_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
607    : MMR6Arch<instr_asm>, MipsR6Inst {
608  bits<5> ft;
609  bits<5> fs;
610
611  bits<32> Inst;
612
613  let Inst{31-26} = 0b010101;
614  let Inst{25-21} = ft;
615  let Inst{20-16} = fs;
616  let Inst{15}    = 0;
617  let Inst{14-13} = fmt;
618  let Inst{12-6}  = funct;
619  let Inst{5-0}   = 0b111011;
620}
621
622class POOL32F_MINMAX_FM<string instr_asm, bits<2> fmt, bits<9> funct>
623    : MMR6Arch<instr_asm>, MipsR6Inst {
624  bits<5> ft;
625  bits<5> fs;
626  bits<5> fd;
627
628  bits<32> Inst;
629
630  let Inst{31-26} = 0b010101;
631  let Inst{25-21} = ft;
632  let Inst{20-16} = fs;
633  let Inst{15-11} = fd;
634  let Inst{10-9} = fmt;
635  let Inst{8-0} = funct;
636}
637
638class POOL32F_CMP_FM<string instr_asm, bits<6> format, FIELD_CMP_COND Cond>
639    : MMR6Arch<instr_asm>, MipsR6Inst {
640  bits<5> ft;
641  bits<5> fs;
642  bits<5> fd;
643
644  bits<32> Inst;
645
646  let Inst{31-26} = 0b010101;
647  let Inst{25-21} = ft;
648  let Inst{20-16} = fs;
649  let Inst{15-11} = fd;
650  let Inst{10-6} = Cond.Value;
651  let Inst{5-0} = format;
652}
653
654class POOL32F_CVT_LW_FM<string instr_asm, bit fmt, bits<8> funct>
655    : MMR6Arch<instr_asm>, MipsR6Inst {
656  bits<5> ft;
657  bits<5> fs;
658
659  bits<32> Inst;
660  let Inst{31-26} = 0b010101;
661  let Inst{25-21} = ft;
662  let Inst{20-16} = fs;
663  let Inst{15} = 0;
664  let Inst{14} = fmt;
665  let Inst{13-6} = funct;
666  let Inst{5-0} = 0b111011;
667}
668
669class POOL32F_CVT_DS_FM<string instr_asm, bits<2> fmt, bits<7> funct>
670    : MMR6Arch<instr_asm>, MipsR6Inst {
671  bits<5> ft;
672  bits<5> fs;
673
674  bits<32> Inst;
675  let Inst{31-26} = 0b010101;
676  let Inst{25-21} = ft;
677  let Inst{20-16} = fs;
678  let Inst{15} = 0;
679  let Inst{14-13} = fmt;
680  let Inst{12-6} = funct;
681  let Inst{5-0} = 0b111011;
682}
683
684class POOL32F_ABS_FM_MMR6<string instr_asm, bits<2> fmt, bits<7> funct>
685    : MMR6Arch<instr_asm>, MipsR6Inst {
686  bits<5> ft;
687  bits<5> fs;
688
689  bits<32> Inst;
690
691  let Inst{31-26} = 0b010101;
692  let Inst{25-21} = ft;
693  let Inst{20-16} = fs;
694  let Inst{15}    = 0;
695  let Inst{14-13} = fmt;
696  let Inst{12-6}  = funct;
697  let Inst{5-0}   = 0b111011;
698}
699
700class POOL32F_MATH_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
701    : MMR6Arch<instr_asm>, MipsR6Inst {
702  bits<5> ft;
703  bits<5> fs;
704
705  bits<32> Inst;
706
707  let Inst{31-26} = 0b010101;
708  let Inst{25-21} = ft;
709  let Inst{20-16} = fs;
710  let Inst{15}    = 0;
711  let Inst{14}    = fmt;
712  let Inst{13-6}  = funct;
713  let Inst{5-0}   = 0b111011;
714}
715
716class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
717  bits<3> rs;
718  bits<3> rt;
719  bits<3> rd;
720
721  bits<16> Inst;
722
723  let Inst{15-10} = 0b000001;
724  let Inst{9-7}   = rs;
725  let Inst{6-4}   = rt;
726  let Inst{3-1}   = rd;
727  let Inst{0}     = 0;
728}
729
730class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
731  bits<3> rt;
732  bits<3> rs;
733
734  bits<16> Inst;
735
736  let Inst{15-10} = 0b010001;
737  let Inst{9-7}   = rt;
738  let Inst{6-4}   = rs;
739  let Inst{3-0}   = 0b0001;
740}
741
742class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
743  bits<3> rt;
744  bits<3> rs;
745
746  bits<16> Inst;
747
748  let Inst{15-10} = 0x11;
749  let Inst{9-7}   = rt;
750  let Inst{6-4}   = rs;
751  let Inst{3-0}   = 0b0000;
752}
753
754class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
755  bits<3> rt;
756  bits<3> rs;
757
758  bits<16> Inst;
759
760  let Inst{15-10} = 0b010001;
761  let Inst{9-7}   = rt;
762  let Inst{6-4}   = rs;
763  let Inst{3-0}   = op;
764}
765
766class POOL16C_BREAKPOINT_FM_MMR6<bits<6> op> {
767  bits<4> code_;
768  bits<16> Inst;
769
770  let Inst{15-10} = 0b010001;
771  let Inst{9-6}   = code_;
772  let Inst{5-0}   = op;
773}
774
775class POOL16A_SUBU16_FM_MMR6 {
776  bits<3> rs;
777  bits<3> rt;
778  bits<3> rd;
779
780  bits<16> Inst;
781
782  let Inst{15-10} = 0b000001;
783  let Inst{9-7}   = rs;
784  let Inst{6-4}   = rt;
785  let Inst{3-1}   = rd;
786  let Inst{0}     = 0b1;
787}
788
789class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
790  bits<5> rt;
791  bits<5> rs;
792
793  bits<32> Inst;
794
795  let Inst{31-26} = 0x00;
796  let Inst{25-21} = rt;
797  let Inst{20-16} = rs;
798  let Inst{15-6}  = funct;
799  let Inst{5-0}   = 0x3c;
800}
801
802class POOL32F_RECIP_ROUND_FM_MMR6<string instr_asm, bits<1> fmt, bits<8> funct>
803    : MMR6Arch<instr_asm>, MipsR6Inst {
804  bits<5> ft;
805  bits<5> fs;
806
807  bits<32> Inst;
808
809  let Inst{31-26} = 0b010101;
810  let Inst{25-21} = ft;
811  let Inst{20-16} = fs;
812  let Inst{15}    = 0;
813  let Inst{14}    = fmt;
814  let Inst{13-6}  = funct;
815  let Inst{5-0}   = 0b111011;
816}
817
818class POOL32F_RINT_FM_MMR6<string instr_asm, bits<2> fmt>
819    : MMR6Arch<instr_asm>, MipsR6Inst {
820  bits<5> fs;
821  bits<5> fd;
822
823  bits<32> Inst;
824
825  let Inst{31-26} = 0b010101;
826  let Inst{25-21} = fs;
827  let Inst{20-16} = fd;
828  let Inst{15-11} = 0;
829  let Inst{10-9}  = fmt;
830  let Inst{8-0}   = 0b000100000;
831}
832
833class POOL32F_SEL_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
834    : MMR6Arch<instr_asm>, MipsR6Inst {
835  bits<5> ft;
836  bits<5> fs;
837  bits<5> fd;
838
839  bits<32> Inst;
840
841  let Inst{31-26} = 0b010101;
842  let Inst{25-21} = ft;
843  let Inst{20-16} = fs;
844  let Inst{15-11} = fd;
845  let Inst{10-9}  = fmt;
846  let Inst{8-0}   = funct;
847}
848
849class POOL32F_CLASS_FM_MMR6<string instr_asm, bits<2> fmt, bits<9> funct>
850    : MMR6Arch<instr_asm>, MipsR6Inst {
851  bits<5> fs;
852  bits<5> fd;
853
854  bits<32> Inst;
855
856  let Inst{31-26} = 0b010101;
857  let Inst{25-21} = fs;
858  let Inst{20-16} = fd;
859  let Inst{15-11} = 0b00000;
860  let Inst{10-9}  = fmt;
861  let Inst{8-0}   = funct;
862}
863