1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes Mips64 instructions. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Mips Operand, Complex Patterns and Transformations Definitions. 16//===----------------------------------------------------------------------===// 17 18// Unsigned Operand 19def uimm16_64 : Operand<i64> { 20 let PrintMethod = "printUnsignedImm"; 21} 22 23// Signed Operand 24def simm10_64 : Operand<i64>; 25 26// Transformation Function - get Imm - 32. 27def Subtract32 : SDNodeXForm<imm, [{ 28 return getImm(N, (unsigned)N->getZExtValue() - 32); 29}]>; 30 31// shamt must fit in 6 bits. 32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 33 34// Node immediate fits as 10-bit sign extended on target immediate. 35// e.g. seqi, snei 36def immSExt10_64 : PatLeaf<(i64 imm), 37 [{ return isInt<10>(N->getSExtValue()); }]>; 38 39def immZExt16_64 : PatLeaf<(i64 imm), 40 [{ return isInt<16>(N->getZExtValue()); }]>; 41 42def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>; 43 44// Transformation function: get log2 of low 32 bits of immediate 45def Log2LO : SDNodeXForm<imm, [{ 46 return getImm(N, Log2_64((unsigned) N->getZExtValue())); 47}]>; 48 49// Transformation function: get log2 of high 32 bits of immediate 50def Log2HI : SDNodeXForm<imm, [{ 51 return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32))); 52}]>; 53 54// Predicate: True if immediate is a power of 2 and fits 32 bits 55def PowerOf2LO : PatLeaf<(imm), [{ 56 if (N->getValueType(0) == MVT::i64) { 57 uint64_t Imm = N->getZExtValue(); 58 return isPowerOf2_64(Imm) && (Imm & 0xffffffff) == Imm; 59 } 60 else 61 return false; 62}]>; 63 64// Predicate: True if immediate is a power of 2 and exceeds 32 bits 65def PowerOf2HI : PatLeaf<(imm), [{ 66 if (N->getValueType(0) == MVT::i64) { 67 uint64_t Imm = N->getZExtValue(); 68 return isPowerOf2_64(Imm) && (Imm & 0xffffffff00000000) == Imm; 69 } 70 else 71 return false; 72}]>; 73 74//===----------------------------------------------------------------------===// 75// Instructions specific format 76//===----------------------------------------------------------------------===// 77let usesCustomInserter = 1 in { 78 def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 79 def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 80 def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 81 def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 82 def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 83 def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 84 def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 85 def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 86} 87 88/// Pseudo instructions for loading and storing accumulator registers. 89let isPseudo = 1, isCodeGenOnly = 1 in { 90 def LOAD_ACC128 : Load<"", ACC128>; 91 def STORE_ACC128 : Store<"", ACC128>; 92} 93 94//===----------------------------------------------------------------------===// 95// Instruction definition 96//===----------------------------------------------------------------------===// 97let DecoderNamespace = "Mips64" in { 98/// Arithmetic Instructions (ALU Immediate) 99def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>, 100 ISA_MIPS3_NOT_32R6_64R6; 101def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, 102 immSExt16, add>, 103 ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3; 104 105let isCodeGenOnly = 1 in { 106def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 107 SLTI_FM<0xa>; 108def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 109 SLTI_FM<0xb>; 110def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>, 111 ADDI_FM<0xc>; 112def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>, 113 ADDI_FM<0xd>; 114def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>, 115 ADDI_FM<0xe>; 116def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM; 117} 118 119/// Arithmetic Instructions (3-Operand, R-Type) 120def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>, 121 ISA_MIPS3; 122def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>, 123 ISA_MIPS3; 124def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>, 125 ISA_MIPS3; 126def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>, 127 ISA_MIPS3; 128 129let isCodeGenOnly = 1 in { 130def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 131def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 132def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>; 133def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>; 134def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>; 135def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 136} 137 138/// Shift Instructions 139def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>, 140 SRA_FM<0x38, 0>, ISA_MIPS3; 141def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>, 142 SRA_FM<0x3a, 0>, ISA_MIPS3; 143def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>, 144 SRA_FM<0x3b, 0>, ISA_MIPS3; 145def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>, 146 SRLV_FM<0x14, 0>, ISA_MIPS3; 147def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>, 148 SRLV_FM<0x16, 0>, ISA_MIPS3; 149def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>, 150 SRLV_FM<0x17, 0>, ISA_MIPS3; 151def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>, 152 SRA_FM<0x3c, 0>, ISA_MIPS3; 153def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>, 154 SRA_FM<0x3e, 0>, ISA_MIPS3; 155def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>, 156 SRA_FM<0x3f, 0>, ISA_MIPS3; 157 158// Rotate Instructions 159def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr, 160 immZExt6>, 161 SRA_FM<0x3a, 1>, ISA_MIPS64R2; 162def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>, 163 SRLV_FM<0x16, 1>, ISA_MIPS64R2; 164def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>, 165 SRA_FM<0x3e, 1>, ISA_MIPS64R2; 166 167/// Load and Store Instructions 168/// aligned 169let isCodeGenOnly = 1 in { 170def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>; 171def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>; 172def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>; 173def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>; 174def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>; 175def SB64 : Store<"sb", GPR64Opnd, truncstorei8, II_SB>, LW_FM<0x28>; 176def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>; 177def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>; 178} 179 180def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3; 181def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3; 182def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3; 183 184/// load/store left/right 185let isCodeGenOnly = 1 in { 186def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>; 187def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>; 188def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>; 189def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>; 190} 191 192def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>, 193 ISA_MIPS3_NOT_32R6_64R6; 194def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>, 195 ISA_MIPS3_NOT_32R6_64R6; 196def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>, 197 ISA_MIPS3_NOT_32R6_64R6; 198def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>, 199 ISA_MIPS3_NOT_32R6_64R6; 200 201/// Load-linked, Store-conditional 202def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3_NOT_32R6_64R6; 203def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3_NOT_32R6_64R6; 204 205/// Jump and Branch Instructions 206let isCodeGenOnly = 1 in { 207 def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; 208 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 209 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 210 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 211 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 212 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 213 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 214 def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 215 def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 216 def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; 217} 218 219def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; 220def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; 221 222/// Multiply and Divide Instructions. 223def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>, 224 MULT_FM<0, 0x1c>, ISA_MIPS3_NOT_32R6_64R6; 225def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>, 226 MULT_FM<0, 0x1d>, ISA_MIPS3_NOT_32R6_64R6; 227def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 228 II_DMULT>, ISA_MIPS3_NOT_32R6_64R6; 229def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 230 II_DMULTU>, ISA_MIPS3_NOT_32R6_64R6; 231def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>, 232 MULT_FM<0, 0x1e>, ISA_MIPS3_NOT_32R6_64R6; 233def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>, 234 MULT_FM<0, 0x1f>, ISA_MIPS3_NOT_32R6_64R6; 235def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 236 II_DDIV, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 237def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 238 II_DDIVU, 0, 1, 1>, ISA_MIPS3_NOT_32R6_64R6; 239 240let isCodeGenOnly = 1 in { 241def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>, 242 ISA_MIPS3_NOT_32R6_64R6; 243def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>, 244 ISA_MIPS3_NOT_32R6_64R6; 245def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>, 246 ISA_MIPS3_NOT_32R6_64R6; 247def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>, 248 ISA_MIPS3_NOT_32R6_64R6; 249def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>, 250 ISA_MIPS3_NOT_32R6_64R6; 251def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>, 252 ISA_MIPS3_NOT_32R6_64R6; 253def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>, ISA_MIPS3_NOT_32R6_64R6; 254 255/// Sign Ext In Register Instructions. 256def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>, 257 ISA_MIPS32R2; 258def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, 259 ISA_MIPS32R2; 260} 261 262/// Count Leading 263def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, ISA_MIPS64_NOT_64R6; 264def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, ISA_MIPS64_NOT_64R6; 265 266/// Double Word Swap Bytes/HalfWords 267def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; 268def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2; 269 270def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 271 272let isCodeGenOnly = 1 in 273def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 274 275let AdditionalPredicates = [NotInMicroMips] in { 276 // TODO: Add 'pos + size' constraint check to dext* instructions 277 // DEXT: 0 < pos + size <= 63 278 // DEXTM, DEXTU: 32 < pos + size <= 64 279 def DEXT : ExtBase<"dext", GPR64Opnd, uimm5, uimm5_plus1, MipsExt>, 280 EXT_FM<3>; 281 def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5, uimm5_plus33, MipsExt>, 282 EXT_FM<1>; 283 def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, 284 MipsExt>, EXT_FM<2>; 285} 286 287def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; 288def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32>, EXT_FM<6>; 289def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>; 290 291let isCodeGenOnly = 1, rs = 0, shamt = 0 in { 292 def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 293 "dsll\t$rd, $rt, 32", [], II_DSLL>; 294 def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 295 "sll\t$rd, $rt, 0", [], II_SLL>; 296 def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 297 "sll\t$rd, $rt, 0", [], II_SLL>; 298} 299 300// We need the following pseudo instruction to avoid offset calculation for 301// long branches. See the comment in file MipsLongBranch.cpp for detailed 302// explanation. 303 304// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt) 305// where %PART may be %hi or %lo, depending on the relocation kind 306// that $tgt is annotated with. 307def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst), 308 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>; 309 310// Cavium Octeon cnMIPS instructions 311let DecoderNamespace = "CnMips", 312 EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug 313 AdditionalPredicates = [HasCnMips] in { 314 315class Count1s<string opstr, RegisterOperand RO>: 316 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 317 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> { 318 let TwoOperandAliasConstraint = "$rd = $rs"; 319} 320 321class ExtsCins<string opstr, SDPatternOperator Op = null_frag>: 322 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), 323 !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), 324 [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], 325 NoItinerary, FrmR, opstr> { 326 let TwoOperandAliasConstraint = "$rt = $rs"; 327} 328 329class SetCC64_R<string opstr, PatFrag cond_op> : 330 InstSE<(outs GPR64Opnd:$rd), (ins GPR64Opnd:$rs, GPR64Opnd:$rt), 331 !strconcat(opstr, "\t$rd, $rs, $rt"), 332 [(set GPR64Opnd:$rd, (zext (cond_op GPR64Opnd:$rs, 333 GPR64Opnd:$rt)))], 334 II_SEQ_SNE, FrmR, opstr> { 335 let TwoOperandAliasConstraint = "$rd = $rs"; 336} 337 338class SetCC64_I<string opstr, PatFrag cond_op>: 339 InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, simm10_64:$imm10), 340 !strconcat(opstr, "\t$rt, $rs, $imm10"), 341 [(set GPR64Opnd:$rt, (zext (cond_op GPR64Opnd:$rs, 342 immSExt10_64:$imm10)))], 343 II_SEQI_SNEI, FrmI, opstr> { 344 let TwoOperandAliasConstraint = "$rt = $rs"; 345} 346 347class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, 348 RegisterOperand RO, Operand ImmOp, bits<64> shift = 1> : 349 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset), 350 !strconcat(opstr, "\t$rs, $p, $offset"), 351 [(brcond (i32 (cond_op (and RO:$rs, (shl shift, immZExt5_64:$p)), 0)), 352 bb:$offset)], II_BBIT, FrmI, opstr> { 353 let isBranch = 1; 354 let isTerminator = 1; 355 let hasDelaySlot = 1; 356 let Defs = [AT]; 357} 358 359class MFC2OP<string asmstr, RegisterOperand RO> : 360 InstSE<(outs RO:$rt, uimm16:$imm16), (ins), 361 !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>; 362 363// Unsigned Byte Add 364let Pattern = [(set GPR64Opnd:$rd, 365 (and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in 366def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, 367 ADD_FM<0x1c, 0x28>; 368 369// Branch on Bit Clear /+32 370def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd, 371 uimm5_64_report_uimm6>, BBIT_FM<0x32>; 372def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64, 373 0x100000000>, 374 BBIT_FM<0x36>; 375 376// Branch on Bit Set /+32 377def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd, 378 uimm5_64_report_uimm6>, BBIT_FM<0x3a>; 379def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64, 380 0x100000000>, BBIT_FM<0x3e>; 381 382// Multiply Doubleword to GPR 383let Defs = [HI0, LO0, P0, P1, P2] in 384def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, 385 ADD_FM<0x1c, 0x03>; 386 387// Extract a signed bit field /+32 388def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>; 389def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>; 390 391// Clear and insert a bit field /+32 392def CINS : ExtsCins<"cins">, EXTS_FM<0x32>; 393def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>; 394 395// Move to multiplier/product register 396def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>; 397def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>; 398def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>; 399def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>; 400def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>; 401def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>; 402 403// Count Ones in a Word/Doubleword 404def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>; 405def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>; 406 407// Set on equal/not equal 408def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>; 409def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>; 410def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>; 411def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>; 412 413// 192-bit x 64-bit Unsigned Multiply and Add 414let Defs = [P0, P1, P2] in 415def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, 416 ADD_FM<0x1c, 0x11>; 417 418// 64-bit Unsigned Multiply and Add Move 419let Defs = [MPL0, P0, P1, P2] in 420def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, 421 ADD_FM<0x1c, 0x10>; 422 423// 64-bit Unsigned Multiply and Add 424let Defs = [MPL1, MPL2, P0, P1, P2] in 425def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, 426 ADD_FM<0x1c, 0x0f>; 427 428// Move between CPU and coprocessor registers 429def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>; 430def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>; 431} 432 433} 434 435/// Move between CPU and coprocessor registers 436let DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 437def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd, COP0Opnd>, MFC3OP_FM<0x10, 1>, ISA_MIPS3; 438def DMTC0 : MTC3OP<"dmtc0", COP0Opnd, GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3; 439def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd, COP2Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3; 440def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3; 441} 442 443//===----------------------------------------------------------------------===// 444// Arbitrary patterns that map to one or more instructions 445//===----------------------------------------------------------------------===// 446 447// extended loads 448def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 449def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 450def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 451def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 452 453// hi/lo relocs 454def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 455def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 456def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 457def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 458def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 459def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 460 461def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 462def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 463def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 464def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 465def : MipsPat<(MipsLo tglobaltlsaddr:$in), 466 (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 467def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 468 469def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 470 (DADDiu GPR64:$hi, tglobaladdr:$lo)>; 471def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 472 (DADDiu GPR64:$hi, tblockaddress:$lo)>; 473def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 474 (DADDiu GPR64:$hi, tjumptable:$lo)>; 475def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 476 (DADDiu GPR64:$hi, tconstpool:$lo)>; 477def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 478 (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>; 479 480def : WrapperPat<tglobaladdr, DADDiu, GPR64>; 481def : WrapperPat<tconstpool, DADDiu, GPR64>; 482def : WrapperPat<texternalsym, DADDiu, GPR64>; 483def : WrapperPat<tblockaddress, DADDiu, GPR64>; 484def : WrapperPat<tjumptable, DADDiu, GPR64>; 485def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; 486 487defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 488 ZERO_64>; 489 490def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 491 (BLEZ64 i64:$lhs, bb:$dst)>; 492def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 493 (BGEZ64 i64:$lhs, bb:$dst)>; 494 495// setcc patterns 496defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; 497defm : SetlePats<GPR64, SLT64, SLTu64>; 498defm : SetgtPats<GPR64, SLT64, SLTu64>; 499defm : SetgePats<GPR64, SLT64, SLTu64>; 500defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; 501 502// truncate 503def : MipsPat<(trunc (assertsext GPR64:$src)), 504 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 505def : MipsPat<(trunc (assertzext GPR64:$src)), 506 (EXTRACT_SUBREG GPR64:$src, sub_32)>; 507def : MipsPat<(i32 (trunc GPR64:$src)), 508 (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; 509 510// variable shift instructions patterns 511def : MipsPat<(shl GPR64:$rt, (i32 (trunc GPR64:$rs))), 512 (DSLLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 513def : MipsPat<(srl GPR64:$rt, (i32 (trunc GPR64:$rs))), 514 (DSRLV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 515def : MipsPat<(sra GPR64:$rt, (i32 (trunc GPR64:$rs))), 516 (DSRAV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 517def : MipsPat<(rotr GPR64:$rt, (i32 (trunc GPR64:$rs))), 518 (DROTRV GPR64:$rt, (EXTRACT_SUBREG GPR64:$rs, sub_32))>; 519 520// 32-to-64-bit extension 521def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; 522def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 523def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 524 525// Sign extend in register 526def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 527 (SLL64_64 GPR64:$src)>; 528 529// bswap MipsPattern 530def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 531 532// Carry pattern 533def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), 534 (DSUBu GPR64:$lhs, GPR64:$rhs)>; 535let AdditionalPredicates = [NotDSP] in { 536 def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), 537 (DADDu GPR64:$lhs, GPR64:$rhs)>; 538 def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), 539 (DADDiu GPR64:$lhs, imm:$imm)>; 540} 541 542// Octeon bbit0/bbit1 MipsPattern 543let Predicates = [HasMips64, HasCnMips] in { 544def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 545 (BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; 546def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 547 (BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; 548def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst), 549 (BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>; 550def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst), 551 (BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>; 552} 553 554// Atomic load patterns. 555def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>; 556def : MipsPat<(atomic_load_16 addr:$a), (LH64 addr:$a)>; 557def : MipsPat<(atomic_load_32 addr:$a), (LW64 addr:$a)>; 558def : MipsPat<(atomic_load_64 addr:$a), (LD addr:$a)>; 559 560// Atomic store patterns. 561def : MipsPat<(atomic_store_8 addr:$a, GPR64:$v), (SB64 GPR64:$v, addr:$a)>; 562def : MipsPat<(atomic_store_16 addr:$a, GPR64:$v), (SH64 GPR64:$v, addr:$a)>; 563def : MipsPat<(atomic_store_32 addr:$a, GPR64:$v), (SW64 GPR64:$v, addr:$a)>; 564def : MipsPat<(atomic_store_64 addr:$a, GPR64:$v), (SD GPR64:$v, addr:$a)>; 565 566//===----------------------------------------------------------------------===// 567// Instruction aliases 568//===----------------------------------------------------------------------===// 569def : MipsInstAlias<"move $dst, $src", 570 (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 571 GPR_64; 572def : MipsInstAlias<"move $dst, $src", 573 (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 574 GPR_64; 575def : MipsInstAlias<"daddu $rs, $rt, $imm", 576 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 577 0>, ISA_MIPS3; 578def : MipsInstAlias<"dadd $rs, $rt, $imm", 579 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 580 0>, ISA_MIPS3_NOT_32R6_64R6; 581def : MipsInstAlias<"daddu $rs, $imm", 582 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 583 0>, ISA_MIPS3; 584def : MipsInstAlias<"dadd $rs, $imm", 585 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 586 0>, ISA_MIPS3_NOT_32R6_64R6; 587def : MipsInstAlias<"dsll $rd, $rt, $rs", 588 (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 589 ISA_MIPS3; 590def : MipsInstAlias<"dneg $rt, $rs", 591 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 592 ISA_MIPS3; 593def : MipsInstAlias<"dneg $rt", 594 (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>, 595 ISA_MIPS3; 596def : MipsInstAlias<"dnegu $rt, $rs", 597 (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, 598 ISA_MIPS3; 599def : MipsInstAlias<"dsubu $rt, $rs, $imm", 600 (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, 601 InvertedImOperand64:$imm), 0>, ISA_MIPS3; 602def : MipsInstAlias<"dsubi $rs, $rt, $imm", 603 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 604 InvertedImOperand64:$imm), 605 0>, ISA_MIPS3_NOT_32R6_64R6; 606def : MipsInstAlias<"dsubi $rs, $imm", 607 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 608 InvertedImOperand64:$imm), 609 0>, ISA_MIPS3_NOT_32R6_64R6; 610def : MipsInstAlias<"dsub $rs, $rt, $imm", 611 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, 612 InvertedImOperand64:$imm), 613 0>, ISA_MIPS3_NOT_32R6_64R6; 614def : MipsInstAlias<"dsub $rs, $imm", 615 (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, 616 InvertedImOperand64:$imm), 617 0>, ISA_MIPS3_NOT_32R6_64R6; 618def : MipsInstAlias<"dsubu $rs, $imm", 619 (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, 620 InvertedImOperand64:$imm), 621 0>, ISA_MIPS3; 622def : MipsInstAlias<"dsra $rd, $rt, $rs", 623 (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 624 ISA_MIPS3; 625def : MipsInstAlias<"dsrl $rd, $rt, $rs", 626 (DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, 627 ISA_MIPS3; 628 629// Two operand (implicit 0 selector) versions: 630def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, COP0Opnd:$rd, 0), 0>; 631def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 632def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>; 633def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>; 634 635let Predicates = [HasMips64, HasCnMips] in { 636def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>; 637def : MipsInstAlias<"syncs", (SYNC 0x6), 0>; 638def : MipsInstAlias<"syncw", (SYNC 0x4), 0>; 639def : MipsInstAlias<"syncws", (SYNC 0x5), 0>; 640} 641 642// cnMIPS Aliases. 643 644// bbit* with $p 32-63 converted to bbit*32 with $p 0-31 645def : MipsInstAlias<"bbit0 $rs, $p, $offset", 646 (BBIT032 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 647 brtarget:$offset), 0>, 648 ASE_CNMIPS; 649def : MipsInstAlias<"bbit1 $rs, $p, $offset", 650 (BBIT132 GPR64Opnd:$rs, uimm5_plus32_normalize_64:$p, 651 brtarget:$offset), 0>, 652 ASE_CNMIPS; 653 654// exts with $pos 32-63 in converted to exts32 with $pos 0-31 655def : MipsInstAlias<"exts $rt, $rs, $pos, $lenm1", 656 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 657 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 658 ASE_CNMIPS; 659def : MipsInstAlias<"exts $rt, $pos, $lenm1", 660 (EXTS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 661 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 662 ASE_CNMIPS; 663 664// cins with $pos 32-63 in converted to cins32 with $pos 0-31 665def : MipsInstAlias<"cins $rt, $rs, $pos, $lenm1", 666 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rs, 667 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 668 ASE_CNMIPS; 669def : MipsInstAlias<"cins $rt, $pos, $lenm1", 670 (CINS32 GPR64Opnd:$rt, GPR64Opnd:$rt, 671 uimm5_plus32_normalize:$pos, uimm5:$lenm1), 0>, 672 ASE_CNMIPS; 673 674//===----------------------------------------------------------------------===// 675// Assembler Pseudo Instructions 676//===----------------------------------------------------------------------===// 677 678class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> : 679 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm64), 680 !strconcat(instr_asm, "\t$rt, $imm64")> ; 681def LoadImm64 : LoadImmediate64<"dli", imm64, GPR64Opnd>; 682 683def LoadAddrReg64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins mem:$addr), 684 "dla\t$rt, $addr">; 685def LoadAddrImm64 : MipsAsmPseudoInst<(outs GPR64Opnd:$rt), (ins imm64:$imm64), 686 "dla\t$rt, $imm64">; 687