1 //===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This pass tries to replace instructions with shorter forms.  For example,
11 // IILF can be replaced with LLILL or LLILH if the constant fits and if the
12 // other 32 bits of the GR64 destination are not live.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/LivePhysRegs.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 
22 using namespace llvm;
23 
24 #define DEBUG_TYPE "systemz-shorten-inst"
25 
26 namespace {
27 class SystemZShortenInst : public MachineFunctionPass {
28 public:
29   static char ID;
30   SystemZShortenInst(const SystemZTargetMachine &tm);
31 
getPassName() const32   const char *getPassName() const override {
33     return "SystemZ Instruction Shortening";
34   }
35 
36   bool processBlock(MachineBasicBlock &MBB);
37   bool runOnMachineFunction(MachineFunction &F) override;
38 
39 private:
40   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
41   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
42   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
43   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
44   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
45   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
46 
47   const SystemZInstrInfo *TII;
48   const TargetRegisterInfo *TRI;
49   LivePhysRegs LiveRegs;
50 };
51 
52 char SystemZShortenInst::ID = 0;
53 } // end anonymous namespace
54 
createSystemZShortenInstPass(SystemZTargetMachine & TM)55 FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
56   return new SystemZShortenInst(TM);
57 }
58 
SystemZShortenInst(const SystemZTargetMachine & tm)59 SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
60   : MachineFunctionPass(ID), TII(nullptr) {}
61 
62 // Tie operands if MI has become a two-address instruction.
tieOpsIfNeeded(MachineInstr & MI)63 static void tieOpsIfNeeded(MachineInstr &MI) {
64   if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
65       !MI.getOperand(0).isTied())
66     MI.tieOperands(0, 1);
67 }
68 
69 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
70 // are the halfword immediate loads for the same word.  Try to use one of them
71 // instead of IIxF.
shortenIIF(MachineInstr & MI,unsigned LLIxL,unsigned LLIxH)72 bool SystemZShortenInst::shortenIIF(MachineInstr &MI,
73                                     unsigned LLIxL, unsigned LLIxH) {
74   unsigned Reg = MI.getOperand(0).getReg();
75   // The new opcode will clear the other half of the GR64 reg, so
76   // cancel if that is live.
77   unsigned thisSubRegIdx = (SystemZ::GRH32BitRegClass.contains(Reg) ?
78 			    SystemZ::subreg_h32 : SystemZ::subreg_l32);
79   unsigned otherSubRegIdx = (thisSubRegIdx == SystemZ::subreg_l32 ?
80 			     SystemZ::subreg_h32 : SystemZ::subreg_l32);
81   unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx,
82 						 &SystemZ::GR64BitRegClass);
83   unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
84   if (LiveRegs.contains(OtherReg))
85     return false;
86 
87   uint64_t Imm = MI.getOperand(1).getImm();
88   if (SystemZ::isImmLL(Imm)) {
89     MI.setDesc(TII->get(LLIxL));
90     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
91     return true;
92   }
93   if (SystemZ::isImmLH(Imm)) {
94     MI.setDesc(TII->get(LLIxH));
95     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
96     MI.getOperand(1).setImm(Imm >> 16);
97     return true;
98   }
99   return false;
100 }
101 
102 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
shortenOn0(MachineInstr & MI,unsigned Opcode)103 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
104   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
105     MI.setDesc(TII->get(Opcode));
106     return true;
107   }
108   return false;
109 }
110 
111 // Change MI's opcode to Opcode if register operands 0 and 1 have a
112 // 4-bit encoding.
shortenOn01(MachineInstr & MI,unsigned Opcode)113 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
114   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
115       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
116     MI.setDesc(TII->get(Opcode));
117     return true;
118   }
119   return false;
120 }
121 
122 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
123 // 4-bit encoding and if operands 0 and 1 are tied. Also ties op 0
124 // with op 1, if MI becomes 2-address.
shortenOn001(MachineInstr & MI,unsigned Opcode)125 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
126   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
127       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
128       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
129     MI.setDesc(TII->get(Opcode));
130     tieOpsIfNeeded(MI);
131     return true;
132   }
133   return false;
134 }
135 
136 // Calls shortenOn001 if CCLive is false. CC def operand is added in
137 // case of success.
shortenOn001AddCC(MachineInstr & MI,unsigned Opcode)138 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI,
139 					   unsigned Opcode) {
140   if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
141     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
142       .addReg(SystemZ::CC, RegState::ImplicitDefine);
143     return true;
144   }
145   return false;
146 }
147 
148 // MI is a vector-style conversion instruction with the operand order:
149 // destination, source, exact-suppress, rounding-mode.  If both registers
150 // have a 4-bit encoding then change it to Opcode, which has operand order:
151 // destination, rouding-mode, source, exact-suppress.
shortenFPConv(MachineInstr & MI,unsigned Opcode)152 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
153   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
154       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
155     MachineOperand Dest(MI.getOperand(0));
156     MachineOperand Src(MI.getOperand(1));
157     MachineOperand Suppress(MI.getOperand(2));
158     MachineOperand Mode(MI.getOperand(3));
159     MI.RemoveOperand(3);
160     MI.RemoveOperand(2);
161     MI.RemoveOperand(1);
162     MI.RemoveOperand(0);
163     MI.setDesc(TII->get(Opcode));
164     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
165       .addOperand(Dest)
166       .addOperand(Mode)
167       .addOperand(Src)
168       .addOperand(Suppress);
169     return true;
170   }
171   return false;
172 }
173 
174 // Process all instructions in MBB.  Return true if something changed.
processBlock(MachineBasicBlock & MBB)175 bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
176   bool Changed = false;
177 
178   // Set up the set of live registers at the end of MBB (live out)
179   LiveRegs.clear();
180   LiveRegs.addLiveOuts(&MBB);
181 
182   // Iterate backwards through the block looking for instructions to change.
183   for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
184     MachineInstr &MI = *MBBI;
185     switch (MI.getOpcode()) {
186     case SystemZ::IILF:
187       Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
188       break;
189 
190     case SystemZ::IIHF:
191       Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
192       break;
193 
194     case SystemZ::WFADB:
195       Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
196       break;
197 
198     case SystemZ::WFDDB:
199       Changed |= shortenOn001(MI, SystemZ::DDBR);
200       break;
201 
202     case SystemZ::WFIDB:
203       Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
204       break;
205 
206     case SystemZ::WLDEB:
207       Changed |= shortenOn01(MI, SystemZ::LDEBR);
208       break;
209 
210     case SystemZ::WLEDB:
211       Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
212       break;
213 
214     case SystemZ::WFMDB:
215       Changed |= shortenOn001(MI, SystemZ::MDBR);
216       break;
217 
218     case SystemZ::WFLCDB:
219       Changed |= shortenOn01(MI, SystemZ::LCDFR);
220       break;
221 
222     case SystemZ::WFLNDB:
223       Changed |= shortenOn01(MI, SystemZ::LNDFR);
224       break;
225 
226     case SystemZ::WFLPDB:
227       Changed |= shortenOn01(MI, SystemZ::LPDFR);
228       break;
229 
230     case SystemZ::WFSQDB:
231       Changed |= shortenOn01(MI, SystemZ::SQDBR);
232       break;
233 
234     case SystemZ::WFSDB:
235       Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
236       break;
237 
238     case SystemZ::WFCDB:
239       Changed |= shortenOn01(MI, SystemZ::CDBR);
240       break;
241 
242     case SystemZ::VL32:
243       // For z13 we prefer LDE over LE to avoid partial register dependencies.
244       Changed |= shortenOn0(MI, SystemZ::LDE32);
245       break;
246 
247     case SystemZ::VST32:
248       Changed |= shortenOn0(MI, SystemZ::STE);
249       break;
250 
251     case SystemZ::VL64:
252       Changed |= shortenOn0(MI, SystemZ::LD);
253       break;
254 
255     case SystemZ::VST64:
256       Changed |= shortenOn0(MI, SystemZ::STD);
257       break;
258     }
259 
260     LiveRegs.stepBackward(MI);
261   }
262 
263   return Changed;
264 }
265 
runOnMachineFunction(MachineFunction & F)266 bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
267   const SystemZSubtarget &ST = F.getSubtarget<SystemZSubtarget>();
268   TII = ST.getInstrInfo();
269   TRI = ST.getRegisterInfo();
270   LiveRegs.init(TRI);
271 
272   bool Changed = false;
273   for (auto &MBB : F)
274     Changed |= processBlock(MBB);
275 
276   return Changed;
277 }
278