1%default {"opcode":"lsl"}
2    /*
3     * Generic 64-bit shift operation.
4     */
5    /* binop/2addr vA, vB */
6    lsr     w1, wINST, #12              // w1<- B
7    ubfx    w2, wINST, #8, #4           // w2<- A
8    GET_VREG w1, w1                     // x1<- vB
9    GET_VREG_WIDE x0, w2                // x0<- vA
10    FETCH_ADVANCE_INST 1                // advance rPC, load rINST
11    and     x1, x1, #63                 // Mask low 6 bits.
12    $opcode x0, x0, x1
13    GET_INST_OPCODE ip                  // extract opcode from rINST
14    SET_VREG_WIDE x0, w2               // vAA<- result
15    GOTO_OPCODE ip                      // jump to next instruction
16    /* 10-13 instructions */
17